From fc25a3339aeb511153a787863c71363b6e953e94 Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Thu, 26 Oct 2017 15:13:03 +0200 Subject: [PATCH] traceswoasync: Implement async swo for stm32. Use for stlink. Uses dma with large buffer. Pull up swo to provide idle level on unconnected swo pin. --- src/platforms/stlink/Makefile.inc | 1 + src/platforms/stlink/platform.h | 20 ++++- src/platforms/stm32/traceswoasync.c | 133 ++++++++++++++++++++++++++++ 3 files changed, 152 insertions(+), 2 deletions(-) create mode 100644 src/platforms/stm32/traceswoasync.c diff --git a/src/platforms/stlink/Makefile.inc b/src/platforms/stlink/Makefile.inc index 18486e8..4bde36c 100644 --- a/src/platforms/stlink/Makefile.inc +++ b/src/platforms/stlink/Makefile.inc @@ -26,6 +26,7 @@ SRC += cdcacm.c \ serialno.c \ timing.c \ timing_stm32.c \ + traceswoasync.c \ stlink_common.c \ all: blackmagic.bin blackmagic_dfu.bin blackmagic_dfu.hex dfu_upgrade.bin dfu_upgrade.hex diff --git a/src/platforms/stlink/platform.h b/src/platforms/stlink/platform.h index 5cb29cc..83eb90a 100644 --- a/src/platforms/stlink/platform.h +++ b/src/platforms/stlink/platform.h @@ -68,6 +68,9 @@ #define LED_PORT_UART GPIOC #define LED_UART GPIO14 +#define PLATFORM_HAS_TRACESWO 1 +#define NUM_TRACE_PACKETS (192) /* This is an 12K buffer */ + #define TMS_SET_MODE() \ gpio_set_mode(TMS_PORT, GPIO_MODE_OUTPUT_50_MHZ, \ GPIO_CNF_OUTPUT_PUSHPULL, TMS_PIN); @@ -87,13 +90,12 @@ #define USB_ISR usb_lp_can_rx0_isr /* Interrupt priorities. Low numbers are high priority. * For now USART2 preempts USB which may spin while buffer is drained. - * TIM3 is used for traceswo capture and must be highest priority. */ #define IRQ_PRI_USB (2 << 4) #define IRQ_PRI_USBUSART (1 << 4) #define IRQ_PRI_USBUSART_TIM (3 << 4) #define IRQ_PRI_USB_VBUS (14 << 4) -#define IRQ_PRI_TIM3 (0 << 4) +#define IRQ_PRI_SWO_DMA (1 << 4) #define USBUSART USART2 #define USBUSART_CR1 USART2_CR1 @@ -115,6 +117,20 @@ int usbuart_debug_write(const char *buf, size_t len); # define DEBUG(...) #endif +/* On F103, only USART1 is on AHB2 and can reach 4.5 MBaud at 72 MHz.*/ +#define SWO_UART USART1 +#define SWO_UART_DR USART1_DR +#define SWO_UART_CLK RCC_USART1 +#define SWO_UART_PORT GPIOA +#define SWO_UART_RX_PIN GPIO10 + +/* This DMA channel is set by the USART in use */ +#define SWO_DMA_BUS DMA1 +#define SWO_DMA_CLK RCC_DMA1 +#define SWO_DMA_CHAN DMA_CHANNEL5 +#define SWO_DMA_IRQ NVIC_DMA1_CHANNEL5_IRQ +#define SWO_DMA_ISR(x) dma1_channel5_isr(x) + extern uint16_t led_idle_run; #define LED_IDLE_RUN led_idle_run #define SET_RUN_STATE(state) {running_status = (state);} diff --git a/src/platforms/stm32/traceswoasync.c b/src/platforms/stm32/traceswoasync.c new file mode 100644 index 0000000..dfa6bae --- /dev/null +++ b/src/platforms/stm32/traceswoasync.c @@ -0,0 +1,133 @@ +/* + * This file is part of the Black Magic Debug project. + * + * Based on work that is Copyright (C) 2017 Black Sphere Technologies Ltd. + * Copyright (C) 2017 Dave Marples + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* This file implements capture of the TRACESWO output using ASYNC signalling. + * + * ARM DDI 0403D - ARMv7M Architecture Reference Manual + * ARM DDI 0337I - Cortex-M3 Technical Reference Manual + * ARM DDI 0314H - CoreSight Components Technical Reference Manual + */ + +/* TDO/TRACESWO signal comes into the SWOUSART RX pin. + */ + +#include "general.h" +#include "cdcacm.h" +#include "platform.h" + +#include +#include +#include +#include +#include +#include + +/* For speed this is set to the USB transfer size */ +#define FULL_SWO_PACKET (64) +/* Default line rate....used as default for a request without baudrate */ +#define DEFAULTSPEED (2250000) + +static volatile uint32_t w; /* Packet currently received via UART */ +static volatile uint32_t r; /* Packet currently waiting to transmit to USB */ +/* Packets arrived from the SWO interface */ +static uint8_t trace_rx_buf[NUM_TRACE_PACKETS * FULL_SWO_PACKET]; +/* Packet pingpong buffer used for receiving packets */ +static uint8_t pingpong_buf[2 * FULL_SWO_PACKET]; + +void trace_buf_drain(usbd_device *dev, uint8_t ep) +{ + static volatile char inBufDrain; + + /* If we are already in this routine then we don't need to come in again */ + if (__atomic_test_and_set (&inBufDrain, __ATOMIC_RELAXED)) + return; + /* Attempt to write everything we buffered */ + if ((w != r) && (usbd_ep_write_packet(dev, ep, + &trace_rx_buf[r * FULL_SWO_PACKET], + FULL_SWO_PACKET))) + r =(r + 1) % NUM_TRACE_PACKETS; + __atomic_clear (&inBufDrain, __ATOMIC_RELAXED); +} + +void traceswo_setspeed(uint32_t baudrate) +{ + dma_disable_channel(SWO_DMA_BUS, SWO_DMA_CHAN); + usart_disable(SWO_UART); + usart_set_baudrate(SWO_UART, baudrate); + usart_set_databits(SWO_UART, 8); + usart_set_stopbits(SWO_UART, USART_STOPBITS_1); + usart_set_mode(SWO_UART, USART_MODE_RX); + usart_set_parity(SWO_UART, USART_PARITY_NONE); + usart_set_flow_control(SWO_UART, USART_FLOWCONTROL_NONE); + + /* Set up DMA channel*/ + dma_channel_reset(SWO_DMA_BUS, SWO_DMA_CHAN); + dma_set_peripheral_address(SWO_DMA_BUS, SWO_DMA_CHAN, + (uint32_t)&SWO_UART_DR); + dma_set_read_from_peripheral(SWO_DMA_BUS, SWO_DMA_CHAN); + dma_enable_memory_increment_mode(SWO_DMA_BUS, SWO_DMA_CHAN); + dma_set_peripheral_size(SWO_DMA_BUS, SWO_DMA_CHAN, DMA_CCR_PSIZE_8BIT); + dma_set_memory_size(SWO_DMA_BUS, SWO_DMA_CHAN, DMA_CCR_MSIZE_8BIT); + dma_set_priority(SWO_DMA_BUS, SWO_DMA_CHAN, DMA_CCR_PL_HIGH); + dma_enable_transfer_complete_interrupt(SWO_DMA_BUS, SWO_DMA_CHAN); + dma_enable_half_transfer_interrupt(SWO_DMA_BUS, SWO_DMA_CHAN); + dma_enable_circular_mode(SWO_DMA_BUS,SWO_DMA_CHAN); + + usart_enable(SWO_UART); + nvic_enable_irq(SWO_DMA_IRQ); + w = r = 0; + dma_set_memory_address(SWO_DMA_BUS, SWO_DMA_CHAN, (uint32_t)pingpong_buf); + dma_set_number_of_data(SWO_DMA_BUS, SWO_DMA_CHAN, 2 * FULL_SWO_PACKET); + dma_enable_channel(SWO_DMA_BUS, SWO_DMA_CHAN); + usart_enable_rx_dma(SWO_UART); +} + +void SWO_DMA_ISR(void) +{ + if (DMA_ISR(SWO_DMA_BUS) & DMA_ISR_HTIF(SWO_DMA_CHAN)) { + DMA_IFCR(SWO_DMA_BUS) |= DMA_ISR_HTIF(SWO_DMA_CHAN); + memcpy(&trace_rx_buf[w * FULL_SWO_PACKET], pingpong_buf, + FULL_SWO_PACKET); + } + if (DMA_ISR(SWO_DMA_BUS) & DMA_ISR_TCIF(SWO_DMA_CHAN)) { + DMA_IFCR(SWO_DMA_BUS) |= DMA_ISR_TCIF(SWO_DMA_CHAN); + memcpy(&trace_rx_buf[w * FULL_SWO_PACKET], + &pingpong_buf[FULL_SWO_PACKET], FULL_SWO_PACKET); + } + w = (w + 1) % NUM_TRACE_PACKETS; + trace_buf_drain(usbdev, 0x85); +} + +void traceswo_init(uint32_t baudrate) +{ + if (!baudrate) + baudrate = DEFAULTSPEED; + + rcc_periph_clock_enable(SWO_UART_CLK); + rcc_periph_clock_enable(SWO_DMA_CLK); + + gpio_set_mode(SWO_UART_PORT, GPIO_MODE_INPUT, + GPIO_CNF_INPUT_PULL_UPDOWN, SWO_UART_RX_PIN); + /* Pull SWO pin high to keep open SWO line ind uart idle state!*/ + gpio_set(SWO_UART_PORT, SWO_UART_RX_PIN); + nvic_set_priority(SWO_DMA_IRQ, IRQ_PRI_SWO_DMA); + nvic_enable_irq(SWO_DMA_IRQ); + traceswo_setspeed(baudrate); +}