From 46b9cf8c62f18d3ccbc11c34922d7f4cfa57b3ae Mon Sep 17 00:00:00 2001
From: sys64738 <sys64738@hellsite.site>
Date: Mon, 20 Jun 2022 03:55:54 +0200
Subject: [PATCH] add stuff

---
 .gitignore |  3 ++
 Makefile   | 15 +++++++++
 isa.dot    | 97 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 115 insertions(+)
 create mode 100644 .gitignore
 create mode 100644 Makefile
 create mode 100644 isa.dot

diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..db56478
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,3 @@
+*.png
+*.svg
+isa-tree.*
diff --git a/Makefile b/Makefile
new file mode 100644
index 0000000..05f6394
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,15 @@
+
+default: all
+
+DOT ?= dot
+
+isa-tree.%: isa.dot
+	$(DOT) -T$* "$<" > "$@"
+
+all: isa-tree.png isa-tree.svg
+
+clean:
+	$(RM) isa-tree.*
+
+.PHONY: all default clean
+
diff --git a/isa.dot b/isa.dot
new file mode 100644
index 0000000..f7cdcb9
--- /dev/null
+++ b/isa.dot
@@ -0,0 +1,97 @@
+digraph {
+	"4004" -> {TMS1000 "8008"}
+	TMS1000 -> {"17K" MSP430}
+	"8008" -> {"8080" "8048"}
+	"8080" -> {"8088" "8086" Z80 "87AD" LR35902 ST6}
+	"8086" -> {V60 x86}
+	Z80 -> {Z8 Z180 Z800 Z8000 LR35902 "TLCS-90" "87AD" eZ80}
+	"87AD" -> "78K0"
+	"17K" -> "78K0"
+	"78K0" -> "78K0S"
+	"78K0" -> "78K0R"
+	"78K0R" -> RL78
+	"TLCS-90" -> {"TLCS-870" "TLCS-900"}
+	Z8000 -> Z80000
+	Z180 -> Z280
+	Z800 -> Z280
+	Z280 -> Z380
+	Z8 -> eZ8
+	//eZ80 -> eZ8
+
+	"8048" -> "8051"
+
+	ST6 -> ST7
+	ST7 -> STM8
+
+	"6800" -> {"6801" "6809" "6502" "68000"}
+	"6801" -> {"68HC05" "68HC08" "68HC11"}
+	"68HC11" -> {"68HC12" "68HC16"}
+	"6502" -> "65816"
+	"68HC12" -> S12
+	S12 -> MagniV
+
+	PDP11 -> VAX
+	PDP11 -> MSP430
+	VAX -> {"68000" "V60, V70, V80" "H8/300" "DEC Alpha"}
+
+	"V60, V70, V80" -> "V810, V830"
+	"V810, V830" -> V850
+	V850 -> RH850
+
+	"68000" -> {"680x0" ColdFire "H8/300" /*"88000"*/}
+	"680x0" -> "Apollo 68080"
+
+	"H8/300" -> {"H8/300H" "H8/300L"}
+	"H8/300H" -> H8S
+	H8S -> H8SX
+
+	H8SX -> RX
+	V850 -> RX
+	RL78 -> RX
+	SuperH -> RX, ARMv4, ARCompact, "RISC-V"
+
+	"Super FX" -> ARC
+	ARC -> ARCompact
+
+	RISC -> {i960 Am29000 ARMv2 SuperH "PA-RISC" "801" ROMP SPARC DLX OpenRISC1000 AVR ARC "88000" "RISC-V"}
+	MIPS -> {PRISM OpenRISC1000 Xtensa LoongArch "RISC-V" "C-SKY"}
+
+	"801" -> PowerPC
+	ROMP -> PowerPC
+	"88000" -> PowerPC
+	DLX -> MicroBlaze
+	OpenRISC1000 -> LM32, "RISC-V"
+	SPARC -> {UltraSPARC SPARCLite}
+	SuperH -> {CR16 Xtensa}
+	PRISM -> "DEC Alpha"
+
+	ARMv2 -> ARMv4
+	ARMv4 -> ARMv5
+	ARMv5 -> ARMv6
+	ARMv6 -> {"Cortex-A" "Cortex-R" "Cortex-M"}
+	ARMv4 -> "Cortex-M"
+	"DEC Alpha" -> {StrongARM "Cortex-A"}
+	"Cortex-A" -> {"Cortex-X" Neoverse}
+
+	"PA-RISC" -> Itanium
+	x86 -> Itanium
+	PowerPC -> {Itanium "C-SKY"}
+	i960 -> Itanium
+	x86 -> AMD64
+
+	//"8051" -> AVR
+	AVR -> AVR32
+	ARMv4 -> AVR32
+	ARMv4 -> StrongARM
+	StrongARM -> XScale
+
+	SPARCLite -> FR
+	FR -> "FR-V"
+
+	"56000" -> {Teak Oak}
+	Oak -> Teak
+	Teak -> "CEVA-X"
+	TMS320 -> {"FR-V" "CEVA-X" SHARC Hexagon Xtensa}
+	SHARC -> {Blackfin TigerSHARC}
+	XScale -> Blackfin
+}