From f8852df2176355211261e8f615d0254fd66d70dd Mon Sep 17 00:00:00 2001 From: "Tadashi G. Takaoka" Date: Mon, 16 Mar 2020 22:46:40 +0900 Subject: [PATCH] Update chipinfo.db with MSPDS-OPEN-SOURCE_3.15.0.1 The chipinfo.db is extracted from MSPDS. https://www.ti.com/tool/download/MSPDS-OPEN-SOURCE The latest is MSPDS-OPEN_SOURCE_3.15.0.1. http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSPDS/3_15_0_000/export/MSPDebugStack_OS_Package_3_15_0_1.zip You can find the release note of version 3.15.0.1 at http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSPDS/3_15_0_000/export/Release_Notes.html The following msp-ds-dumpdb.patch is necessary to extract chipinfo.db from MSPDS, using msp-ds-dumpdb command. https://raw.githubusercontent.com/tgtakaoka/homebrew-mspdebug-mspds/master/patches/msp-ds-3.15.0.1-dumpdb.patch --- chipinfo.db | 1810 ++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 1806 insertions(+), 4 deletions(-) diff --git a/chipinfo.db b/chipinfo.db index ed09014..b36244c 100644 --- a/chipinfo.db +++ b/chipinfo.db @@ -1,6 +1,6 @@ /* MSP430 chip database * - * THIS FILE WAS GENERATED FROM MSP430.DLL v3.13.0.601 + * THIS FILE WAS GENERATED FROM MSP430.DLL v3.15.0.1 * * Copyright (C) 2011 - 2018 Texas Instruments Incorporated - http://www.ti.com/ * @@ -34,10 +34,10 @@ */ #define CI_DLL430_VERSION_MAJOR 3 -#define CI_DLL430_VERSION_MINOR 13 +#define CI_DLL430_VERSION_MINOR 15 #define CI_DLL430_VERSION_PATCH 0 -#define CI_DLL430_VERSION_BUILD 601 -#define CI_DLL430_VERSION_STRING "3.13.0.601" +#define CI_DLL430_VERSION_BUILD 1 +#define CI_DLL430_VERSION_STRING "3.15.0.1" static const struct chipinfo_funclet erase_xv2_fr41xx = { .code_size = 42, @@ -92986,6 +92986,1808 @@ const struct chipinfo chipinfo_db[] = { { }, }, + { + .name = "MSP430FR2676", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x000000fe, + .clock_map = { + {"ADC", 0xd6}, + {"CAPTIVATE", 0xb7}, + {"PORT", 0x50}, + {"Comparator E0", 0xa9}, + {"eUSCIA0", 0x2c}, + {"eUSCIA1", 0x2d}, + {"eUSCIB0", 0x30}, + {"eUSCIB1", 0x31}, + {"RTC", 0x8a}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A3", 0x90}, + {"Timer3_A3", 0x62}, + {"Timer0_B7", 0x9d}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8328, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + [0x4e] = 0x3f, + }, + .v3_erase = &erase_xv2_fr41xx, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x00018, + .disable_lpm5 = 0x00018, + .reg_mask_3v = 0x04020, + .enable_lpm5_3v = 0x04020, + .disable_lpm5_3v = 0x04020, + }, + .memory = { + { + .name = "Bsl2", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0xffc00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Lib", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 16384, + .offset = 0xc0000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 65536, + .offset = 0x08000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 8192, + .offset = 0x02000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 1536, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit2", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4064, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 6, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR2675", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x000000fe, + .clock_map = { + {"ADC", 0xd6}, + {"CAPTIVATE", 0xb7}, + {"PORT", 0x50}, + {"Comparator E0", 0xa9}, + {"eUSCIA0", 0x2c}, + {"eUSCIA1", 0x2d}, + {"eUSCIB0", 0x30}, + {"eUSCIB1", 0x31}, + {"RTC", 0x8a}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A3", 0x90}, + {"Timer3_A3", 0x62}, + {"Timer0_B7", 0x9d}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8329, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + [0x4e] = 0x3f, + }, + .v3_erase = &erase_xv2_fr41xx, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x00018, + .disable_lpm5 = 0x00018, + .reg_mask_3v = 0x04020, + .enable_lpm5_3v = 0x04020, + .disable_lpm5_3v = 0x04020, + }, + .memory = { + { + .name = "Bsl2", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0xffc00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Lib", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 16384, + .offset = 0xc0000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 32768, + .offset = 0x08000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 6144, + .offset = 0x02000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 1536, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit2", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4064, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 6, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR2476", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x000000fe, + .clock_map = { + {"ADC", 0xd6}, + {"CAPTIVATE", 0xb7}, + {"PORT", 0x50}, + {"Comparator E0", 0xa9}, + {"eUSCIA0", 0x2c}, + {"eUSCIA1", 0x2d}, + {"eUSCIB0", 0x30}, + {"eUSCIB1", 0x31}, + {"RTC", 0x8a}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A3", 0x90}, + {"Timer3_A3", 0x62}, + {"Timer0_B7", 0x9d}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x832a, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + [0x4e] = 0x3f, + }, + .v3_erase = &erase_xv2_fr41xx, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x00018, + .disable_lpm5 = 0x00018, + .reg_mask_3v = 0x04020, + .enable_lpm5_3v = 0x04020, + .disable_lpm5_3v = 0x04020, + }, + .memory = { + { + .name = "Bsl2", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0xffc00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Lib", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 16384, + .offset = 0xc0000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 65536, + .offset = 0x08000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 8192, + .offset = 0x02000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 1536, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit2", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4064, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 6, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR2475", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x000000fe, + .clock_map = { + {"ADC", 0xd6}, + {"CAPTIVATE", 0xb7}, + {"PORT", 0x50}, + {"Comparator E0", 0xa9}, + {"eUSCIA0", 0x2c}, + {"eUSCIA1", 0x2d}, + {"eUSCIB0", 0x30}, + {"eUSCIB1", 0x31}, + {"RTC", 0x8a}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A3", 0x90}, + {"Timer3_A3", 0x62}, + {"Timer0_B7", 0x9d}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x832b, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + [0x4e] = 0x3f, + }, + .v3_erase = &erase_xv2_fr41xx, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x00018, + .disable_lpm5 = 0x00018, + .reg_mask_3v = 0x04020, + .enable_lpm5_3v = 0x04020, + .disable_lpm5_3v = 0x04020, + }, + .memory = { + { + .name = "Bsl2", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0xffc00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Lib", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 16384, + .offset = 0xc0000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 32768, + .offset = 0x08000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x02000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 1536, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit2", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4064, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 6, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR6007", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x1000107f, + .clock_map = { + {"PORT", 0x50}, + {"ADC12B", 0xd8}, + {"Comparator E", 0xa8}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIB1", 0x31}, + {"eUSCIA1", 0x2d}, + {"eUSCIA2", 0x2e}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A2", 0x8c}, + {"Timer4_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {"eUSCIA3", 0x2f}, + {0}, + {0}, + {"AES256", 0x60}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x832e, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 262144, + .offset = 0x04000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "LeaRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x02c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit3", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x00f00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "UssPeripheral", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x00e00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit2", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 768, + .offset = 0x00b00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "LeaPeripheral", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 128, + .offset = 0x00a80, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 2656, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Eem", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 0, + .mapped = 0, + .size = 128, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR6005", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x1000107f, + .clock_map = { + {"PORT", 0x50}, + {"ADC12B", 0xd8}, + {"Comparator E", 0xa8}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIB1", 0x31}, + {"eUSCIA1", 0x2d}, + {"eUSCIA2", 0x2e}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A2", 0x8c}, + {"Timer4_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {"eUSCIA3", 0x2f}, + {0}, + {0}, + {"AES256", 0x60}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x832f, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 131072, + .offset = 0x04000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "LeaRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x02c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit3", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x00f00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "UssPeripheral", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x00e00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit2", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 768, + .offset = 0x00b00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "LeaPeripheral", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 128, + .offset = 0x00a80, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 2656, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Eem", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 0, + .mapped = 0, + .size = 128, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR2673", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x000000fe, + .clock_map = { + {"ADC", 0xd6}, + {"CAPTIVATE", 0xb7}, + {"PORT", 0x50}, + {"Comparator E0", 0xa9}, + {"eUSCIA0", 0x2c}, + {"eUSCIA1", 0x2d}, + {"eUSCIB0", 0x30}, + {"eUSCIB1", 0x31}, + {"RTC", 0x8a}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A3", 0x90}, + {"Timer3_A3", 0x62}, + {"Timer0_B7", 0x9d}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8338, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + [0x4e] = 0x3f, + }, + .v3_erase = &erase_xv2_fr41xx, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x00018, + .disable_lpm5 = 0x00018, + .reg_mask_3v = 0x04020, + .enable_lpm5_3v = 0x04020, + .disable_lpm5_3v = 0x04020, + }, + .memory = { + { + .name = "Bsl2", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0xffc00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Lib", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 16384, + .offset = 0xc0000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 16384, + .offset = 0x0c000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x02000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 1536, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit2", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4064, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 6, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR2672", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x000000fe, + .clock_map = { + {"ADC", 0xd6}, + {"CAPTIVATE", 0xb7}, + {"PORT", 0x50}, + {"Comparator E0", 0xa9}, + {"eUSCIA0", 0x2c}, + {"eUSCIA1", 0x2d}, + {"eUSCIB0", 0x30}, + {"eUSCIB1", 0x31}, + {"RTC", 0x8a}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A3", 0x90}, + {"Timer3_A3", 0x62}, + {"Timer0_B7", 0x9d}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8339, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + [0x4e] = 0x3f, + }, + .v3_erase = &erase_xv2_fr41xx, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x00018, + .disable_lpm5 = 0x00018, + .reg_mask_3v = 0x04020, + .enable_lpm5_3v = 0x04020, + .disable_lpm5_3v = 0x04020, + }, + .memory = { + { + .name = "Bsl2", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0xffc00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Lib", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 16384, + .offset = 0xc0000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 8192, + .offset = 0x0e000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x02000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 1536, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit2", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4064, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 6, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + { .name = "MSP430L092", .bits = 20,