diff --git a/drivers/hal_proto.c b/drivers/hal_proto.c
index 9ba1d4b..2af2172 100644
--- a/drivers/hal_proto.c
+++ b/drivers/hal_proto.c
@@ -198,7 +198,7 @@ int hal_proto_execute(struct hal_proto *p, uint8_t fid,
 	uint8_t fdata[HAL_MAX_PAYLOAD];
 
 	if (len + 2 > HAL_MAX_PAYLOAD) {
-		printc_err("hal_proto_execute: payload too big: %d\n", len);
+		printc_err("hal_proto_execute: fid 0x%02x: payload too big: %d\n", fid, len);
 		return -1;
 	}
 
@@ -219,8 +219,8 @@ int hal_proto_execute(struct hal_proto *p, uint8_t fid,
 			goto fail;
 
 		if ((p->type == HAL_PROTO_TYPE_EXCEPTION) && (r >= 2)) {
-			printc_err("hal_proto_execute: HAL exception: 0x%04x\n",
-				   LE_WORD(p->payload, p->length));
+			printc_err("hal_proto_execute: fid 0x%02x: HAL exception: 0x%04x\n",
+				   fid, LE_WORD(p->payload, p->length));
 			goto fail;
 		}
 
@@ -228,8 +228,8 @@ int hal_proto_execute(struct hal_proto *p, uint8_t fid,
 			break;
 
 		if (p->type != HAL_PROTO_TYPE_DATA) {
-			printc_err("hal_proto_execute: no data "
-				   "(got type 0x%02x)\n", p->type);
+			printc_err("hal_proto_execute: fid 0x%02x: no data "
+				   "(got type 0x%02x)\n", fid, p->type);
 			goto fail;
 		}
 
@@ -242,6 +242,6 @@ int hal_proto_execute(struct hal_proto *p, uint8_t fid,
 	return 0;
 
 fail:
-	printc_err("hal_proto_execute: fid: 0x%02x\n", fid);
+	printc_err("hal_proto_execute: fid: 0x%02x: failed\n", fid);
 	return -1;
 }
diff --git a/drivers/v3hil.c b/drivers/v3hil.c
index 9581f21..616b64b 100644
--- a/drivers/v3hil.c
+++ b/drivers/v3hil.c
@@ -57,7 +57,7 @@ typedef enum {
 	HAL_PROTO_FID_WRITE_ALL_CPU_REGS	,
 	HAL_PROTO_FID_PSA			,
 	HAL_PROTO_FID_EXECUTE_FUNCLET		,
-	HAL_PROTO_FID_EXECUTE_FUNCLET_JTAG	,
+	HAL_PROTO_FID_EXECUTE_FUNCLET_JTAG	, // 0x20
 	HAL_PROTO_FID_GET_DCO_FREQUENCY		,
 	HAL_PROTO_FID_GET_DCO_FREQUENCY_JTAG	,
 	HAL_PROTO_FID_GET_FLL_FREQUENCY		,
@@ -73,7 +73,7 @@ typedef enum {
 	HAL_PROTO_FID_WRITE_MEM_WORDS_X		,
 	HAL_PROTO_FID_EEM_DX_X			,
 	HAL_PROTO_FID_SINGLE_STEP_X		,
-	HAL_PROTO_FID_READ_ALL_CPU_REGS_X	,
+	HAL_PROTO_FID_READ_ALL_CPU_REGS_X	, // 0x30
 	HAL_PROTO_FID_WRITE_ALL_CPU_REGS_X	,
 	HAL_PROTO_FID_PSA_X			,
 	HAL_PROTO_FID_EXECUTE_FUNCLET_X		,
@@ -88,7 +88,7 @@ typedef enum {
 	HAL_PROTO_FID_READ_MEM_WORDS_XV2	,
 	HAL_PROTO_FID_READ_MEM_QUICK_XV2	,
 	HAL_PROTO_FID_WRITE_MEM_WORDS_XV2	,
-	HAL_PROTO_FID_EEM_DX_XV2		,
+	HAL_PROTO_FID_EEM_DX_XV2		, // 0x40
 	HAL_PROTO_FID_SINGLE_STEP_XV2		,
 	HAL_PROTO_FID_READ_ALL_CPU_REGS_XV2	,
 	HAL_PROTO_FID_WRITE_ALL_CPU_REGS_XV2	,
@@ -104,7 +104,7 @@ typedef enum {
 	HAL_PROTO_FID_RESET_XV2			,
 	HAL_PROTO_FID_WRITE_FRAM_QUICK_XV2	,
 	HAL_PROTO_FID_SEND_JTAG_MAILBOX_XV2	,
-	HAL_PROTO_FID_SINGLE_STEP_JSTATE_XV2	,
+	HAL_PROTO_FID_SINGLE_STEP_JSTATE_XV2	, // 0x50
 	HAL_PROTO_FID_POLL_JSTATE_REG_ET8	,
 	HAL_PROTO_FID_RESET_STATIC_GLOBAL_VARS	,
 	HAL_PROTO_FID_RESET_430I		,
@@ -185,8 +185,6 @@ int v3hil_set_vcc(struct v3hil *h, int vcc_mv)
 	return hal_proto_execute(&h->hal, HAL_PROTO_FID_SET_VCC, data, 2);
 }
 
-static int set_param(struct v3hil *fet, hal_proto_config_t cfg,
-		     uint32_t value);
 int v3hil_comm_init(struct v3hil *h)
 {
 	const uint8_t ver_payload = 0;
@@ -199,6 +197,40 @@ int v3hil_comm_init(struct v3hil *h)
 		return -1;
 	if (h->hal.length < 8) {
 		printc_err("warning: v3hil: short reply to version request\n");
+	} else if (h->hal.length == 40) {
+		// TODO
+		/*printc_dbg("Version:");
+		for (int i = 0; i < h->hal.length; i++)
+			printc_dbg(" %02x", h->hal.payload[i]);
+		printc_dbg("\n");*/
+		const uint16_t sw_version = r32le(h->hal.payload + 0);
+		const uint16_t sw_build = r32le(h->hal.payload + 2);
+		const uint32_t hw_thing = r32le(h->hal.payload + 4);
+		const uint32_t tool_id = r16le(h->hal.payload + 8);
+		const uint16_t core_version = r16le(h->hal.payload + 10);
+		const uint16_t hil_version = r16le(h->hal.payload + 12);
+		const uint16_t dcdc_layer_version = r16le(h->hal.payload + 14);
+		const uint16_t dcdc_mcu_version = r16le(h->hal.payload + 16);
+		const uint16_t com_version = r16le(h->hal.payload + 18);
+
+		const uint16_t hil_crc = r16le(h->hal.payload + 20);
+		const uint16_t hal_crc = r16le(h->hal.payload + 22);
+		const uint16_t dcdc_crc = r16le(h->hal.payload + 24);
+		const uint16_t core_crc = r16le(h->hal.payload + 26);
+		const uint16_t com_crc = r16le(h->hal.payload + 28);
+
+		const uint16_t fpga_version = r16le(h->hal.payload + 30);
+		const uint16_t n_rx_queues = r16le(h->hal.payload + 32);
+		const uint16_t rx_queue_size = r16le(h->hal.payload + 34);
+
+		const uint8_t major = (sw_version >> 14) + 1;
+		const uint8_t minor = (sw_version >> 8) & 0x3f;
+		const uint8_t patch = sw_version & 0xff;
+		const uint8_t build = sw_build;
+
+		printc_dbg("Version: %d.%d.%d.%d Core version: 0x%02x, HIL version: 0x%02x, HW: 0x%04x\n",
+				major, minor, patch, build,
+				core_version, hil_version, hw_thing);
 	} else {
 		const uint8_t major = h->hal.payload[1] >> 6;
 		const uint8_t minor = h->hal.payload[1] & 0x3f;