From 713541525cfad3580c755847ef10ee74aaae6bc0 Mon Sep 17 00:00:00 2001 From: Dennis de Lange Date: Mon, 4 Nov 2019 11:28:26 +0100 Subject: [PATCH] Added the FR5994 and FR5964 chips (based upon the FR5968) --- drivers/devicelist.c | 2 + drivers/devicelist.h | 2 + drivers/fet_db.c | 258 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 262 insertions(+) diff --git a/drivers/devicelist.c b/drivers/devicelist.c index 43902ba..7bc40a7 100644 --- a/drivers/devicelist.c +++ b/drivers/devicelist.c @@ -324,6 +324,8 @@ const struct device_table sdeviceID[] = {{0x65, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430FR5959, "MSP430FR5959"}, // MSP430FR5959 {{0x67, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430FR5967, "MSP430FR5967"}, // MSP430FR5967 {{0x68, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430FR5968, "MSP430FR5968"}, // MSP430FR5968 + {{0xA1, 0x82, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430FR5994, "MSP430FR5994"}, // MSP430FR5994 + {{0xA4, 0x82, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430FR5964, "MSP430FR5964"}, // MSP430FR5964 // end of device table default return value {{ 0 , -1 , -1 , -1 , -1 , -1 , -1 , -1 , -1 }, -1, NULL} }; diff --git a/drivers/devicelist.h b/drivers/devicelist.h index c473188..01ff35f 100644 --- a/drivers/devicelist.h +++ b/drivers/devicelist.h @@ -319,6 +319,8 @@ typedef enum { DT_MSP430FR5959, DT_MSP430FR5967, DT_MSP430FR5968, + DT_MSP430FR5994, + DT_MSP430FR5964 } devicetype_t; /* Mapping between device types and identification bytes. */ diff --git a/drivers/fet_db.c b/drivers/fet_db.c index 7472da3..ec9dd57 100644 --- a/drivers/fet_db.c +++ b/drivers/fet_db.c @@ -38263,6 +38263,264 @@ static const struct fet_db_record fet_db[] = {{ .name= "Prototype_MSP430F #endif +}, +{ .name= "MSP430FR5994" /* database IDX F2*/ +, .msg28_data= { 0xA1, 0x82 /* ID (off: 0)*/ + , 0xFF /* REV (off: 2)*/ + , 0xFF /* FAB (off: 3)*/ + , 0x00, 0x00, 0x00, 0x00 + , 0xFF /* SELF0 (off: 8)*/ + , 0xFF /* SELF1 (off: 9)*/ + , 0x00, 0x00, 0x00 + , 0xFF /* CONF (off: 13)*/ + , 0x00, 0x00 + , 0xFF /* FUSES (off: 16)*/ + , 0xFF } /* F PATT (off: 17)*/ + +, .msg29_params={ 0x00, 0x209, 0xEA /*, 0x4A */ } +, .msg29_data={ 0x00, 0x40, 0xFF, 0x3F, 0x04, 0x00 /* off: 0 ROM */ + , 0x00, 0x18, 0xFF, 0x19, 0x00, 0x00 /* off: 6 INFO */ + , 0x00, 0x1C, 0xFF, 0x2B /* off: 12 RAM */ + , 0x00, 0x2C, 0xFF, 0x3B /* off: 16 RAM2 (placed LEA ram here)*/ + + , 0x03, 0x00 /* off: 20 Breakpoints */ + , 0x05, 0x00 /* off: 22 Emulation */ + , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ + , 0x0F, 0x04 /* off: 26 Id devices */ + , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ + + , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ + , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ + , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ + , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ + , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ + + , 0x01, 0x00 /* off: 42 Has test Vpp*/ + , 0x03, 0x00 /* off: 44 3-> Default clock control */ + , 0x00, 0x00 + , 0x00, 0x00 + , 0x00, 0x00 + , 0x01, 0x00 /* SET */ + , 0x01, 0x00 /* SET */ + , 0x01, 0x00 /* SET */ + , 0x00, 0x00 + , 0x00, 0x00 + , 0x00, 0x00 + , 0x00, 0x00 + , 0x00, 0x00 + , 0xFF, 0x00 /* SET */ + , 0xFF, 0x00 /* SET */ + , 0xFF, 0x00 /* SET */} + +, .msg2b_len= 0x4A +, .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ + , 0x00, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ + + , 0x00, 0x00 /* off: 10 BYTE FLAGS ?? */ + + , ETWPID_WDT_A , ETWPID_TMR3_A2 + , ETWPID_TMR1_A2, ETWPID_TA3_1 + , ETWPID_TA3_0 , ETWPID_TMR0_B7 + , ETWPID_USCIA1 , ETWPID_USCIA0 + , ETWPID_USCIB0 , ETWPID_EMPTY + , ETWPID_RTC , ETWPID_ADC12_A + , ETWPID_COMP_B , ETWPID_AES128 + , ETWPID_EMPTY , ETWPID_EMPTY + + , 0x01, 0x00, 0x01, 0x01 /* off: 28 BYTE FLAGS ?? */ + + , 0x00, 0x00 + , 0x00, 0x00 + , 0x00, 0x00 + , 0x01, 0x00 /* SET */ + , 0x01, 0x00 /* SET */ + , 0x01, 0x00 /* SET */ + , 0x01, 0x00 /* SET */ + , 0x01, 0x00 /* SET */ + , 0x00, 0x00 + , 0x01, 0x00 /* SET */ + , 0x01, 0x00 /* SET */ + , 0x00, 0x00 + , 0x00, 0x00 + , 0x00, 0x00 + , 0x00, 0x00 + , 0x00, 0x00 + , 0x00, 0x00 + , 0x00, 0x00 + , 0x00, 0x00 + , 0x00, 0x00 + , 0x00, 0x00 } + + +#ifdef MSP430_STORED_INFO + +, .endian = 0xAA55 /* The value 0xaa55. */ +, .id = 0x209 /* Identification number.*/ +, .string = "MSP430FR5994" +, .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ +, .coreIpId = 0x0000 /* The CoreIP ID.*/ +, .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ + +, .mainStart = 0x4000, .mainEnd = 0x43FFF /* MAIN Memory range */ +, .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ +, .ramStart = 0x1C00, .ramEnd = 0x2BFF /* RAM Memory range.*/ +, .ram2Start = 0x2C00, .ram2End = 0x3BFF /* RAM Memory range.*//* LEA? */ +, .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ +, .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ +, .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ + +, .hasFramMemory = 1 /* FRAM Memory type */ +, .hasTestVpp = 1 /* Device has TEST/VPP.*/ + +, .nBreakpoints = 3 /* Number of breakpoints.*/ +, .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ +, .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ +, .nBreakOps = 1 /* Breakpoint Modes*/ +, .nBreakRdWr = 1 +, .nBreakRdDma = 1 +, .TrigerMask = 1 /* Trigger Mask for Breakpoint */ +, .nRegTriggerMod= 1 /* Register Trigger modes*/ +, .nStateStorage = 0 /* MSP430 has Stage Storage*/ +, .nCycleCount = 1 /* Number of cycle counters of MSP430*/ +, .nCycleCountOps= 1 /* Cycle couter modes*/ +, .nSequencer = 0 /* Msp430 has Sequencer*/ +, .clockControl = 2 /* Clock control level.*/ + +, .emulation = 0x0005 /* Emulation level.*/ +, .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ +, .eemVersion = 0x2800 /* The EEM Version Number.*/ + +#endif + +}, +{ .name= "MSP430FR5964" /* database IDX F2*/ +, .msg28_data= { 0xA4, 0x82 /* ID (off: 0)*/ + , 0xFF /* REV (off: 2)*/ + , 0xFF /* FAB (off: 3)*/ + , 0x00, 0x00, 0x00, 0x00 + , 0xFF /* SELF0 (off: 8)*/ + , 0xFF /* SELF1 (off: 9)*/ + , 0x00, 0x00, 0x00 + , 0xFF /* CONF (off: 13)*/ + , 0x00, 0x00 + , 0xFF /* FUSES (off: 16)*/ + , 0xFF } /* F PATT (off: 17)*/ + +, .msg29_params={ 0x00, 0x20A, 0xEA /*, 0x4A */ } +, .msg29_data={ 0x00, 0x40, 0xFF, 0x3F, 0x04, 0x00 /* off: 0 ROM */ + , 0x00, 0x18, 0xFF, 0x19, 0x00, 0x00 /* off: 6 INFO */ + , 0x00, 0x1C, 0xFF, 0x3B /* off: 12 RAM */ + , 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */ + + , 0x03, 0x00 /* off: 20 Breakpoints */ + , 0x05, 0x00 /* off: 22 Emulation */ + , 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/ + , 0x0F, 0x04 /* off: 26 Id devices */ + , 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */ + + , 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */ + , 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */ + , 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */ + , 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */ + , 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */ + + , 0x01, 0x00 /* off: 42 Has test Vpp*/ + , 0x03, 0x00 /* off: 44 3-> Default clock control */ + , 0x00, 0x00 + , 0x00, 0x00 + , 0x00, 0x00 + , 0x01, 0x00 /* SET */ + , 0x01, 0x00 /* SET */ + , 0x01, 0x00 /* SET */ + , 0x00, 0x00 + , 0x00, 0x00 + , 0x00, 0x00 + , 0x00, 0x00 + , 0x00, 0x00 + , 0xFF, 0x00 /* SET */ + , 0xFF, 0x00 /* SET */ + , 0xFF, 0x00 /* SET */} + +, .msg2b_len= 0x4A +, .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */ + , 0x00, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */ + + , 0x00, 0x00 /* off: 10 BYTE FLAGS ?? */ + + , ETWPID_WDT_A , ETWPID_TMR3_A2 + , ETWPID_TMR1_A2, ETWPID_TA3_1 + , ETWPID_TA3_0 , ETWPID_TMR0_B7 + , ETWPID_USCIA1 , ETWPID_USCIA0 + , ETWPID_USCIB0 , ETWPID_EMPTY + , ETWPID_RTC , ETWPID_ADC12_A + , ETWPID_COMP_B , ETWPID_AES128 + , ETWPID_EMPTY , ETWPID_EMPTY + + , 0x01, 0x00, 0x01, 0x01 /* off: 28 BYTE FLAGS ?? */ + + , 0x00, 0x00 + , 0x00, 0x00 + , 0x00, 0x00 + , 0x01, 0x00 /* SET */ + , 0x01, 0x00 /* SET */ + , 0x01, 0x00 /* SET */ + , 0x01, 0x00 /* SET */ + , 0x01, 0x00 /* SET */ + , 0x00, 0x00 + , 0x01, 0x00 /* SET */ + , 0x01, 0x00 /* SET */ + , 0x00, 0x00 + , 0x00, 0x00 + , 0x00, 0x00 + , 0x00, 0x00 + , 0x00, 0x00 + , 0x00, 0x00 + , 0x00, 0x00 + , 0x00, 0x00 + , 0x00, 0x00 + , 0x00, 0x00 } + + +#ifdef MSP430_STORED_INFO + +, .endian = 0xAA55 /* The value 0xaa55. */ +, .id = 0x20A /* Identification number.*/ +, .string = "MSP430FR5964" +, .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/ +, .coreIpId = 0x0000 /* The CoreIP ID.*/ +, .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/ + +, .mainStart = 0x4000, .mainEnd = 0x43FFF /* MAIN Memory range */ +, .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */ +, .ramStart = 0x1C00, .ramEnd = 0x3BFF /* RAM Memory range.*/ +, .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/ +, .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/ +, .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/ +, .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/ + +, .hasFramMemory = 1 /* FRAM Memory type */ +, .hasTestVpp = 1 /* Device has TEST/VPP.*/ + +, .nBreakpoints = 3 /* Number of breakpoints.*/ +, .nRegTrigger = 1 /* Number of CPU Register Trigger.*/ +, .nCombinations = 4 /* Number of EEM Trigger Combinations.*/ +, .nBreakOps = 1 /* Breakpoint Modes*/ +, .nBreakRdWr = 1 +, .nBreakRdDma = 1 +, .TrigerMask = 1 /* Trigger Mask for Breakpoint */ +, .nRegTriggerMod= 1 /* Register Trigger modes*/ +, .nStateStorage = 0 /* MSP430 has Stage Storage*/ +, .nCycleCount = 1 /* Number of cycle counters of MSP430*/ +, .nCycleCountOps= 1 /* Cycle couter modes*/ +, .nSequencer = 0 /* Msp430 has Sequencer*/ +, .clockControl = 2 /* Clock control level.*/ + +, .emulation = 0x0005 /* Emulation level.*/ +, .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/ +, .eemVersion = 0x2800 /* The EEM Version Number.*/ + +#endif + }, };