diff --git a/chipinfo.db b/chipinfo.db
index d5e0f12..d7d69a9 100644
--- a/chipinfo.db
+++ b/chipinfo.db
@@ -59231,6 +59231,657 @@ const struct chipinfo chipinfo_db[] = {	{
 		},
 	},
 
+	{
+		.name		= "MSP430FR5959",
+		.bits		= 20,
+		.psa		= CHIPINFO_PSA_REGULAR,
+		.clock_control	= 0x02,
+		.mclk_control	= 0xbdff,
+		.clock_map	= {
+			{"Timer1_A2", 0x06},
+			{0},
+			{"AES128", 0x04},
+			{"Comparator D", 0x2b},
+			{"ADC12B", 0x38},
+			{"RTC", 0x28},
+			{0},
+			{"eUSCIB0", 0x27},
+			{"eUSCIA1", 0x24},
+			{"eUSCIA0", 0x23},
+			{"Timer0_B7", 0x1c},
+			{"Timer0_A3", 0x08},
+			{"Timer1_A3", 0x09},
+			{"Timer2_A3", 0x0a},
+			{"Timer0_A2", 0x05},
+			{"Watchdog Timer", 0x01},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+		},
+		.id		= {
+			.ver_id		= 0x8165,
+			.ver_sub_id	= 0x0000,
+			.revision	= 0x30,
+			.fab		= 0x00,
+			.self		= 0x0000,
+			.config		= 0x00,
+			.fuses		= 0x00,
+			.activation_key	= 0x00000000,
+		},
+		.id_mask		= {
+			.ver_id		= 0xffff,
+			.ver_sub_id	= 0xffff,
+			.revision	= 0xff,
+			.fab		= 0x00,
+			.self		= 0x0000,
+			.config		= 0x00,
+			.fuses		= 0x00,
+			.activation_key	= 0x00000000,
+		},
+		.eem		= {
+			.state_storage		= 0x00,
+			.cycle_counter		= 0x01,
+			.cycle_counter_ops	= 0x01,
+			.trig_emulation_level	= 0x05,
+			.trig_mem		= 0x03,
+			.trig_reg		= 0x01,
+			.trig_combinations	= 0x04,
+			.trig_options		= 0x01,
+			.trig_dma		= 0x01,
+			.trig_read_write	= 0x01,
+			.trig_reg_ops		= 0x01,
+			.trig_comp_level	= 0x02,
+			.trig_mem_cond_level	= 0x00,
+			.trig_mem_umask_level	= 0x00,
+			.seq_states		= 0x00,
+			.seq_start		= 0x00,
+			.seq_end		= 0x00,
+			.seq_reset		= 0x00,
+			.seq_blocked		= 0x00,
+		},
+		.voltage	= {
+			.vcc_min	= 1800,
+			.vcc_max	= 3600,
+			.vcc_flash_min	= 1800,
+			.vcc_secure_min	= 2500,
+			.vpp_secure_min	= 6000,
+			.vpp_secure_max	= 7000,
+			.has_test_vpp	= 1,
+		},
+		.v3_functions	= {
+			[0x09]	= 0x38,
+			[0x0a]	= 0x0a,
+			[0x11]	= 0x39,
+			[0x12]	= 0x3a,
+			[0x13]	= 0x3b,
+			[0x14]	= 0x3c,
+			[0x15]	= 0x3c,
+			[0x16]	= 0x3d,
+			[0x17]	= 0x3e,
+			[0x18]	= 0x3e,
+			[0x19]	= 0x3f,
+			[0x1b]	= 0x40,
+			[0x1c]	= 0x41,
+			[0x1d]	= 0x42,
+			[0x1e]	= 0x43,
+			[0x1f]	= 0x44,
+			[0x25]	= 0x36,
+		},
+		.v3_erase	= &erase_xv2_fram,
+		.v3_write	= &write_xv2_fram,
+		.clock_sys	= CHIPINFO_CLOCK_SYS_MOD_OSC,
+		.features	= 0
+			| CHIPINFO_FEATURE_LCFE
+			| CHIPINFO_FEATURE_QUICK_MEM_READ
+			| CHIPINFO_FEATURE_FRAM,
+		.power		= {
+			.reg_mask		= 0x10018,
+			.enable_lpm5		= 0x10018,
+			.disable_lpm5		= 0x10000,
+			.reg_mask_3v		= 0x0c020,
+			.enable_lpm5_3v		= 0x04020,
+			.disable_lpm5_3v	= 0x04020,
+		},
+		.memory		= {
+			{
+				.name		= "main",
+				.type		= CHIPINFO_MEMTYPE_RAM,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 64512,
+				.offset		= 0x04400,
+				.seg_size	= 1,
+				.bank_size	= 0,
+				.banks		= 1,
+			},
+			{
+				.name		= "information",
+				.type		= CHIPINFO_MEMTYPE_RAM,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 512,
+				.offset		= 0x01800,
+				.seg_size	= 1,
+				.bank_size	= 0,
+				.banks		= 1,
+			},
+			{
+				.name		= "boot",
+				.type		= CHIPINFO_MEMTYPE_ROM,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 2048,
+				.offset		= 0x01000,
+				.seg_size	= 1,
+				.bank_size	= 0,
+				.banks		= 1,
+			},
+			{
+				.name		= "bootcode",
+				.type		= CHIPINFO_MEMTYPE_ROM,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 256,
+				.offset		= 0x01a00,
+				.seg_size	= 1,
+				.bank_size	= 0,
+				.banks		= 1,
+			},
+			{
+				.name		= "system",
+				.type		= CHIPINFO_MEMTYPE_RAM,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 2048,
+				.offset		= 0x01c00,
+				.seg_size	= 1,
+				.bank_size	= 0,
+				.banks		= 1,
+			},
+			{
+				.name		= "peripheral16bit",
+				.type		= CHIPINFO_MEMTYPE_REGISTER,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 4096,
+				.offset		= 0x00000,
+				.seg_size	= 1,
+				.bank_size	= 0,
+				.banks		= 1,
+			},
+			{
+				.name		= "CPU",
+				.type		= CHIPINFO_MEMTYPE_REGISTER,
+				.bits		= 0,
+				.mapped		= 0,
+				.size		= 16,
+				.offset		= 0x00000,
+				.seg_size	= 1,
+				.bank_size	= 0,
+				.banks		= 1,
+			},
+			{
+				.name		= "EEM",
+				.type		= CHIPINFO_MEMTYPE_REGISTER,
+				.bits		= 0,
+				.mapped		= 0,
+				.size		= 128,
+				.offset		= 0x00000,
+				.seg_size	= 1,
+				.bank_size	= 0,
+				.banks		= 1,
+			},
+			{0}
+		},
+	},
+
+	{
+		.name		= "MSP430FR5959",
+		.bits		= 20,
+		.psa		= CHIPINFO_PSA_REGULAR,
+		.clock_control	= 0x02,
+		.mclk_control	= 0xbdff,
+		.clock_map	= {
+			{"Timer1_A2", 0x06},
+			{0},
+			{"AES128", 0x04},
+			{"Comparator D", 0x2b},
+			{"ADC12B", 0x38},
+			{"RTC", 0x28},
+			{0},
+			{"eUSCIB0", 0x27},
+			{"eUSCIA1", 0x24},
+			{"eUSCIA0", 0x23},
+			{"Timer0_B7", 0x1c},
+			{"Timer0_A3", 0x08},
+			{"Timer1_A3", 0x09},
+			{"Timer2_A3", 0x0a},
+			{"Timer0_A2", 0x05},
+			{"Watchdog Timer", 0x01},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+		},
+		.id		= {
+			.ver_id		= 0x8165,
+			.ver_sub_id	= 0x0000,
+			.revision	= 0x31,
+			.fab		= 0x00,
+			.self		= 0x0000,
+			.config		= 0x00,
+			.fuses		= 0x00,
+			.activation_key	= 0x00000000,
+		},
+		.id_mask		= {
+			.ver_id		= 0xffff,
+			.ver_sub_id	= 0xffff,
+			.revision	= 0xff,
+			.fab		= 0x00,
+			.self		= 0x0000,
+			.config		= 0x00,
+			.fuses		= 0x00,
+			.activation_key	= 0x00000000,
+		},
+		.eem		= {
+			.state_storage		= 0x00,
+			.cycle_counter		= 0x01,
+			.cycle_counter_ops	= 0x01,
+			.trig_emulation_level	= 0x05,
+			.trig_mem		= 0x03,
+			.trig_reg		= 0x01,
+			.trig_combinations	= 0x04,
+			.trig_options		= 0x01,
+			.trig_dma		= 0x01,
+			.trig_read_write	= 0x01,
+			.trig_reg_ops		= 0x01,
+			.trig_comp_level	= 0x02,
+			.trig_mem_cond_level	= 0x00,
+			.trig_mem_umask_level	= 0x00,
+			.seq_states		= 0x00,
+			.seq_start		= 0x00,
+			.seq_end		= 0x00,
+			.seq_reset		= 0x00,
+			.seq_blocked		= 0x00,
+		},
+		.voltage	= {
+			.vcc_min	= 1800,
+			.vcc_max	= 3600,
+			.vcc_flash_min	= 1800,
+			.vcc_secure_min	= 2500,
+			.vpp_secure_min	= 6000,
+			.vpp_secure_max	= 7000,
+			.has_test_vpp	= 1,
+		},
+		.v3_functions	= {
+			[0x09]	= 0x38,
+			[0x0a]	= 0x49,
+			[0x11]	= 0x39,
+			[0x12]	= 0x3a,
+			[0x13]	= 0x3b,
+			[0x14]	= 0x3c,
+			[0x15]	= 0x3c,
+			[0x16]	= 0x3d,
+			[0x17]	= 0x3e,
+			[0x18]	= 0x3e,
+			[0x19]	= 0x3f,
+			[0x1b]	= 0x4f,
+			[0x1c]	= 0x41,
+			[0x1d]	= 0x42,
+			[0x1e]	= 0x43,
+			[0x1f]	= 0x44,
+			[0x25]	= 0x36,
+		},
+		.v3_erase	= &erase_xv2_fram,
+		.v3_write	= &write_xv2_fram,
+		.clock_sys	= CHIPINFO_CLOCK_SYS_MOD_OSC,
+		.features	= 0
+			| CHIPINFO_FEATURE_LCFE
+			| CHIPINFO_FEATURE_QUICK_MEM_READ
+			| CHIPINFO_FEATURE_FRAM,
+		.power		= {
+			.reg_mask		= 0x10018,
+			.enable_lpm5		= 0x10018,
+			.disable_lpm5		= 0x10000,
+			.reg_mask_3v		= 0x0c020,
+			.enable_lpm5_3v		= 0x0c020,
+			.disable_lpm5_3v	= 0x04020,
+		},
+		.memory		= {
+			{
+				.name		= "main",
+				.type		= CHIPINFO_MEMTYPE_RAM,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 64512,
+				.offset		= 0x04400,
+				.seg_size	= 1,
+				.bank_size	= 0,
+				.banks		= 1,
+			},
+			{
+				.name		= "information",
+				.type		= CHIPINFO_MEMTYPE_RAM,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 512,
+				.offset		= 0x01800,
+				.seg_size	= 1,
+				.bank_size	= 0,
+				.banks		= 1,
+			},
+			{
+				.name		= "boot",
+				.type		= CHIPINFO_MEMTYPE_ROM,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 2048,
+				.offset		= 0x01000,
+				.seg_size	= 1,
+				.bank_size	= 0,
+				.banks		= 1,
+			},
+			{
+				.name		= "bootcode",
+				.type		= CHIPINFO_MEMTYPE_ROM,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 256,
+				.offset		= 0x01a00,
+				.seg_size	= 1,
+				.bank_size	= 0,
+				.banks		= 1,
+			},
+			{
+				.name		= "system",
+				.type		= CHIPINFO_MEMTYPE_RAM,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 2048,
+				.offset		= 0x01c00,
+				.seg_size	= 1,
+				.bank_size	= 0,
+				.banks		= 1,
+			},
+			{
+				.name		= "peripheral16bit",
+				.type		= CHIPINFO_MEMTYPE_REGISTER,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 4096,
+				.offset		= 0x00000,
+				.seg_size	= 1,
+				.bank_size	= 0,
+				.banks		= 1,
+			},
+			{
+				.name		= "CPU",
+				.type		= CHIPINFO_MEMTYPE_REGISTER,
+				.bits		= 0,
+				.mapped		= 0,
+				.size		= 16,
+				.offset		= 0x00000,
+				.seg_size	= 1,
+				.bank_size	= 0,
+				.banks		= 1,
+			},
+			{
+				.name		= "EEM",
+				.type		= CHIPINFO_MEMTYPE_REGISTER,
+				.bits		= 0,
+				.mapped		= 0,
+				.size		= 128,
+				.offset		= 0x00000,
+				.seg_size	= 1,
+				.bank_size	= 0,
+				.banks		= 1,
+			},
+			{0}
+		},
+	},
+
+	{
+		.name		= "MSP430FR5959",
+		.bits		= 20,
+		.psa		= CHIPINFO_PSA_REGULAR,
+		.clock_control	= 0x02,
+		.mclk_control	= 0xbdff,
+		.clock_map	= {
+			{"Timer1_A2", 0x06},
+			{0},
+			{"AES128", 0x04},
+			{"Comparator D", 0x2b},
+			{"ADC12B", 0x38},
+			{"RTC", 0x28},
+			{0},
+			{"eUSCIB0", 0x27},
+			{"eUSCIA1", 0x24},
+			{"eUSCIA0", 0x23},
+			{"Timer0_B7", 0x1c},
+			{"Timer0_A3", 0x08},
+			{"Timer1_A3", 0x09},
+			{"Timer2_A3", 0x0a},
+			{"Timer0_A2", 0x05},
+			{"Watchdog Timer", 0x01},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+		},
+		.id		= {
+			.ver_id		= 0x8165,
+			.ver_sub_id	= 0x0000,
+			.revision	= 0x40,
+			.fab		= 0x00,
+			.self		= 0x0000,
+			.config		= 0x00,
+			.fuses		= 0x00,
+			.activation_key	= 0x00000000,
+		},
+		.id_mask		= {
+			.ver_id		= 0xffff,
+			.ver_sub_id	= 0xffff,
+			.revision	= 0xff,
+			.fab		= 0x00,
+			.self		= 0x0000,
+			.config		= 0x00,
+			.fuses		= 0x00,
+			.activation_key	= 0x00000000,
+		},
+		.eem		= {
+			.state_storage		= 0x00,
+			.cycle_counter		= 0x01,
+			.cycle_counter_ops	= 0x01,
+			.trig_emulation_level	= 0x05,
+			.trig_mem		= 0x03,
+			.trig_reg		= 0x01,
+			.trig_combinations	= 0x04,
+			.trig_options		= 0x01,
+			.trig_dma		= 0x01,
+			.trig_read_write	= 0x01,
+			.trig_reg_ops		= 0x01,
+			.trig_comp_level	= 0x02,
+			.trig_mem_cond_level	= 0x00,
+			.trig_mem_umask_level	= 0x00,
+			.seq_states		= 0x00,
+			.seq_start		= 0x00,
+			.seq_end		= 0x00,
+			.seq_reset		= 0x00,
+			.seq_blocked		= 0x00,
+		},
+		.voltage	= {
+			.vcc_min	= 1800,
+			.vcc_max	= 3600,
+			.vcc_flash_min	= 1800,
+			.vcc_secure_min	= 2500,
+			.vpp_secure_min	= 6000,
+			.vpp_secure_max	= 7000,
+			.has_test_vpp	= 1,
+		},
+		.v3_functions	= {
+			[0x09]	= 0x38,
+			[0x0a]	= 0x49,
+			[0x11]	= 0x39,
+			[0x12]	= 0x3a,
+			[0x13]	= 0x3b,
+			[0x14]	= 0x3c,
+			[0x15]	= 0x3c,
+			[0x16]	= 0x3d,
+			[0x17]	= 0x3e,
+			[0x18]	= 0x3e,
+			[0x19]	= 0x3f,
+			[0x1b]	= 0x4f,
+			[0x1c]	= 0x41,
+			[0x1d]	= 0x42,
+			[0x1e]	= 0x43,
+			[0x1f]	= 0x44,
+			[0x25]	= 0x36,
+		},
+		.v3_erase	= &erase_xv2_fram,
+		.v3_write	= &write_xv2_fram,
+		.clock_sys	= CHIPINFO_CLOCK_SYS_MOD_OSC,
+		.features	= 0
+			| CHIPINFO_FEATURE_LCFE
+			| CHIPINFO_FEATURE_QUICK_MEM_READ
+			| CHIPINFO_FEATURE_FRAM,
+		.power		= {
+			.reg_mask		= 0x10018,
+			.enable_lpm5		= 0x10018,
+			.disable_lpm5		= 0x10000,
+			.reg_mask_3v		= 0x0c020,
+			.enable_lpm5_3v		= 0x0c020,
+			.disable_lpm5_3v	= 0x04020,
+		},
+		.memory		= {
+			{
+				.name		= "main",
+				.type		= CHIPINFO_MEMTYPE_RAM,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 64512,
+				.offset		= 0x04400,
+				.seg_size	= 1,
+				.bank_size	= 0,
+				.banks		= 1,
+			},
+			{
+				.name		= "information",
+				.type		= CHIPINFO_MEMTYPE_RAM,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 512,
+				.offset		= 0x01800,
+				.seg_size	= 1,
+				.bank_size	= 0,
+				.banks		= 1,
+			},
+			{
+				.name		= "boot",
+				.type		= CHIPINFO_MEMTYPE_ROM,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 2048,
+				.offset		= 0x01000,
+				.seg_size	= 1,
+				.bank_size	= 0,
+				.banks		= 1,
+			},
+			{
+				.name		= "bootcode",
+				.type		= CHIPINFO_MEMTYPE_ROM,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 256,
+				.offset		= 0x01a00,
+				.seg_size	= 1,
+				.bank_size	= 0,
+				.banks		= 1,
+			},
+			{
+				.name		= "system",
+				.type		= CHIPINFO_MEMTYPE_RAM,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 2048,
+				.offset		= 0x01c00,
+				.seg_size	= 1,
+				.bank_size	= 0,
+				.banks		= 1,
+			},
+			{
+				.name		= "peripheral16bit",
+				.type		= CHIPINFO_MEMTYPE_REGISTER,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 4096,
+				.offset		= 0x00000,
+				.seg_size	= 1,
+				.bank_size	= 0,
+				.banks		= 1,
+			},
+			{
+				.name		= "CPU",
+				.type		= CHIPINFO_MEMTYPE_REGISTER,
+				.bits		= 0,
+				.mapped		= 0,
+				.size		= 16,
+				.offset		= 0x00000,
+				.seg_size	= 1,
+				.bank_size	= 0,
+				.banks		= 1,
+			},
+			{
+				.name		= "EEM",
+				.type		= CHIPINFO_MEMTYPE_REGISTER,
+				.bits		= 0,
+				.mapped		= 0,
+				.size		= 128,
+				.offset		= 0x00000,
+				.seg_size	= 1,
+				.bank_size	= 0,
+				.banks		= 1,
+			},
+			{0}
+		},
+	},
+
 	{
 		.name		= "MSP430FR5969",
 		.bits		= 20,
@@ -59274,7 +59925,7 @@ const struct chipinfo chipinfo_db[] = {	{
 		.id		= {
 			.ver_id		= 0x8169,
 			.ver_sub_id	= 0x0000,
-			.revision	= 0x12,
+			.revision	= 0x30,
 			.fab		= 0x00,
 			.self		= 0x0000,
 			.config		= 0x00,
@@ -59491,7 +60142,7 @@ const struct chipinfo chipinfo_db[] = {	{
 		.id		= {
 			.ver_id		= 0x8169,
 			.ver_sub_id	= 0x0000,
-			.revision	= 0x20,
+			.revision	= 0x31,
 			.fab		= 0x00,
 			.self		= 0x0000,
 			.config		= 0x00,
@@ -59708,7 +60359,7 @@ const struct chipinfo chipinfo_db[] = {	{
 		.id		= {
 			.ver_id		= 0x8169,
 			.ver_sub_id	= 0x0000,
-			.revision	= 0x21,
+			.revision	= 0x40,
 			.fab		= 0x00,
 			.self		= 0x0000,
 			.config		= 0x00,
@@ -59882,6 +60533,7 @@ const struct chipinfo chipinfo_db[] = {	{
 		},
 	},
 
+
 	{
 		.name		= "MSP430F6734",
 		.bits		= 20,