diff --git a/chipinfo.db b/chipinfo.db index d7d69a9..37d776f 100644 --- a/chipinfo.db +++ b/chipinfo.db @@ -1,8 +1,8 @@ /* MSP430 chip database * - * THIS FILE WAS GENERATED FROM MSP430.DLL v3.3.1.4 + * THIS FILE WAS GENERATED FROM MSP430.DLL v3.12.0.604 * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011 - 2018 Texas Instruments Incorporated - http://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -34,10 +34,29 @@ */ #define CI_DLL430_VERSION_MAJOR 3 -#define CI_DLL430_VERSION_MINOR 3 -#define CI_DLL430_VERSION_PATCH 1 -#define CI_DLL430_VERSION_BUILD 4 -#define CI_DLL430_VERSION_STRING "3.3.1.4" +#define CI_DLL430_VERSION_MINOR 12 +#define CI_DLL430_VERSION_PATCH 0 +#define CI_DLL430_VERSION_BUILD 604 +#define CI_DLL430_VERSION_STRING "3.12.0.604" + +static const struct chipinfo_funclet erase_xv2_fr41xx = { + .code_size = 42, + .max_payload = 0, + .entry_point = 0x0000, + .code = { + 0x40b2, 0x5a80, 0x01cc, 0x40b2, + 0x00d0, 0x0146, 0x40b2, 0xabad, + 0x014e, 0x40b2, 0xbabe, 0x014c, + 0xb3a2, 0x0146, 0x27fd, 0x90b2, + 0xbeef, 0x0148, 0x23f9, 0x90b2, + 0xdead, 0x014a, 0x23f5, 0x1800, + 0x454a, 0x1800, 0x464b, 0x43ba, + 0x0000, 0x1800, 0x536a, 0x1800, + 0x836b, 0x930b, 0x23f8, 0x40b2, + 0xcafe, 0x014e, 0x40b2, 0xbabe, + 0x014c, 0x3fff, + } +}; static const struct chipinfo_funclet erase_fll = { .code_size = 48, @@ -73,8 +92,8 @@ static const struct chipinfo_funclet erase_dco = { 0x450c, 0x40bc, 0xdead, 0x0000, 0x403c, 0x227a, 0x831c, 0x23fe, 0x40b2, 0xa500, 0x0128, 0x831b, - 0x23f1, 0x40f2, 0x0087, 0x0057, - 0x3c05, 0x0000, 0x0000, 0x0000, + 0x23f1, 0x3c08, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3fff, 0x4303, } }; @@ -134,8 +153,8 @@ static const struct chipinfo_funclet write_dco = { 0xb392, 0x012c, 0x23fd, 0x40b2, 0xa500, 0x0128, 0x40b2, 0xa500, 0x012c, 0x532b, 0x532c, 0x8316, - 0x23ee, 0x40f2, 0x0087, 0x0057, - 0x3c01, 0x0000, 0x3fff, 0x4303, + 0x23ee, 0x3c04, 0x0000, 0x0000, + 0x0000, 0x0000, 0x3fff, 0x4303, } }; @@ -177,8 +196,8 @@ static const struct chipinfo_funclet erase_xdco = { 0x40bc, 0xdead, 0x0000, 0x1840, 0x403c, 0x227a, 0x832c, 0x23fe, 0x1840, 0x40b2, 0xa500, 0x0128, - 0x832b, 0x23ec, 0x40f2, 0x0087, - 0x0057, 0x3c02, 0x0000, 0x0000, + 0x832b, 0x23ec, 0x3c05, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x3fff, 0x4303, } }; @@ -221,8 +240,8 @@ static const struct chipinfo_funclet write_xdco = { 0x4bac, 0x0000, 0xb392, 0x012c, 0x23fd, 0x40b2, 0xa500, 0x0128, 0x40b2, 0xa500, 0x012c, 0x03eb, - 0x03ec, 0x8316, 0x23ee, 0x40f2, - 0x0087, 0x0057, 0x3c01, 0x0000, + 0x03ec, 0x8316, 0x23ee, 0x3c04, + 0x0000, 0x0000, 0x0000, 0x0000, 0x3fff, 0x4303, } }; @@ -420,148 +439,11 @@ static const struct chipinfo_funclet write_xv2_word = { }; const struct chipinfo chipinfo_db[] = { { - .name = "DeviceUnknown", - .bits = 20, - .psa = CHIPINFO_PSA_REGULAR, - .clock_control = 0x00, - .mclk_control = 0x0000, - .clock_map = { - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - }, - .id = { - .ver_id = 0x0000, - .ver_sub_id = 0x0000, - .revision = 0xff, - .fab = 0xff, - .self = 0xffff, - .config = 0xff, - .fuses = 0xff, - .activation_key = 0x00000000, - }, - .id_mask = { - .ver_id = 0xffff, - .ver_sub_id = 0xffff, - .revision = 0xff, - .fab = 0xff, - .self = 0xffff, - .config = 0xff, - .fuses = 0xff, - .activation_key = 0x00000000, - }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, - .voltage = { - .vcc_min = 1800, - .vcc_max = 3600, - .vcc_flash_min = 2700, - .vcc_secure_min = 2500, - .vpp_secure_min = 6000, - .vpp_secure_max = 7000, - .has_test_vpp = 0, - }, - .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, - [0x12] = 0x3a, - [0x13] = 0x3b, - [0x14] = 0x3c, - [0x15] = 0x3c, - [0x16] = 0x3d, - [0x17] = 0x3e, - [0x18] = 0x3e, - [0x19] = 0x3f, - [0x1b] = 0x40, - [0x1c] = 0x41, - [0x1d] = 0x42, - [0x1e] = 0x43, - [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, - }, - .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, - .features = 0 - | CHIPINFO_FEATURE_LCFE - | CHIPINFO_FEATURE_QUICK_MEM_READ, - .power = { - .reg_mask = 0x00000, - .enable_lpm5 = 0x00000, - .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x00000, - .enable_lpm5_3v = 0x00000, - .disable_lpm5_3v = 0x00000, - }, - .memory = { - { - .name = "DeviceUnknown", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 0, - .offset = 0x00000, - .seg_size = 0, - .bank_size = 0, - .banks = 1, - }, - {0} - }, - }, - - { .name = "F20x1_G2x0x_G2x1x", .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -616,27 +498,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -653,8 +515,7 @@ const struct chipinfo chipinfo_db[] = { { .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE - | CHIPINFO_FEATURE_QUICK_MEM_READ - | CHIPINFO_FEATURE_NO_BSL, + | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, @@ -665,91 +526,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x0f800, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, - .bank_size = 64, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 128, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -761,7 +600,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -816,27 +655,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -853,8 +672,7 @@ const struct chipinfo chipinfo_db[] = { { .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE - | CHIPINFO_FEATURE_QUICK_MEM_READ - | CHIPINFO_FEATURE_NO_BSL, + | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, @@ -865,91 +683,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x0f800, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, - .bank_size = 64, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 128, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -961,7 +757,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -1016,27 +812,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -1053,8 +829,7 @@ const struct chipinfo chipinfo_db[] = { { .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE - | CHIPINFO_FEATURE_QUICK_MEM_READ - | CHIPINFO_FEATURE_NO_BSL, + | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, @@ -1065,91 +840,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x0f800, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, - .bank_size = 64, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 128, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -1161,7 +914,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x00, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -1216,27 +969,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -1251,7 +984,8 @@ const struct chipinfo chipinfo_db[] = { { .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_1XX, - .features = 0, + .features = 0 + | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, @@ -1262,91 +996,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x0f000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, - .bank_size = 128, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -1358,7 +1070,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x00, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -1413,27 +1125,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -1448,7 +1140,8 @@ const struct chipinfo chipinfo_db[] = { { .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_1XX, - .features = 0, + .features = 0 + | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, @@ -1459,91 +1152,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x0f000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, - .bank_size = 128, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -1555,24 +1226,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, + {"Comparator B", 0xa8}, {0}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"USB", 0x03}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"USB", 0x40}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -1610,27 +1281,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -1641,27 +1292,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -1677,102 +1327,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -1784,7 +1412,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -1839,27 +1467,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -1887,91 +1495,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, - .bank_size = 64, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -1983,7 +1569,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -2038,27 +1624,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x03, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -2086,91 +1652,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, - .bank_size = 64, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -2182,7 +1726,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -2237,27 +1781,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x03, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -2285,91 +1809,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x0f000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, - .bank_size = 64, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -2381,7 +1883,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -2436,27 +1938,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x03, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -2484,91 +1966,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x0f800, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, - .bank_size = 64, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -2580,7 +2040,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -2635,27 +2095,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -2666,8 +2106,8 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x1f] = 0x20, - [0x21] = 0x24, + [0x20] = 0x21, + [0x22] = 0x25, }, .v3_erase = &erase_fll, .v3_write = &write_fll, @@ -2686,102 +2126,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, - .bank_size = 128, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 13, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 13, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -2793,24 +2211,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, + {"Comparator B", 0xa8}, {0}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"USB", 0x03}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"USB", 0x40}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -2848,27 +2266,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -2879,27 +2277,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -2915,102 +2312,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 65536, .offset = 0x04400, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -3022,24 +2397,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, + {"Comparator B", 0xa8}, {0}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"USB", 0x03}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"USB", 0x40}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -3077,27 +2452,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -3108,27 +2463,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -3144,102 +2498,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 65536, .offset = 0x04400, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -3251,24 +2583,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, + {"Comparator B", 0xa8}, {0}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"USB", 0x03}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"USB", 0x40}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -3306,27 +2638,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -3337,27 +2649,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -3373,102 +2684,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 98304, .offset = 0x04400, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 3, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 6144, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 3, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -3480,24 +2769,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000040f, .clock_map = { {0}, {0}, {0}, {0}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, {0}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -3535,27 +2824,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -3566,27 +2835,27 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + [0x4d] = 0x59, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -3602,91 +2871,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x05c00, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -3698,24 +2945,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000040f, .clock_map = { {0}, {0}, {0}, {0}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -3753,27 +3000,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -3784,27 +3011,27 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + [0x4d] = 0x59, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -3820,91 +3047,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x05c00, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -3916,24 +3121,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, + {"Comparator B", 0xa8}, {0}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"USB", 0x03}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"USB", 0x40}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -3971,27 +3176,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -4002,27 +3187,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -4038,102 +3222,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x04400, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -4145,7 +3307,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x03, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -4200,27 +3362,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -4231,8 +3373,9 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x49] = 0x53, - [0x4c] = 0x52, + [0x09] = 0x58, + [0x4a] = 0x54, + [0x4d] = 0x53, }, .v3_erase = &erase_dco, .v3_write = &write_430i, @@ -4250,91 +3393,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 1024, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x01000, .seg_size = 1024, - .bank_size = 1024, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -4346,24 +3467,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"USB", 0x03}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"USB", 0x40}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -4401,27 +3522,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -4432,27 +3533,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -4468,102 +3568,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -4575,24 +3653,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"USB", 0x03}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"USB", 0x40}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -4630,27 +3708,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -4661,27 +3719,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -4697,102 +3754,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -4804,7 +3839,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x00, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -4859,27 +3894,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -4890,8 +3905,8 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x1f] = 0x20, - [0x21] = 0x22, + [0x20] = 0x21, + [0x22] = 0x23, }, .v3_erase = &erase_dco, .v3_write = &write_dco, @@ -4908,91 +3923,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, - .bank_size = 128, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -5004,24 +3997,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"USB", 0x03}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"USB", 0x40}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -5059,27 +4052,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -5090,27 +4063,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -5126,102 +4098,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 65536, .offset = 0x04400, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -5233,24 +4183,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"USB", 0x03}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"USB", 0x40}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -5288,27 +4238,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -5319,27 +4249,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -5355,102 +4284,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 65536, .offset = 0x04400, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -5462,24 +4369,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x00002407, .clock_map = { {0}, {0}, - {"AES128", 0x04}, - {"Comparator B", 0x2a}, + {"AES128", 0x60}, + {"Comparator B", 0xa8}, {0}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"LCDB", 0x2c}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"LCDB", 0xb0}, {0}, {0}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -5517,27 +4424,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -5548,27 +4435,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -5583,91 +4469,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -5679,24 +4543,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"USB", 0x03}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"USB", 0x40}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -5734,27 +4598,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -5765,27 +4609,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -5801,102 +4644,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 98304, .offset = 0x04400, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 3, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 6144, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 3, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -5908,24 +4729,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x00002407, .clock_map = { {0}, {0}, - {"AES128", 0x04}, - {"Comparator B", 0x2a}, + {"AES128", 0x60}, + {"Comparator B", 0xa8}, {0}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"LCDB", 0x2c}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"LCDB", 0xb0}, {0}, {0}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -5963,27 +4784,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -5994,27 +4795,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -6029,91 +4829,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -6125,24 +4903,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"USB", 0x03}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"USB", 0x40}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -6180,27 +4958,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -6211,27 +4969,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -6247,102 +5004,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 98304, .offset = 0x04400, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 3, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 6144, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 3, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -6354,24 +5089,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x00002407, .clock_map = { {0}, {0}, - {"AES128", 0x04}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"LCDB", 0x2c}, + {"AES128", 0x60}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"LCDB", 0xb0}, {0}, {0}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -6409,27 +5144,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -6440,27 +5155,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -6475,91 +5189,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -6571,7 +5263,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -6626,27 +5318,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x07, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -6675,91 +5347,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, - .bank_size = 64, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -6771,7 +5421,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -6826,27 +5476,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x07, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -6875,91 +5505,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, - .bank_size = 64, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -6971,7 +5579,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -7026,27 +5634,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x07, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -7075,91 +5663,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, - .bank_size = 64, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -7171,7 +5737,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -7226,27 +5792,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x07, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -7275,91 +5821,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, - .bank_size = 64, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -7371,7 +5895,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -7426,27 +5950,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x07, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -7475,91 +5979,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, - .bank_size = 64, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -7571,7 +6053,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -7626,27 +6108,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x07, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -7675,91 +6137,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, - .bank_size = 64, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -7771,7 +6211,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -7826,27 +6266,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x1f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 2700, .vcc_max = 3600, @@ -7857,7 +6277,7 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x21] = 0x23, + [0x22] = 0x24, }, .v3_erase = &erase_fll, .v3_write = &write_fll, @@ -7876,102 +6296,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, - .bank_size = 128, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 21, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 21, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -7983,7 +6381,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -8038,27 +6436,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x1f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 2700, .vcc_max = 3600, @@ -8069,7 +6447,7 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x21] = 0x23, + [0x22] = 0x24, }, .v3_erase = &erase_fll, .v3_write = &write_fll, @@ -8088,102 +6466,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, - .bank_size = 128, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 21, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 21, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -8195,7 +6551,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -8250,27 +6606,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x1f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 2700, .vcc_max = 3600, @@ -8281,7 +6617,7 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x21] = 0x23, + [0x22] = 0x24, }, .v3_erase = &erase_fll, .v3_write = &write_fll, @@ -8300,102 +6636,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, - .bank_size = 128, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 21, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 21, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -8407,7 +6721,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -8462,27 +6776,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x1f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 2700, .vcc_max = 3600, @@ -8493,7 +6787,7 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x21] = 0x23, + [0x22] = 0x24, }, .v3_erase = &erase_fll, .v3_write = &write_fll, @@ -8512,102 +6806,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, - .bank_size = 128, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 21, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 21, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -8619,7 +6891,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -8674,27 +6946,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x1f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 2700, .vcc_max = 3600, @@ -8705,7 +6957,7 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x21] = 0x23, + [0x22] = 0x24, }, .v3_erase = &erase_fll, .v3_write = &write_fll, @@ -8724,102 +6976,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, - .bank_size = 128, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 21, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 21, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -8831,7 +7061,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -8886,27 +7116,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x1f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 2700, .vcc_max = 3600, @@ -8917,7 +7127,7 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x21] = 0x23, + [0x22] = 0x24, }, .v3_erase = &erase_fll, .v3_write = &write_fll, @@ -8936,102 +7146,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, - .bank_size = 128, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 21, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 21, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -9043,7 +7231,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -9098,27 +7286,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x07, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -9129,7 +7297,7 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x21] = 0x23, + [0x22] = 0x24, }, .v3_erase = &erase_fll, .v3_write = &write_fll, @@ -9149,102 +7317,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, - .bank_size = 128, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 32, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 32, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -9256,7 +7402,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -9311,27 +7457,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x07, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -9342,7 +7468,7 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x21] = 0x23, + [0x22] = 0x24, }, .v3_erase = &erase_fll, .v3_write = &write_fll, @@ -9362,102 +7488,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, - .bank_size = 128, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 32, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 32, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -9469,7 +7573,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -9524,27 +7628,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x07, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -9555,7 +7639,7 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x21] = 0x23, + [0x22] = 0x24, }, .v3_erase = &erase_fll, .v3_write = &write_fll, @@ -9575,102 +7659,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, - .bank_size = 128, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 32, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 32, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -9682,7 +7744,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -9737,27 +7799,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x07, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -9768,7 +7810,7 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x21] = 0x23, + [0x22] = 0x24, }, .v3_erase = &erase_fll, .v3_write = &write_fll, @@ -9788,102 +7830,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, - .bank_size = 128, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 32, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 32, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -9895,7 +7915,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -9950,27 +7970,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x07, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -9981,7 +7981,7 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x21] = 0x23, + [0x22] = 0x24, }, .v3_erase = &erase_fll, .v3_write = &write_fll, @@ -10001,102 +8001,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, - .bank_size = 128, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 32, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 32, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -10108,7 +8086,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -10163,27 +8141,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -10194,7 +8152,7 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x21] = 0x23, + [0x22] = 0x24, }, .v3_erase = &erase_fll, .v3_write = &write_fll, @@ -10212,102 +8170,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, - .bank_size = 128, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 13, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 13, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -10319,24 +8255,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"USB", 0x03}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"USB", 0x40}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -10374,27 +8310,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -10405,27 +8321,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -10441,102 +8356,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x04400, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -10548,24 +8441,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"USB", 0x03}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"USB", 0x40}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -10603,27 +8496,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -10634,27 +8507,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -10670,102 +8542,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x04400, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -10777,7 +8627,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -10832,27 +8682,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -10863,7 +8693,7 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x21] = 0x23, + [0x22] = 0x24, }, .v3_erase = &erase_fll, .v3_write = &write_fll, @@ -10882,102 +8712,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 61184, .offset = 0x01100, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, - .bank_size = 128, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 21, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 21, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -10989,7 +8797,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x00, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -11044,27 +8852,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -11079,7 +8867,8 @@ const struct chipinfo chipinfo_db[] = { { .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_1XX, - .features = 0, + .features = 0 + | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, @@ -11090,91 +8879,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, - .bank_size = 128, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -11186,7 +8953,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x00, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -11241,27 +9008,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -11288,91 +9035,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, - .bank_size = 128, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -11384,24 +9109,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x00002407, .clock_map = { {0}, {0}, - {"AES128", 0x04}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"AES128", 0x60}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, {0}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -11439,27 +9164,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -11470,27 +9175,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -11505,91 +9209,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -11601,24 +9283,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x00002407, .clock_map = { {0}, {0}, - {"AES128", 0x04}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"AES128", 0x60}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, {0}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -11656,27 +9338,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -11687,27 +9349,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -11722,91 +9383,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -11818,24 +9457,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000040f, .clock_map = { {0}, {0}, {0}, {0}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, {0}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -11873,27 +9512,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -11904,27 +9523,27 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + [0x4d] = 0x59, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -11940,91 +9559,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 196608, .offset = 0x05c00, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -12036,24 +9633,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x00002407, .clock_map = { {0}, {0}, - {"AES128", 0x04}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"LCDB", 0x2c}, + {"AES128", 0x60}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"LCDB", 0xb0}, {0}, {0}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -12091,27 +9688,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -12122,27 +9699,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -12157,91 +9733,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -12253,24 +9807,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000040f, .clock_map = { {0}, {0}, {0}, {0}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -12308,27 +9862,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -12339,27 +9873,27 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + [0x4d] = 0x59, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -12375,91 +9909,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 196608, .offset = 0x05c00, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -12471,24 +9983,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x00002407, .clock_map = { {0}, {0}, - {"AES128", 0x04}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"AES128", 0x60}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, {0}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -12526,27 +10038,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -12557,27 +10049,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -12592,91 +10083,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -12688,24 +10157,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000040f, .clock_map = { {0}, {0}, {0}, {0}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, {0}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -12743,27 +10212,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -12774,27 +10223,27 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + [0x4d] = 0x59, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -12810,91 +10259,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x05c00, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -12906,24 +10333,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x00002407, .clock_map = { {0}, {0}, - {"AES128", 0x04}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"LCDB", 0x2c}, + {"AES128", 0x60}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"LCDB", 0xb0}, {0}, {0}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -12961,27 +10388,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -12992,27 +10399,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -13027,91 +10433,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -13123,7 +10507,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -13178,27 +10562,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x03, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -13226,91 +10590,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, - .bank_size = 64, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -13322,7 +10664,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -13377,27 +10719,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x03, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -13425,91 +10747,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, - .bank_size = 64, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -13521,7 +10821,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -13576,27 +10876,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x03, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -13624,91 +10904,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, - .bank_size = 64, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -13720,7 +10978,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006017, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -13737,7 +10995,7 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -13775,27 +11033,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x03, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x08, - .trig_options = 0x01, - .trig_dma = 0x00, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x01, - .seq_start = 0x02, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -13806,7 +11044,7 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x21] = 0x23, + [0x22] = 0x24, }, .v3_erase = &erase_fll, .v3_write = &write_fll, @@ -13824,102 +11062,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, - .bank_size = 128, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 21, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 21, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -13931,24 +11147,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000040f, .clock_map = { {0}, {0}, {0}, {0}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -13986,27 +11202,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -14017,27 +11213,27 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + [0x4d] = 0x59, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -14052,91 +11248,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x05c00, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -14148,7 +11322,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006017, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -14165,7 +11339,7 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -14203,27 +11377,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x01, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x01, - .seq_start = 0x02, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -14234,7 +11388,7 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x21] = 0x23, + [0x22] = 0x24, }, .v3_erase = &erase_fll, .v3_write = &write_fll, @@ -14251,102 +11405,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 61184, .offset = 0x01100, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, - .bank_size = 128, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 13, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 13, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -14358,7 +11490,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x00, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -14413,27 +11545,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x0f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x02, - .trig_mem = 0x03, - .trig_reg = 0x00, - .trig_combinations = 0x03, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -14460,91 +11572,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 61184, .offset = 0x01100, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, - .bank_size = 128, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -14556,7 +11646,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x00, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -14611,27 +11701,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x0f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x02, - .trig_mem = 0x03, - .trig_reg = 0x00, - .trig_combinations = 0x03, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -14658,91 +11728,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 49152, .offset = 0x04000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, - .bank_size = 128, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -14754,7 +11802,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x00, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -14809,27 +11857,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x0f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x02, - .trig_mem = 0x03, - .trig_reg = 0x00, - .trig_combinations = 0x03, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -14856,289 +11884,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, - .bank_size = 128, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - {0} - }, - }, - - { - .name = "MSP430F1471", - .bits = 16, - .psa = CHIPINFO_PSA_REGULAR, - .clock_control = 0x00, - .mclk_control = 0x60d7, - .clock_map = { - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - }, - .id = { - .ver_id = 0x49f1, - .ver_sub_id = 0x0000, - .revision = 0x00, - .fab = 0x00, - .self = 0x0000, - .config = 0x00, - .fuses = 0x03, - .activation_key = 0x00000000, - }, - .id_mask = { - .ver_id = 0xffff, - .ver_sub_id = 0xffff, - .revision = 0x00, - .fab = 0x00, - .self = 0x0000, - .config = 0x00, - .fuses = 0x0f, - .activation_key = 0x00000000, - }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x02, - .trig_mem = 0x03, - .trig_reg = 0x00, - .trig_combinations = 0x03, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, - .voltage = { - .vcc_min = 1800, - .vcc_max = 3600, - .vcc_flash_min = 2700, - .vcc_secure_min = 2500, - .vpp_secure_min = 6000, - .vpp_secure_max = 7000, - .has_test_vpp = 0, - }, - .v3_functions = { - }, - .v3_erase = &erase_dco, - .v3_write = &write_dco, - .clock_sys = CHIPINFO_CLOCK_SYS_BC_1XX, - .features = 0 - | CHIPINFO_FEATURE_QUICK_MEM_READ, - .power = { - .reg_mask = 0x00000, - .enable_lpm5 = 0x00000, - .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x00000, - .enable_lpm5_3v = 0x00000, - .disable_lpm5_3v = 0x00000, - }, - .memory = { - { - .name = "main", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 32768, - .offset = 0x08000, - .seg_size = 512, - .bank_size = 65536, - .banks = 1, - }, - { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01000, - .seg_size = 128, - .bank_size = 128, - .banks = 2, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 1024, - .offset = 0x00c00, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 5120, - .offset = 0x00200, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "peripheral16bit", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x00100, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "peripheral8bit", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 8, - .mapped = 1, - .size = 256, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -15150,7 +11958,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x00, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -15205,27 +12013,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x0f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x02, - .trig_mem = 0x03, - .trig_reg = 0x00, - .trig_combinations = 0x03, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -15252,91 +12040,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, - .bank_size = 128, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -15348,7 +12114,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x00, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -15403,27 +12169,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x0f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x02, - .trig_mem = 0x03, - .trig_reg = 0x00, - .trig_combinations = 0x03, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -15450,289 +12196,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, - .bank_size = 128, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - {0} - }, - }, - - { - .name = "MSP430F1491", - .bits = 16, - .psa = CHIPINFO_PSA_REGULAR, - .clock_control = 0x00, - .mclk_control = 0x60d7, - .clock_map = { - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - }, - .id = { - .ver_id = 0x49f1, - .ver_sub_id = 0x0000, - .revision = 0x00, - .fab = 0x00, - .self = 0x0000, - .config = 0x00, - .fuses = 0x06, - .activation_key = 0x00000000, - }, - .id_mask = { - .ver_id = 0xffff, - .ver_sub_id = 0xffff, - .revision = 0x00, - .fab = 0x00, - .self = 0x0000, - .config = 0x00, - .fuses = 0x0f, - .activation_key = 0x00000000, - }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x02, - .trig_mem = 0x03, - .trig_reg = 0x00, - .trig_combinations = 0x03, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, - .voltage = { - .vcc_min = 1800, - .vcc_max = 3600, - .vcc_flash_min = 2700, - .vcc_secure_min = 2500, - .vpp_secure_min = 6000, - .vpp_secure_max = 7000, - .has_test_vpp = 0, - }, - .v3_functions = { - }, - .v3_erase = &erase_dco, - .v3_write = &write_dco, - .clock_sys = CHIPINFO_CLOCK_SYS_BC_1XX, - .features = 0 - | CHIPINFO_FEATURE_QUICK_MEM_READ, - .power = { - .reg_mask = 0x00000, - .enable_lpm5 = 0x00000, - .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x00000, - .enable_lpm5_3v = 0x00000, - .disable_lpm5_3v = 0x00000, - }, - .memory = { - { - .name = "main", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 61184, - .offset = 0x01100, - .seg_size = 512, - .bank_size = 65536, - .banks = 1, - }, - { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01000, - .seg_size = 128, - .bank_size = 128, - .banks = 2, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 1024, - .offset = 0x00c00, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 5120, - .offset = 0x00200, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "peripheral16bit", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x00100, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "peripheral8bit", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 8, - .mapped = 1, - .size = 256, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -15744,7 +12270,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006007, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -15752,8 +12278,8 @@ const struct chipinfo chipinfo_db[] = { { {"ACLK (Pin)", 0x00}, {"ADC12", 0x00}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, {0}, @@ -15761,7 +12287,7 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -15799,27 +12325,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x0f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x02, - .trig_mem = 0x03, - .trig_reg = 0x00, - .trig_combinations = 0x03, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -15847,91 +12353,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 61184, .offset = 0x01100, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, - .bank_size = 64, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -15943,7 +12427,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006007, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -15951,8 +12435,8 @@ const struct chipinfo chipinfo_db[] = { { {"ACLK (Pin)", 0x00}, {"ADC12", 0x00}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, {0}, @@ -15960,7 +12444,7 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -15998,27 +12482,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x0f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x02, - .trig_mem = 0x03, - .trig_reg = 0x00, - .trig_combinations = 0x03, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -16046,102 +12510,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 49152, .offset = 0x04000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01000, - .seg_size = 64, - .bank_size = 64, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 1024, - .offset = 0x00c00, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x00200, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram2", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01000, + .seg_size = 64, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x00c00, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x00200, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -16153,7 +12595,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006007, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -16161,8 +12603,8 @@ const struct chipinfo chipinfo_db[] = { { {"ACLK (Pin)", 0x00}, {"ADC12", 0x00}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, {0}, @@ -16170,7 +12612,7 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -16208,27 +12650,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x0f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x02, - .trig_mem = 0x03, - .trig_reg = 0x00, - .trig_combinations = 0x03, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -16256,102 +12678,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01000, - .seg_size = 64, - .bank_size = 64, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 1024, - .offset = 0x00c00, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x00200, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram2", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01000, + .seg_size = 64, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x00c00, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x00200, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -16363,7 +12763,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006007, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -16372,7 +12772,7 @@ const struct chipinfo chipinfo_db[] = { { {"ADC12", 0x00}, {0}, {0}, - {"USCI0", 0x1f}, + {"USCI0", 0x28}, {0}, {0}, {0}, @@ -16380,7 +12780,7 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -16418,27 +12818,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x0f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x02, - .trig_mem = 0x03, - .trig_reg = 0x00, - .trig_combinations = 0x03, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -16466,91 +12846,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, - .bank_size = 64, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -16562,7 +12920,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006007, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -16570,8 +12928,8 @@ const struct chipinfo chipinfo_db[] = { { {"ACLK (Pin)", 0x00}, {0}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, {0}, @@ -16579,7 +12937,7 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -16617,27 +12975,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x0f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x02, - .trig_mem = 0x03, - .trig_reg = 0x00, - .trig_combinations = 0x03, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -16665,91 +13003,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 61184, .offset = 0x01100, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, - .bank_size = 64, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -16761,7 +13077,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006007, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -16769,8 +13085,8 @@ const struct chipinfo chipinfo_db[] = { { {"ACLK (Pin)", 0x00}, {0}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, {0}, @@ -16778,7 +13094,7 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -16816,27 +13132,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x0f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x02, - .trig_mem = 0x03, - .trig_reg = 0x00, - .trig_combinations = 0x03, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -16864,102 +13160,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 49152, .offset = 0x04000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01000, - .seg_size = 64, - .bank_size = 64, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 1024, - .offset = 0x00c00, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x00200, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram2", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01000, + .seg_size = 64, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x00c00, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x00200, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -16971,7 +13245,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006007, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -16979,8 +13253,8 @@ const struct chipinfo chipinfo_db[] = { { {"ACLK (Pin)", 0x00}, {0}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, {0}, @@ -16988,7 +13262,7 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -17026,27 +13300,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x0f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x02, - .trig_mem = 0x03, - .trig_reg = 0x00, - .trig_combinations = 0x03, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -17074,102 +13328,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01000, - .seg_size = 64, - .bank_size = 64, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 1024, - .offset = 0x00c00, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x00200, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram2", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01000, + .seg_size = 64, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x00c00, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x00200, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -17181,7 +13413,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006007, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -17190,7 +13422,7 @@ const struct chipinfo chipinfo_db[] = { { {"ADC12", 0x00}, {0}, {0}, - {"USCI0", 0x1f}, + {"USCI0", 0x28}, {0}, {0}, {0}, @@ -17198,7 +13430,7 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -17236,27 +13468,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x0f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x02, - .trig_mem = 0x03, - .trig_reg = 0x00, - .trig_combinations = 0x03, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -17284,91 +13496,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, - .bank_size = 64, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -17380,7 +13570,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006007, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -17388,8 +13578,8 @@ const struct chipinfo chipinfo_db[] = { { {"ACLK (Pin)", 0x00}, {"ADC12", 0x00}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, {0}, @@ -17397,7 +13587,7 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -17435,27 +13625,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x0f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x02, - .trig_mem = 0x03, - .trig_reg = 0x00, - .trig_combinations = 0x03, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -17483,102 +13653,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 57088, .offset = 0x02100, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01000, - .seg_size = 64, - .bank_size = 64, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 1024, - .offset = 0x00c00, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x00200, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram2", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01000, + .seg_size = 64, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x00c00, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x00200, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -17590,7 +13738,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006017, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -17607,7 +13755,7 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -17645,27 +13793,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x0f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x03, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x08, - .trig_options = 0x01, - .trig_dma = 0x00, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x01, - .seq_start = 0x02, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -17676,7 +13804,7 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x21] = 0x23, + [0x22] = 0x24, }, .v3_erase = &erase_fll, .v3_write = &write_fll, @@ -17694,102 +13822,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 61184, .offset = 0x01100, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, - .bank_size = 128, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 21, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 21, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -17801,7 +13907,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006017, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -17818,7 +13924,7 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -17856,27 +13962,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x0f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x03, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x08, - .trig_options = 0x01, - .trig_dma = 0x00, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x01, - .seq_start = 0x02, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -17887,7 +13973,7 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x21] = 0x23, + [0x22] = 0x24, }, .v3_erase = &erase_fll, .v3_write = &write_fll, @@ -17905,102 +13991,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, - .bank_size = 128, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 21, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 21, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -18012,7 +14076,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00000017, .clock_map = { {0}, {0}, @@ -18020,8 +14084,8 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"SD16", 0x00}, {"Flash Control", 0x00}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, {"LCD Frequency", 0x00}, @@ -18067,27 +14131,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x07, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -18098,7 +14142,7 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x21] = 0x23, + [0x22] = 0x24, }, .v3_erase = &erase_fll, .v3_write = &write_fll, @@ -18117,102 +14161,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 61184, .offset = 0x01100, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, - .bank_size = 64, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 32, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2560, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 32, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -18224,7 +14246,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00000017, .clock_map = { {0}, {0}, @@ -18232,8 +14254,8 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"SD16", 0x00}, {"Flash Control", 0x00}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, {"LCD Frequency", 0x00}, @@ -18279,27 +14301,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x07, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -18310,7 +14312,7 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x21] = 0x23, + [0x22] = 0x24, }, .v3_erase = &erase_fll, .v3_write = &write_fll, @@ -18329,102 +14331,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 49152, .offset = 0x04000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, - .bank_size = 64, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 32, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 32, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -18436,7 +14416,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00000017, .clock_map = { {0}, {0}, @@ -18444,8 +14424,8 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"SD16", 0x00}, {"Flash Control", 0x00}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, {"LCD Frequency", 0x00}, @@ -18491,27 +14471,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x07, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -18522,7 +14482,7 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x21] = 0x23, + [0x22] = 0x24, }, .v3_erase = &erase_fll, .v3_write = &write_fll, @@ -18541,102 +14501,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 61184, .offset = 0x01100, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, - .bank_size = 64, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 32, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2560, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 32, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -18648,7 +14586,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00000017, .clock_map = { {0}, {0}, @@ -18656,8 +14594,8 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"SD16", 0x00}, {"Flash Control", 0x00}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, {"LCD Frequency", 0x00}, @@ -18703,27 +14641,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x07, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -18734,7 +14652,7 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x21] = 0x23, + [0x22] = 0x24, }, .v3_erase = &erase_fll, .v3_write = &write_fll, @@ -18753,102 +14671,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 49152, .offset = 0x04000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, - .bank_size = 64, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 32, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 32, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -18860,7 +14756,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -18915,27 +14811,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -18952,8 +14828,7 @@ const struct chipinfo chipinfo_db[] = { { .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE - | CHIPINFO_FEATURE_QUICK_MEM_READ - | CHIPINFO_FEATURE_NO_BSL, + | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, @@ -18964,91 +14839,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, - .bank_size = 64, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -19060,7 +14913,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006017, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -19069,7 +14922,7 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"Flash Controller", 0x00}, {0}, - {"USCI0", 0x1f}, + {"USCI0", 0x28}, {0}, {0}, {0}, @@ -19077,7 +14930,7 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"TimerB3", 0x00}, {"TimerA3", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -19115,27 +14968,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x01, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -19146,7 +14979,7 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x21] = 0x23, + [0x22] = 0x24, }, .v3_erase = &erase_fll, .v3_write = &write_fll, @@ -19164,102 +14997,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, - .bank_size = 64, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 32, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 32, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -19271,7 +15082,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006017, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -19280,7 +15091,7 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"Flash Controller", 0x00}, {0}, - {"USCI0", 0x1f}, + {"USCI0", 0x28}, {0}, {0}, {0}, @@ -19288,7 +15099,7 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"TimerB3", 0x00}, {"TimerA3", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -19326,27 +15137,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x01, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -19357,7 +15148,7 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x21] = 0x23, + [0x22] = 0x24, }, .v3_erase = &erase_fll, .v3_write = &write_fll, @@ -19375,102 +15166,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, - .bank_size = 64, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 32, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 32, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -19482,7 +15251,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -19537,27 +15306,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x1f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 2700, .vcc_max = 3600, @@ -19568,7 +15317,7 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x21] = 0x23, + [0x22] = 0x24, }, .v3_erase = &erase_fll, .v3_write = &write_fll, @@ -19587,102 +15336,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, - .bank_size = 128, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 21, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 21, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -19694,7 +15421,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -19749,27 +15476,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x1f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 2700, .vcc_max = 3600, @@ -19780,7 +15487,7 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x21] = 0x23, + [0x22] = 0x24, }, .v3_erase = &erase_fll, .v3_write = &write_fll, @@ -19799,102 +15506,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, - .bank_size = 128, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 21, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 21, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -19906,7 +15591,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -19961,27 +15646,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x1f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 2700, .vcc_max = 3600, @@ -19992,7 +15657,7 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x21] = 0x23, + [0x22] = 0x24, }, .v3_erase = &erase_fll, .v3_write = &write_fll, @@ -20011,102 +15676,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, - .bank_size = 128, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 21, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 21, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -20118,7 +15761,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -20173,27 +15816,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x0f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -20204,7 +15827,6 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x19] = 0x1a, }, .v3_erase = &erase_dco, .v3_write = &write_dco, @@ -20223,80 +15845,58 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, - .bank_size = 64, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -20308,7 +15908,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -20363,27 +15963,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x0f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -20394,7 +15974,6 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x19] = 0x1a, }, .v3_erase = &erase_dco, .v3_write = &write_dco, @@ -20413,80 +15992,58 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, - .bank_size = 64, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -20498,7 +16055,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -20553,27 +16110,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x0f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -20584,7 +16121,6 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x19] = 0x1a, }, .v3_erase = &erase_dco, .v3_write = &write_dco, @@ -20603,80 +16139,58 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x0f000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, - .bank_size = 64, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -20688,7 +16202,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -20743,27 +16257,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x0f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -20774,7 +16268,6 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x19] = 0x1a, }, .v3_erase = &erase_dco, .v3_write = &write_dco, @@ -20793,80 +16286,58 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, - .bank_size = 64, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -20878,7 +16349,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -20933,27 +16404,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x0f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -20964,7 +16415,6 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x19] = 0x1a, }, .v3_erase = &erase_dco, .v3_write = &write_dco, @@ -20983,80 +16433,58 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, - .bank_size = 64, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -21068,7 +16496,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -21123,27 +16551,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x0f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -21154,7 +16562,6 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x19] = 0x1a, }, .v3_erase = &erase_dco, .v3_write = &write_dco, @@ -21173,80 +16580,58 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x0f000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, - .bank_size = 64, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -21258,7 +16643,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -21313,27 +16698,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x0f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -21344,7 +16709,6 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x19] = 0x1a, }, .v3_erase = &erase_dco, .v3_write = &write_dco, @@ -21363,80 +16727,58 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, - .bank_size = 64, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -21448,7 +16790,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -21503,27 +16845,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x0f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -21534,7 +16856,6 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x19] = 0x1a, }, .v3_erase = &erase_dco, .v3_write = &write_dco, @@ -21553,80 +16874,58 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, - .bank_size = 64, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -21638,7 +16937,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -21693,27 +16992,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x0f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -21724,7 +17003,6 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x19] = 0x1a, }, .v3_erase = &erase_dco, .v3_write = &write_dco, @@ -21743,80 +17021,58 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x0f000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, - .bank_size = 64, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -21828,7 +17084,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -21883,27 +17139,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x0f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -21914,7 +17150,6 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x19] = 0x1a, }, .v3_erase = &erase_dco, .v3_write = &write_dco, @@ -21933,80 +17168,58 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, - .bank_size = 64, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -22018,7 +17231,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -22073,27 +17286,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x0f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -22104,7 +17297,6 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x19] = 0x1a, }, .v3_erase = &erase_dco, .v3_write = &write_dco, @@ -22123,80 +17315,58 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, - .bank_size = 64, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -22208,7 +17378,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -22263,27 +17433,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x0f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -22294,7 +17444,6 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x19] = 0x1a, }, .v3_erase = &erase_dco, .v3_write = &write_dco, @@ -22313,80 +17462,58 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x0f000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, - .bank_size = 64, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -22398,7 +17525,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -22453,27 +17580,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -22490,8 +17597,7 @@ const struct chipinfo chipinfo_db[] = { { .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE - | CHIPINFO_FEATURE_QUICK_MEM_READ - | CHIPINFO_FEATURE_NO_BSL, + | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, @@ -22502,91 +17608,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, - .bank_size = 64, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -22598,7 +17682,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x03, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -22653,27 +17737,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -22684,15 +17748,13 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x19] = 0x1a, }, .v3_erase = &erase_dco, .v3_write = &write_dco, .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE - | CHIPINFO_FEATURE_QUICK_MEM_READ - | CHIPINFO_FEATURE_NO_BSL, + | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, @@ -22703,102 +17765,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 57088, .offset = 0x02100, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01000, - .seg_size = 64, - .bank_size = 64, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 1024, - .offset = 0x00c00, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x00200, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram2", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01000, + .seg_size = 64, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x00c00, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x00200, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -22810,7 +17850,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -22865,27 +17905,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -22902,8 +17922,7 @@ const struct chipinfo chipinfo_db[] = { { .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE - | CHIPINFO_FEATURE_QUICK_MEM_READ - | CHIPINFO_FEATURE_NO_BSL, + | CHIPINFO_FEATURE_QUICK_MEM_READ, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, @@ -22914,91 +17933,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, - .bank_size = 64, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -23010,7 +18007,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006007, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -23027,7 +18024,7 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -23065,27 +18062,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x0f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x03, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x08, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x01, - .seq_start = 0x02, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -23113,91 +18090,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 61184, .offset = 0x01100, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, - .bank_size = 128, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -23209,7 +18164,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006007, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -23226,7 +18181,7 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -23264,27 +18219,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x0f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x03, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x08, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x01, - .seq_start = 0x02, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -23312,91 +18247,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 49152, .offset = 0x04000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, - .bank_size = 128, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -23408,7 +18321,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006007, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -23425,7 +18338,7 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -23463,27 +18376,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x0f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x03, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x08, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x01, - .seq_start = 0x02, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -23511,91 +18404,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, - .bank_size = 128, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -23607,7 +18478,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006007, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -23624,7 +18495,7 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -23662,27 +18533,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x0f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x03, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x08, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x01, - .seq_start = 0x02, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -23710,91 +18561,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, - .bank_size = 128, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -23806,7 +18635,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006007, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -23823,7 +18652,7 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -23861,27 +18690,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x0f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x03, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x08, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x01, - .seq_start = 0x02, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -23909,91 +18718,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 24576, .offset = 0x0a000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, - .bank_size = 128, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -24005,7 +18792,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006007, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -24022,7 +18809,7 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -24060,27 +18847,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x0f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x03, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x08, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x01, - .seq_start = 0x02, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -24108,91 +18875,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, - .bank_size = 128, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -24204,7 +18949,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006007, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -24221,7 +18966,7 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -24259,27 +19004,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x07, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x03, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x08, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x01, - .seq_start = 0x02, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -24307,102 +19032,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 49152, .offset = 0x04000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01000, - .seg_size = 128, - .bank_size = 128, - .banks = 2, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 1024, - .offset = 0x00c00, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x00200, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram2", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 10240, .offset = 0x01100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01000, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 2, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x00c00, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x00200, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -24414,7 +19117,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006007, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -24431,7 +19134,7 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -24469,27 +19172,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x07, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x03, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x08, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x01, - .seq_start = 0x02, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -24517,102 +19200,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01000, - .seg_size = 128, - .bank_size = 128, - .banks = 2, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 1024, - .offset = 0x00c00, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x00200, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram2", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 5120, .offset = 0x01100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01000, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 2, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x00c00, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x00200, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -24624,7 +19285,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006007, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -24641,7 +19302,7 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -24679,27 +19340,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x07, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x03, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x08, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x01, - .seq_start = 0x02, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -24727,102 +19368,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 56064, .offset = 0x02500, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01000, - .seg_size = 128, - .bank_size = 128, - .banks = 2, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 1024, - .offset = 0x00c00, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x00200, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram2", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 5120, .offset = 0x01100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01000, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 2, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x00c00, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x00200, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -24834,7 +19453,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006007, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -24851,7 +19470,7 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -24889,27 +19508,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x07, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x03, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x08, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x01, - .seq_start = 0x02, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -24937,91 +19536,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 61184, .offset = 0x01100, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, - .bank_size = 128, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -25033,7 +19610,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006017, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -25041,8 +19618,8 @@ const struct chipinfo chipinfo_db[] = { { {"ACLK (Pin)", 0x00}, {"ADC12", 0x00}, {"Flash Control", 0x00}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, {0}, @@ -25050,7 +19627,7 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -25088,27 +19665,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x07, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x03, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x08, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x01, - .seq_start = 0x02, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -25119,20 +19676,20 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x11] = 0x26, [0x12] = 0x27, [0x13] = 0x28, - [0x15] = 0x2a, + [0x14] = 0x29, [0x16] = 0x2b, - [0x18] = 0x2d, + [0x17] = 0x2c, [0x19] = 0x2e, - [0x1b] = 0x2f, + [0x1a] = 0x2f, [0x1c] = 0x30, [0x1d] = 0x31, [0x1e] = 0x32, [0x1f] = 0x33, - [0x21] = 0x34, - [0x25] = 0x36, + [0x20] = 0x34, + [0x22] = 0x35, + [0x26] = 0x37, }, .v3_erase = &erase_xdco, .v3_write = &write_xdco, @@ -25150,102 +19707,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 122624, .offset = 0x02100, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01000, - .seg_size = 64, - .bank_size = 64, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 1024, - .offset = 0x00c00, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x00200, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram2", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01000, + .seg_size = 64, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x00c00, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x00200, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -25257,7 +19792,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006017, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -25265,8 +19800,8 @@ const struct chipinfo chipinfo_db[] = { { {"ACLK (Pin)", 0x00}, {"ADC12", 0x00}, {"Flash Control", 0x00}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, {0}, @@ -25274,7 +19809,7 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -25312,27 +19847,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x07, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x03, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x08, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x01, - .seq_start = 0x02, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -25343,20 +19858,20 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x11] = 0x26, [0x12] = 0x27, [0x13] = 0x28, - [0x15] = 0x2a, + [0x14] = 0x29, [0x16] = 0x2b, - [0x18] = 0x2d, + [0x17] = 0x2c, [0x19] = 0x2e, - [0x1b] = 0x2f, + [0x1a] = 0x2f, [0x1c] = 0x30, [0x1d] = 0x31, [0x1e] = 0x32, [0x1f] = 0x33, - [0x21] = 0x34, - [0x25] = 0x36, + [0x20] = 0x34, + [0x22] = 0x35, + [0x26] = 0x37, }, .v3_erase = &erase_xdco, .v3_write = &write_xdco, @@ -25374,102 +19889,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 118528, .offset = 0x03100, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01000, - .seg_size = 64, - .bank_size = 64, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 1024, - .offset = 0x00c00, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x00200, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram2", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x01100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01000, + .seg_size = 64, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x00c00, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x00200, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -25481,7 +19974,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006017, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -25489,8 +19982,8 @@ const struct chipinfo chipinfo_db[] = { { {"ACLK (Pin)", 0x00}, {"ADC12", 0x00}, {"Flash Control", 0x00}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, {0}, @@ -25498,7 +19991,7 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -25536,27 +20029,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x07, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x03, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x08, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x01, - .seq_start = 0x02, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -25567,20 +20040,20 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x11] = 0x26, [0x12] = 0x27, [0x13] = 0x28, - [0x15] = 0x2a, + [0x14] = 0x29, [0x16] = 0x2b, - [0x18] = 0x2d, + [0x17] = 0x2c, [0x19] = 0x2e, - [0x1b] = 0x2f, + [0x1a] = 0x2f, [0x1c] = 0x30, [0x1d] = 0x31, [0x1e] = 0x32, [0x1f] = 0x33, - [0x21] = 0x34, - [0x25] = 0x36, + [0x20] = 0x34, + [0x22] = 0x35, + [0x26] = 0x37, }, .v3_erase = &erase_xdco, .v3_write = &write_xdco, @@ -25598,102 +20071,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 93952, .offset = 0x03100, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01000, - .seg_size = 64, - .bank_size = 64, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 1024, - .offset = 0x00c00, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x00200, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram2", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x01100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01000, + .seg_size = 64, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x00c00, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x00200, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -25705,7 +20156,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006017, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -25713,8 +20164,8 @@ const struct chipinfo chipinfo_db[] = { { {"ACLK (Pin)", 0x00}, {"ADC12", 0x00}, {"Flash Control", 0x00}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, {0}, @@ -25722,7 +20173,7 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -25760,27 +20211,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x07, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x03, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x08, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x01, - .seq_start = 0x02, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -25791,20 +20222,20 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x11] = 0x26, [0x12] = 0x27, [0x13] = 0x28, - [0x15] = 0x2a, + [0x14] = 0x29, [0x16] = 0x2b, - [0x18] = 0x2d, + [0x17] = 0x2c, [0x19] = 0x2e, - [0x1b] = 0x2f, + [0x1a] = 0x2f, [0x1c] = 0x30, [0x1d] = 0x31, [0x1e] = 0x32, [0x1f] = 0x33, - [0x21] = 0x34, - [0x25] = 0x36, + [0x20] = 0x34, + [0x22] = 0x35, + [0x26] = 0x37, }, .v3_erase = &erase_xdco, .v3_write = &write_xdco, @@ -25822,102 +20253,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 93952, .offset = 0x02100, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01000, - .seg_size = 64, - .bank_size = 64, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 1024, - .offset = 0x00c00, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x00200, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram2", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01000, + .seg_size = 64, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x00c00, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x00200, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -25929,7 +20338,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006017, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -25937,8 +20346,8 @@ const struct chipinfo chipinfo_db[] = { { {"ACLK (Pin)", 0x00}, {"ADC12", 0x00}, {"Flash Control", 0x00}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, {0}, @@ -25946,7 +20355,7 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -25984,27 +20393,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x07, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x03, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x08, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x01, - .seq_start = 0x02, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -26015,20 +20404,20 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x11] = 0x26, [0x12] = 0x27, [0x13] = 0x28, - [0x15] = 0x2a, + [0x14] = 0x29, [0x16] = 0x2b, - [0x18] = 0x2d, + [0x17] = 0x2c, [0x19] = 0x2e, - [0x1b] = 0x2f, + [0x1a] = 0x2f, [0x1c] = 0x30, [0x1d] = 0x31, [0x1e] = 0x32, [0x1f] = 0x33, - [0x21] = 0x34, - [0x25] = 0x36, + [0x20] = 0x34, + [0x22] = 0x35, + [0x26] = 0x37, }, .v3_erase = &erase_xdco, .v3_write = &write_xdco, @@ -26046,102 +20435,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 122624, .offset = 0x02100, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01000, - .seg_size = 64, - .bank_size = 64, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 1024, - .offset = 0x00c00, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x00200, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram2", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01000, + .seg_size = 64, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x00c00, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x00200, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -26153,7 +20520,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006017, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -26161,8 +20528,8 @@ const struct chipinfo chipinfo_db[] = { { {"ACLK (Pin)", 0x00}, {"ADC12", 0x00}, {"Flash Control", 0x00}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, {0}, @@ -26170,7 +20537,7 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -26208,27 +20575,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x07, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x03, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x08, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x01, - .seq_start = 0x02, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -26239,20 +20586,20 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x11] = 0x26, [0x12] = 0x27, [0x13] = 0x28, - [0x15] = 0x2a, + [0x14] = 0x29, [0x16] = 0x2b, - [0x18] = 0x2d, + [0x17] = 0x2c, [0x19] = 0x2e, - [0x1b] = 0x2f, + [0x1a] = 0x2f, [0x1c] = 0x30, [0x1d] = 0x31, [0x1e] = 0x32, [0x1f] = 0x33, - [0x21] = 0x34, - [0x25] = 0x36, + [0x20] = 0x34, + [0x22] = 0x35, + [0x26] = 0x37, }, .v3_erase = &erase_xdco, .v3_write = &write_xdco, @@ -26270,102 +20617,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 118528, .offset = 0x03100, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01000, - .seg_size = 64, - .bank_size = 64, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 1024, - .offset = 0x00c00, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x00200, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram2", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x01100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01000, + .seg_size = 64, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x00c00, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x00200, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -26377,7 +20702,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006017, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -26385,8 +20710,8 @@ const struct chipinfo chipinfo_db[] = { { {"ACLK (Pin)", 0x00}, {"ADC12", 0x00}, {"Flash Control", 0x00}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, {0}, @@ -26394,7 +20719,7 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -26432,27 +20757,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x07, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x03, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x08, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x01, - .seq_start = 0x02, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -26463,20 +20768,20 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x11] = 0x26, [0x12] = 0x27, [0x13] = 0x28, - [0x15] = 0x2a, + [0x14] = 0x29, [0x16] = 0x2b, - [0x18] = 0x2d, + [0x17] = 0x2c, [0x19] = 0x2e, - [0x1b] = 0x2f, + [0x1a] = 0x2f, [0x1c] = 0x30, [0x1d] = 0x31, [0x1e] = 0x32, [0x1f] = 0x33, - [0x21] = 0x34, - [0x25] = 0x36, + [0x20] = 0x34, + [0x22] = 0x35, + [0x26] = 0x37, }, .v3_erase = &erase_xdco, .v3_write = &write_xdco, @@ -26494,102 +20799,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 93952, .offset = 0x03100, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01000, - .seg_size = 64, - .bank_size = 64, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 1024, - .offset = 0x00c00, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x00200, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram2", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x01100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01000, + .seg_size = 64, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x00c00, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x00200, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -26601,7 +20884,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006017, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -26609,8 +20892,8 @@ const struct chipinfo chipinfo_db[] = { { {"ACLK (Pin)", 0x00}, {"ADC12", 0x00}, {"Flash Control", 0x00}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, {0}, @@ -26618,7 +20901,7 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -26656,27 +20939,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x07, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x03, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x08, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x01, - .seq_start = 0x02, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -26687,20 +20950,20 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x11] = 0x26, [0x12] = 0x27, [0x13] = 0x28, - [0x15] = 0x2a, + [0x14] = 0x29, [0x16] = 0x2b, - [0x18] = 0x2d, + [0x17] = 0x2c, [0x19] = 0x2e, - [0x1b] = 0x2f, + [0x1a] = 0x2f, [0x1c] = 0x30, [0x1d] = 0x31, [0x1e] = 0x32, [0x1f] = 0x33, - [0x21] = 0x34, - [0x25] = 0x36, + [0x20] = 0x34, + [0x22] = 0x35, + [0x26] = 0x37, }, .v3_erase = &erase_xdco, .v3_write = &write_xdco, @@ -26718,102 +20981,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 93952, .offset = 0x02100, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01000, - .seg_size = 64, - .bank_size = 64, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 1024, - .offset = 0x00c00, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x00200, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram2", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01000, + .seg_size = 64, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x00c00, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x00200, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -26825,7 +21066,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006017, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -26833,8 +21074,8 @@ const struct chipinfo chipinfo_db[] = { { {"ACLK (Pin)", 0x00}, {"ADC12", 0x00}, {"Flash Control", 0x00}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, {"LCD Frequency", 0x00}, @@ -26842,7 +21083,7 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -26880,27 +21121,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x03, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x03, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x08, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x01, - .seq_start = 0x02, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -26911,20 +21132,20 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x11] = 0x26, [0x12] = 0x27, [0x13] = 0x28, - [0x15] = 0x2a, + [0x14] = 0x29, [0x16] = 0x2b, - [0x18] = 0x2d, + [0x17] = 0x2c, [0x19] = 0x2e, - [0x1b] = 0x2f, + [0x1a] = 0x2f, [0x1c] = 0x30, [0x1d] = 0x31, [0x1e] = 0x32, [0x1f] = 0x33, - [0x21] = 0x35, - [0x25] = 0x36, + [0x20] = 0x34, + [0x22] = 0x36, + [0x26] = 0x37, }, .v3_erase = &erase_xfll, .v3_write = &write_xfll, @@ -26942,113 +21163,91 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 122624, .offset = 0x02100, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01000, - .seg_size = 128, - .bank_size = 128, - .banks = 2, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 1024, - .offset = 0x00c00, - .seg_size = 512, - .bank_size = 0, - .banks = 1, - }, - { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 13, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x00200, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram2", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01000, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 2, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x00c00, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x00200, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 13, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -27060,7 +21259,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006017, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -27068,8 +21267,8 @@ const struct chipinfo chipinfo_db[] = { { {"ACLK (Pin)", 0x00}, {"ADC12", 0x00}, {"Flash Control", 0x00}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, {"LCD Frequency", 0x00}, @@ -27077,7 +21276,7 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -27115,27 +21314,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x03, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x03, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x08, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x01, - .seq_start = 0x02, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -27146,20 +21325,20 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x11] = 0x26, [0x12] = 0x27, [0x13] = 0x28, - [0x15] = 0x2a, + [0x14] = 0x29, [0x16] = 0x2b, - [0x18] = 0x2d, + [0x17] = 0x2c, [0x19] = 0x2e, - [0x1b] = 0x2f, + [0x1a] = 0x2f, [0x1c] = 0x30, [0x1d] = 0x31, [0x1e] = 0x32, [0x1f] = 0x33, - [0x21] = 0x35, - [0x25] = 0x36, + [0x20] = 0x34, + [0x22] = 0x36, + [0x26] = 0x37, }, .v3_erase = &erase_xfll, .v3_write = &write_xfll, @@ -27177,113 +21356,91 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 118528, .offset = 0x03100, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01000, - .seg_size = 128, - .bank_size = 128, - .banks = 2, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 1024, - .offset = 0x00c00, - .seg_size = 512, - .bank_size = 0, - .banks = 1, - }, - { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 13, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x00200, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram2", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x01100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01000, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 2, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x00c00, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x00200, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 13, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -27295,7 +21452,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006017, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -27303,8 +21460,8 @@ const struct chipinfo chipinfo_db[] = { { {"ACLK (Pin)", 0x00}, {"ADC12", 0x00}, {"Flash Control", 0x00}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, {"LCD Frequency", 0x00}, @@ -27312,7 +21469,7 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -27350,27 +21507,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x03, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x03, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x08, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x01, - .seq_start = 0x02, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -27381,20 +21518,20 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x11] = 0x26, [0x12] = 0x27, [0x13] = 0x28, - [0x15] = 0x2a, + [0x14] = 0x29, [0x16] = 0x2b, - [0x18] = 0x2d, + [0x17] = 0x2c, [0x19] = 0x2e, - [0x1b] = 0x2f, + [0x1a] = 0x2f, [0x1c] = 0x30, [0x1d] = 0x31, [0x1e] = 0x32, [0x1f] = 0x33, - [0x21] = 0x35, - [0x25] = 0x36, + [0x20] = 0x34, + [0x22] = 0x36, + [0x26] = 0x37, }, .v3_erase = &erase_xfll, .v3_write = &write_xfll, @@ -27412,113 +21549,91 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 93952, .offset = 0x03100, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01000, - .seg_size = 128, - .bank_size = 128, - .banks = 2, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 1024, - .offset = 0x00c00, - .seg_size = 512, - .bank_size = 0, - .banks = 1, - }, - { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 13, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x00200, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram2", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x01100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01000, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 2, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x00c00, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x00200, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 13, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -27530,7 +21645,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006017, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -27538,8 +21653,8 @@ const struct chipinfo chipinfo_db[] = { { {"ACLK (Pin)", 0x00}, {"ADC12", 0x00}, {"Flash Control", 0x00}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, {"LCD Frequency", 0x00}, @@ -27547,7 +21662,7 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"TimerB", 0x00}, {"TimerA", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -27585,27 +21700,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x03, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x03, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x08, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x01, - .seq_start = 0x02, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -27616,20 +21711,20 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x11] = 0x26, [0x12] = 0x27, [0x13] = 0x28, - [0x15] = 0x2a, + [0x14] = 0x29, [0x16] = 0x2b, - [0x18] = 0x2d, + [0x17] = 0x2c, [0x19] = 0x2e, - [0x1b] = 0x2f, + [0x1a] = 0x2f, [0x1c] = 0x30, [0x1d] = 0x31, [0x1e] = 0x32, [0x1f] = 0x33, - [0x21] = 0x35, - [0x25] = 0x36, + [0x20] = 0x34, + [0x22] = 0x36, + [0x26] = 0x37, }, .v3_erase = &erase_xfll, .v3_write = &write_xfll, @@ -27647,113 +21742,91 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 93952, .offset = 0x02100, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01000, - .seg_size = 128, - .bank_size = 128, - .banks = 2, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 1024, - .offset = 0x00c00, - .seg_size = 512, - .bank_size = 0, - .banks = 1, - }, - { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 13, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x00200, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram2", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01000, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 2, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x00c00, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x00200, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 13, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -27765,7 +21838,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006017, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -27774,7 +21847,7 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"Flash Controller", 0x00}, {0}, - {"USCI0", 0x1f}, + {"USCI0", 0x28}, {0}, {0}, {0}, @@ -27782,7 +21855,7 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"TimerB3", 0x00}, {"TimerA3", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -27820,27 +21893,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x07, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -27851,7 +21904,7 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x21] = 0x23, + [0x22] = 0x24, }, .v3_erase = &erase_fll, .v3_write = &write_fll, @@ -27869,102 +21922,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 61184, .offset = 0x01100, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, - .bank_size = 64, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 32, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 32, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -27976,7 +22007,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006017, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -27985,7 +22016,7 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"Flash Controller", 0x00}, {0}, - {"USCI0", 0x1f}, + {"USCI0", 0x28}, {0}, {0}, {0}, @@ -27993,7 +22024,7 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"TimerB3", 0x00}, {"TimerA3", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -28031,27 +22062,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x07, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -28062,7 +22073,7 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x21] = 0x23, + [0x22] = 0x24, }, .v3_erase = &erase_fll, .v3_write = &write_fll, @@ -28080,102 +22091,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 49152, .offset = 0x04000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, - .bank_size = 64, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 32, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 32, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -28187,7 +22176,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006017, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -28196,7 +22185,7 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"Flash Controller", 0x00}, {0}, - {"USCI0", 0x1f}, + {"USCI0", 0x28}, {0}, {0}, {0}, @@ -28204,7 +22193,7 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"TimerB3", 0x00}, {"TimerA3", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -28242,27 +22231,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x07, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -28273,7 +22242,7 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x21] = 0x23, + [0x22] = 0x24, }, .v3_erase = &erase_fll, .v3_write = &write_fll, @@ -28291,102 +22260,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, - .bank_size = 64, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 32, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 32, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -28398,7 +22345,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006017, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -28407,7 +22354,7 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"Flash Controller", 0x00}, {0}, - {"USCI0", 0x1f}, + {"USCI0", 0x28}, {0}, {0}, {0}, @@ -28415,7 +22362,7 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"TimerB3", 0x00}, {"TimerA3", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -28453,27 +22400,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x07, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -28484,7 +22411,7 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x21] = 0x23, + [0x22] = 0x24, }, .v3_erase = &erase_fll, .v3_write = &write_fll, @@ -28502,102 +22429,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 61184, .offset = 0x01100, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, - .bank_size = 64, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 32, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 32, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -28609,7 +22514,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006017, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -28618,7 +22523,7 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"Flash Controller", 0x00}, {0}, - {"USCI0", 0x1f}, + {"USCI0", 0x28}, {0}, {0}, {0}, @@ -28626,7 +22531,7 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"TimerB3", 0x00}, {"TimerA3", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -28664,27 +22569,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x07, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -28695,7 +22580,7 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x21] = 0x23, + [0x22] = 0x24, }, .v3_erase = &erase_fll, .v3_write = &write_fll, @@ -28713,102 +22598,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 49152, .offset = 0x04000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, - .bank_size = 64, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 32, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 32, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -28820,7 +22683,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006017, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -28829,7 +22692,7 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"Flash Controller", 0x00}, {0}, - {"USCI0", 0x1f}, + {"USCI0", 0x28}, {0}, {0}, {0}, @@ -28837,7 +22700,7 @@ const struct chipinfo chipinfo_db[] = { { {0}, {"TimerB3", 0x00}, {"TimerA3", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -28875,27 +22738,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x07, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -28906,7 +22749,7 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x21] = 0x23, + [0x22] = 0x24, }, .v3_erase = &erase_fll, .v3_write = &write_fll, @@ -28924,102 +22767,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 64, - .bank_size = 64, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 32, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 32, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -29031,7 +22852,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -29086,27 +22907,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x1f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 2700, .vcc_max = 3600, @@ -29117,7 +22918,7 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x21] = 0x23, + [0x22] = 0x24, }, .v3_erase = &erase_fll, .v3_write = &write_fll, @@ -29136,102 +22937,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, - .bank_size = 128, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 21, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 21, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -29243,7 +23022,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -29298,27 +23077,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x1f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 2700, .vcc_max = 3600, @@ -29329,7 +23088,7 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x21] = 0x23, + [0x22] = 0x24, }, .v3_erase = &erase_fll, .v3_write = &write_fll, @@ -29348,102 +23107,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, - .bank_size = 128, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 21, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 21, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -29455,7 +23192,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -29510,27 +23247,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x1f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 2700, .vcc_max = 3600, @@ -29541,7 +23258,7 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x21] = 0x23, + [0x22] = 0x24, }, .v3_erase = &erase_fll, .v3_write = &write_fll, @@ -29560,102 +23277,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, - .bank_size = 128, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 21, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 21, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -29667,7 +23362,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -29722,27 +23417,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x1f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 2700, .vcc_max = 3600, @@ -29753,7 +23428,7 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x21] = 0x23, + [0x22] = 0x24, }, .v3_erase = &erase_fll, .v3_write = &write_fll, @@ -29772,102 +23447,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, - .bank_size = 128, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 21, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 21, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -29879,7 +23532,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -29934,27 +23587,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x1f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 2700, .vcc_max = 3600, @@ -29965,7 +23598,7 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x21] = 0x23, + [0x22] = 0x24, }, .v3_erase = &erase_fll, .v3_write = &write_fll, @@ -29984,102 +23617,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, - .bank_size = 128, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 21, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 512, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 21, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -30091,7 +23702,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 16, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x01, - .mclk_control = 0x60d7, + .mclk_control = 0x00000000, .clock_map = { {0}, {0}, @@ -30146,27 +23757,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x1f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x01, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x00, - .trig_dma = 0x00, - .trig_read_write = 0x00, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x00, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 2700, .vcc_max = 3600, @@ -30177,7 +23768,7 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x21] = 0x23, + [0x22] = 0x24, }, .v3_erase = &erase_fll, .v3_write = &write_fll, @@ -30196,102 +23787,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Info", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01000, .seg_size = 128, - .bank_size = 128, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "boot", + .name = "Bsl", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x00c00, .seg_size = 512, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 21, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 21, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -30303,7 +23872,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006017, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -30311,16 +23880,16 @@ const struct chipinfo chipinfo_db[] = { { {"ACLK (Pin)", 0x00}, {0}, {"Flash Control", 0x00}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, {0}, - {"BTRTC", 0x29}, + {"BTRTC", 0x8a}, {0}, {"TimerB3", 0x00}, {"TimerA3", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -30358,27 +23927,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x0f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x03, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x08, - .trig_options = 0x01, - .trig_dma = 0x00, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x01, - .seq_start = 0x02, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -30389,20 +23938,20 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x11] = 0x26, [0x12] = 0x27, [0x13] = 0x28, - [0x15] = 0x2a, + [0x14] = 0x29, [0x16] = 0x2b, - [0x18] = 0x2d, + [0x17] = 0x2c, [0x19] = 0x2e, - [0x1b] = 0x2f, + [0x1a] = 0x2f, [0x1c] = 0x30, [0x1d] = 0x31, [0x1e] = 0x32, [0x1f] = 0x33, - [0x21] = 0x35, - [0x25] = 0x36, + [0x20] = 0x34, + [0x22] = 0x36, + [0x26] = 0x37, }, .v3_erase = &erase_xfll, .v3_write = &write_xfll, @@ -30420,113 +23969,91 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 122624, .offset = 0x02100, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01000, - .seg_size = 64, - .bank_size = 64, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 1024, - .offset = 0x00c00, - .seg_size = 512, - .bank_size = 0, - .banks = 1, - }, - { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 21, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x00200, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram2", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01000, + .seg_size = 64, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x00c00, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x00200, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 21, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -30538,7 +24065,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006017, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -30546,16 +24073,16 @@ const struct chipinfo chipinfo_db[] = { { {"ACLK (Pin)", 0x00}, {0}, {"Flash Control", 0x00}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, {0}, - {"BTRTC", 0x29}, + {"BTRTC", 0x8a}, {0}, {"TimerB3", 0x00}, {"TimerA3", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -30593,27 +24120,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x0f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x03, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x08, - .trig_options = 0x01, - .trig_dma = 0x00, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x01, - .seq_start = 0x02, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -30624,20 +24131,20 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x11] = 0x26, [0x12] = 0x27, [0x13] = 0x28, - [0x15] = 0x2a, + [0x14] = 0x29, [0x16] = 0x2b, - [0x18] = 0x2d, + [0x17] = 0x2c, [0x19] = 0x2e, - [0x1b] = 0x2f, + [0x1a] = 0x2f, [0x1c] = 0x30, [0x1d] = 0x31, [0x1e] = 0x32, [0x1f] = 0x33, - [0x21] = 0x35, - [0x25] = 0x36, + [0x20] = 0x34, + [0x22] = 0x36, + [0x26] = 0x37, }, .v3_erase = &erase_xfll, .v3_write = &write_xfll, @@ -30655,113 +24162,91 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 118528, .offset = 0x03100, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01000, - .seg_size = 64, - .bank_size = 64, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 1024, - .offset = 0x00c00, - .seg_size = 512, - .bank_size = 0, - .banks = 1, - }, - { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 21, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x00200, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram2", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x01100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01000, + .seg_size = 64, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x00c00, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x00200, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 21, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -30773,7 +24258,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006017, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -30781,16 +24266,16 @@ const struct chipinfo chipinfo_db[] = { { {"ACLK (Pin)", 0x00}, {0}, {"Flash Control", 0x00}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, {0}, - {"BTRTC", 0x29}, + {"BTRTC", 0x8a}, {0}, {"TimerB3", 0x00}, {"TimerA3", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -30828,27 +24313,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x0f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x03, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x08, - .trig_options = 0x01, - .trig_dma = 0x00, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x01, - .seq_start = 0x02, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -30859,20 +24324,20 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x11] = 0x26, [0x12] = 0x27, [0x13] = 0x28, - [0x15] = 0x2a, + [0x14] = 0x29, [0x16] = 0x2b, - [0x18] = 0x2d, + [0x17] = 0x2c, [0x19] = 0x2e, - [0x1b] = 0x2f, + [0x1a] = 0x2f, [0x1c] = 0x30, [0x1d] = 0x31, [0x1e] = 0x32, [0x1f] = 0x33, - [0x21] = 0x35, - [0x25] = 0x36, + [0x20] = 0x34, + [0x22] = 0x36, + [0x26] = 0x37, }, .v3_erase = &erase_xfll, .v3_write = &write_xfll, @@ -30890,113 +24355,91 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 93952, .offset = 0x03100, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01000, - .seg_size = 64, - .bank_size = 64, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 1024, - .offset = 0x00c00, - .seg_size = 512, - .bank_size = 0, - .banks = 1, - }, - { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 21, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x00200, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram2", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x01100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01000, + .seg_size = 64, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x00c00, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x00200, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 21, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -31008,7 +24451,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006017, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -31016,16 +24459,16 @@ const struct chipinfo chipinfo_db[] = { { {"ACLK (Pin)", 0x00}, {0}, {"Flash Control", 0x00}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, {0}, - {"BTRTC", 0x29}, + {"BTRTC", 0x8a}, {0}, {"TimerB3", 0x00}, {"TimerA3", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -31063,27 +24506,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x0f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x03, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x08, - .trig_options = 0x01, - .trig_dma = 0x00, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x01, - .seq_start = 0x02, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -31094,20 +24517,20 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x11] = 0x26, [0x12] = 0x27, [0x13] = 0x28, - [0x15] = 0x2a, + [0x14] = 0x29, [0x16] = 0x2b, - [0x18] = 0x2d, + [0x17] = 0x2c, [0x19] = 0x2e, - [0x1b] = 0x2f, + [0x1a] = 0x2f, [0x1c] = 0x30, [0x1d] = 0x31, [0x1e] = 0x32, [0x1f] = 0x33, - [0x21] = 0x35, - [0x25] = 0x36, + [0x20] = 0x34, + [0x22] = 0x36, + [0x26] = 0x37, }, .v3_erase = &erase_xfll, .v3_write = &write_xfll, @@ -31125,113 +24548,91 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 93952, .offset = 0x02100, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01000, - .seg_size = 64, - .bank_size = 64, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 1024, - .offset = 0x00c00, - .seg_size = 512, - .bank_size = 0, - .banks = 1, - }, - { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 21, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x00200, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram2", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01000, + .seg_size = 64, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x00c00, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x00200, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 21, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -31243,7 +24644,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006017, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -31251,16 +24652,16 @@ const struct chipinfo chipinfo_db[] = { { {"ACLK (Pin)", 0x00}, {0}, {"Flash Control", 0x00}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, {0}, - {"BTRTC", 0x29}, + {"BTRTC", 0x8a}, {0}, {"TimerB3", 0x00}, {"TimerA3", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -31298,27 +24699,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x0f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x03, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x08, - .trig_options = 0x01, - .trig_dma = 0x00, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x01, - .seq_start = 0x02, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -31329,20 +24710,20 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x11] = 0x26, [0x12] = 0x27, [0x13] = 0x28, - [0x15] = 0x2a, + [0x14] = 0x29, [0x16] = 0x2b, - [0x18] = 0x2d, + [0x17] = 0x2c, [0x19] = 0x2e, - [0x1b] = 0x2f, + [0x1a] = 0x2f, [0x1c] = 0x30, [0x1d] = 0x31, [0x1e] = 0x32, [0x1f] = 0x33, - [0x21] = 0x35, - [0x25] = 0x36, + [0x20] = 0x34, + [0x22] = 0x36, + [0x26] = 0x37, }, .v3_erase = &erase_xfll, .v3_write = &write_xfll, @@ -31360,113 +24741,91 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 122624, .offset = 0x02100, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01000, - .seg_size = 64, - .bank_size = 64, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 1024, - .offset = 0x00c00, - .seg_size = 512, - .bank_size = 0, - .banks = 1, - }, - { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 21, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x00200, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram2", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01000, + .seg_size = 64, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x00c00, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x00200, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 21, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -31478,7 +24837,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006017, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -31486,16 +24845,16 @@ const struct chipinfo chipinfo_db[] = { { {"ACLK (Pin)", 0x00}, {0}, {"Flash Control", 0x00}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, {0}, - {"BTRTC", 0x29}, + {"BTRTC", 0x8a}, {0}, {"TimerB3", 0x00}, {"TimerA3", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -31533,27 +24892,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x0f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x03, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x08, - .trig_options = 0x01, - .trig_dma = 0x00, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x01, - .seq_start = 0x02, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -31564,20 +24903,20 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x11] = 0x26, [0x12] = 0x27, [0x13] = 0x28, - [0x15] = 0x2a, + [0x14] = 0x29, [0x16] = 0x2b, - [0x18] = 0x2d, + [0x17] = 0x2c, [0x19] = 0x2e, - [0x1b] = 0x2f, + [0x1a] = 0x2f, [0x1c] = 0x30, [0x1d] = 0x31, [0x1e] = 0x32, [0x1f] = 0x33, - [0x21] = 0x35, - [0x25] = 0x36, + [0x20] = 0x34, + [0x22] = 0x36, + [0x26] = 0x37, }, .v3_erase = &erase_xfll, .v3_write = &write_xfll, @@ -31595,113 +24934,91 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 118528, .offset = 0x03100, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01000, - .seg_size = 64, - .bank_size = 64, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 1024, - .offset = 0x00c00, - .seg_size = 512, - .bank_size = 0, - .banks = 1, - }, - { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 21, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x00200, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram2", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x01100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01000, + .seg_size = 64, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x00c00, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x00200, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 21, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -31713,7 +25030,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006017, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -31721,16 +25038,16 @@ const struct chipinfo chipinfo_db[] = { { {"ACLK (Pin)", 0x00}, {0}, {"Flash Control", 0x00}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, {0}, - {"BTRTC", 0x29}, + {"BTRTC", 0x8a}, {0}, {"TimerB3", 0x00}, {"TimerA3", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -31768,27 +25085,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x0f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x03, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x08, - .trig_options = 0x01, - .trig_dma = 0x00, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x01, - .seq_start = 0x02, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -31799,20 +25096,20 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x11] = 0x26, [0x12] = 0x27, [0x13] = 0x28, - [0x15] = 0x2a, + [0x14] = 0x29, [0x16] = 0x2b, - [0x18] = 0x2d, + [0x17] = 0x2c, [0x19] = 0x2e, - [0x1b] = 0x2f, + [0x1a] = 0x2f, [0x1c] = 0x30, [0x1d] = 0x31, [0x1e] = 0x32, [0x1f] = 0x33, - [0x21] = 0x35, - [0x25] = 0x36, + [0x20] = 0x34, + [0x22] = 0x36, + [0x26] = 0x37, }, .v3_erase = &erase_xfll, .v3_write = &write_xfll, @@ -31830,113 +25127,91 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 93952, .offset = 0x03100, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01000, - .seg_size = 64, - .bank_size = 64, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 1024, - .offset = 0x00c00, - .seg_size = 512, - .bank_size = 0, - .banks = 1, - }, - { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 21, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x00200, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram2", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x01100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01000, + .seg_size = 64, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x00c00, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x00200, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 21, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -31948,7 +25223,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006017, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -31956,16 +25231,16 @@ const struct chipinfo chipinfo_db[] = { { {"ACLK (Pin)", 0x00}, {0}, {"Flash Control", 0x00}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, {0}, - {"BTRTC", 0x29}, + {"BTRTC", 0x8a}, {0}, {"TimerB3", 0x00}, {"TimerA3", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -32003,27 +25278,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x0f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x03, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x08, - .trig_options = 0x01, - .trig_dma = 0x00, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x01, - .seq_start = 0x02, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -32034,20 +25289,20 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x11] = 0x26, [0x12] = 0x27, [0x13] = 0x28, - [0x15] = 0x2a, + [0x14] = 0x29, [0x16] = 0x2b, - [0x18] = 0x2d, + [0x17] = 0x2c, [0x19] = 0x2e, - [0x1b] = 0x2f, + [0x1a] = 0x2f, [0x1c] = 0x30, [0x1d] = 0x31, [0x1e] = 0x32, [0x1f] = 0x33, - [0x21] = 0x35, - [0x25] = 0x36, + [0x20] = 0x34, + [0x22] = 0x36, + [0x26] = 0x37, }, .v3_erase = &erase_xfll, .v3_write = &write_xfll, @@ -32065,113 +25320,91 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 93952, .offset = 0x02100, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01000, - .seg_size = 64, - .bank_size = 64, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 1024, - .offset = 0x00c00, - .seg_size = 512, - .bank_size = 0, - .banks = 1, - }, - { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 21, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x00200, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram2", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01000, + .seg_size = 64, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x00c00, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x00200, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 21, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -32183,7 +25416,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006017, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -32191,16 +25424,16 @@ const struct chipinfo chipinfo_db[] = { { {"ACLK (Pin)", 0x00}, {0}, {"Flash Control", 0x00}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, {0}, - {"BTRTC", 0x29}, + {"BTRTC", 0x8a}, {0}, {"TimerB3", 0x00}, {"TimerA3", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -32238,27 +25471,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x0f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x03, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x08, - .trig_options = 0x01, - .trig_dma = 0x00, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x01, - .seq_start = 0x02, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -32269,20 +25482,20 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x11] = 0x26, [0x12] = 0x27, [0x13] = 0x28, - [0x15] = 0x2a, + [0x14] = 0x29, [0x16] = 0x2b, - [0x18] = 0x2d, + [0x17] = 0x2c, [0x19] = 0x2e, - [0x1b] = 0x2f, + [0x1a] = 0x2f, [0x1c] = 0x30, [0x1d] = 0x31, [0x1e] = 0x32, [0x1f] = 0x33, - [0x21] = 0x35, - [0x25] = 0x36, + [0x20] = 0x34, + [0x22] = 0x36, + [0x26] = 0x37, }, .v3_erase = &erase_xfll, .v3_write = &write_xfll, @@ -32300,113 +25513,91 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 122624, .offset = 0x02100, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01000, - .seg_size = 64, - .bank_size = 64, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 1024, - .offset = 0x00c00, - .seg_size = 512, - .bank_size = 0, - .banks = 1, - }, - { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 21, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x00200, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram2", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01000, + .seg_size = 64, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x00c00, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x00200, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 21, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -32418,7 +25609,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006017, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -32426,16 +25617,16 @@ const struct chipinfo chipinfo_db[] = { { {"ACLK (Pin)", 0x00}, {0}, {"Flash Control", 0x00}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, {0}, - {"BTRTC", 0x29}, + {"BTRTC", 0x8a}, {0}, {"TimerB3", 0x00}, {"TimerA3", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -32473,27 +25664,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x0f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x03, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x08, - .trig_options = 0x01, - .trig_dma = 0x00, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x01, - .seq_start = 0x02, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -32504,20 +25675,20 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x11] = 0x26, [0x12] = 0x27, [0x13] = 0x28, - [0x15] = 0x2a, + [0x14] = 0x29, [0x16] = 0x2b, - [0x18] = 0x2d, + [0x17] = 0x2c, [0x19] = 0x2e, - [0x1b] = 0x2f, + [0x1a] = 0x2f, [0x1c] = 0x30, [0x1d] = 0x31, [0x1e] = 0x32, [0x1f] = 0x33, - [0x21] = 0x35, - [0x25] = 0x36, + [0x20] = 0x34, + [0x22] = 0x36, + [0x26] = 0x37, }, .v3_erase = &erase_xfll, .v3_write = &write_xfll, @@ -32535,113 +25706,91 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 118528, .offset = 0x03100, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01000, - .seg_size = 64, - .bank_size = 64, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 1024, - .offset = 0x00c00, - .seg_size = 512, - .bank_size = 0, - .banks = 1, - }, - { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 21, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x00200, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram2", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x01100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01000, + .seg_size = 64, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x00c00, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x00200, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 21, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -32653,7 +25802,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006017, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -32661,16 +25810,16 @@ const struct chipinfo chipinfo_db[] = { { {"ACLK (Pin)", 0x00}, {0}, {"Flash Control", 0x00}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, {0}, - {"BTRTC", 0x29}, + {"BTRTC", 0x8a}, {0}, {"TimerB3", 0x00}, {"TimerA3", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -32708,27 +25857,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x0f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x03, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x08, - .trig_options = 0x01, - .trig_dma = 0x00, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x01, - .seq_start = 0x02, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -32739,20 +25868,20 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x11] = 0x26, [0x12] = 0x27, [0x13] = 0x28, - [0x15] = 0x2a, + [0x14] = 0x29, [0x16] = 0x2b, - [0x18] = 0x2d, + [0x17] = 0x2c, [0x19] = 0x2e, - [0x1b] = 0x2f, + [0x1a] = 0x2f, [0x1c] = 0x30, [0x1d] = 0x31, [0x1e] = 0x32, [0x1f] = 0x33, - [0x21] = 0x35, - [0x25] = 0x36, + [0x20] = 0x34, + [0x22] = 0x36, + [0x26] = 0x37, }, .v3_erase = &erase_xfll, .v3_write = &write_xfll, @@ -32770,113 +25899,91 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 93952, .offset = 0x03100, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01000, - .seg_size = 64, - .bank_size = 64, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 1024, - .offset = 0x00c00, - .seg_size = 512, - .bank_size = 0, - .banks = 1, - }, - { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 21, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x00200, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram2", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x01100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01000, + .seg_size = 64, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x00c00, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x00200, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 21, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -32888,7 +25995,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006017, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -32896,16 +26003,16 @@ const struct chipinfo chipinfo_db[] = { { {"ACLK (Pin)", 0x00}, {0}, {"Flash Control", 0x00}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, {0}, - {"BTRTC", 0x29}, + {"BTRTC", 0x8a}, {0}, {"TimerB3", 0x00}, {"TimerA3", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -32943,27 +26050,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x0f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x03, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x08, - .trig_options = 0x01, - .trig_dma = 0x00, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x01, - .seq_start = 0x02, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -32974,20 +26061,20 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x11] = 0x26, [0x12] = 0x27, [0x13] = 0x28, - [0x15] = 0x2a, + [0x14] = 0x29, [0x16] = 0x2b, - [0x18] = 0x2d, + [0x17] = 0x2c, [0x19] = 0x2e, - [0x1b] = 0x2f, + [0x1a] = 0x2f, [0x1c] = 0x30, [0x1d] = 0x31, [0x1e] = 0x32, [0x1f] = 0x33, - [0x21] = 0x35, - [0x25] = 0x36, + [0x20] = 0x34, + [0x22] = 0x36, + [0x26] = 0x37, }, .v3_erase = &erase_xfll, .v3_write = &write_xfll, @@ -33005,113 +26092,91 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 93952, .offset = 0x02100, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01000, - .seg_size = 64, - .bank_size = 64, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 1024, - .offset = 0x00c00, - .seg_size = 512, - .bank_size = 0, - .banks = 1, - }, - { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 21, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x00200, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram2", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01000, + .seg_size = 64, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x00c00, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x00200, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 21, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -33123,7 +26188,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006017, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -33131,16 +26196,16 @@ const struct chipinfo chipinfo_db[] = { { {"ACLK (Pin)", 0x00}, {0}, {"Flash Control", 0x00}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, {0}, - {"BTRTC", 0x29}, + {"BTRTC", 0x8a}, {0}, {"TimerB3", 0x00}, {"TimerA3", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -33178,27 +26243,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x0f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x03, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x08, - .trig_options = 0x01, - .trig_dma = 0x00, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x01, - .seq_start = 0x02, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -33209,20 +26254,20 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x11] = 0x26, [0x12] = 0x27, [0x13] = 0x28, - [0x15] = 0x2a, + [0x14] = 0x29, [0x16] = 0x2b, - [0x18] = 0x2d, + [0x17] = 0x2c, [0x19] = 0x2e, - [0x1b] = 0x2f, + [0x1a] = 0x2f, [0x1c] = 0x30, [0x1d] = 0x31, [0x1e] = 0x32, [0x1f] = 0x33, - [0x21] = 0x35, - [0x25] = 0x36, + [0x20] = 0x34, + [0x22] = 0x36, + [0x26] = 0x37, }, .v3_erase = &erase_xfll, .v3_write = &write_xfll, @@ -33240,113 +26285,91 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 57344, .offset = 0x02000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01000, - .seg_size = 64, - .bank_size = 64, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 1024, - .offset = 0x00c00, - .seg_size = 512, - .bank_size = 0, - .banks = 1, - }, - { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 21, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x00200, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram2", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01000, + .seg_size = 64, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x00c00, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x00200, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 21, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -33358,7 +26381,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x60d7, + .mclk_control = 0x00006017, .clock_map = { {0}, {"MCLK (Pin)", 0x00}, @@ -33366,16 +26389,16 @@ const struct chipinfo chipinfo_db[] = { { {"ACLK (Pin)", 0x00}, {0}, {"Flash Control", 0x00}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, {0}, - {"BTRTC", 0x29}, + {"BTRTC", 0x8a}, {0}, {"TimerB3", 0x00}, {"TimerA3", 0x00}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -33413,27 +26436,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x0f, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x00, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x03, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x08, - .trig_options = 0x01, - .trig_dma = 0x00, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x01, - .seq_start = 0x02, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -33444,20 +26447,20 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x11] = 0x26, [0x12] = 0x27, [0x13] = 0x28, - [0x15] = 0x2a, + [0x14] = 0x29, [0x16] = 0x2b, - [0x18] = 0x2d, + [0x17] = 0x2c, [0x19] = 0x2e, - [0x1b] = 0x2f, + [0x1a] = 0x2f, [0x1c] = 0x30, [0x1d] = 0x31, [0x1e] = 0x32, [0x1f] = 0x33, - [0x21] = 0x35, - [0x25] = 0x36, + [0x20] = 0x34, + [0x22] = 0x36, + [0x26] = 0x37, }, .v3_erase = &erase_xfll, .v3_write = &write_xfll, @@ -33475,113 +26478,91 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 57344, .offset = 0x02000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01000, - .seg_size = 64, - .bank_size = 64, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 1024, - .offset = 0x00c00, - .seg_size = 512, - .bank_size = 0, - .banks = 1, - }, - { - .name = "lcd", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 21, - .offset = 0x00090, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x00200, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram2", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01000, + .seg_size = 64, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x00c00, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x00200, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 256, .offset = 0x00100, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral8bit", + .name = "Lcd", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 21, + .offset = 0x00090, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral8bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 8, .mapped = 1, .size = 256, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -33593,24 +26574,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000040f, .clock_map = { {0}, {0}, {0}, {0}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, {0}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -33648,27 +26629,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -33679,27 +26640,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -33715,91 +26675,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x05c00, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -33811,24 +26749,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000040f, .clock_map = { {0}, {0}, {0}, {0}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -33866,27 +26804,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -33897,27 +26815,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -33933,91 +26850,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x05c00, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -34029,24 +26924,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000040f, .clock_map = { {0}, {0}, {0}, {0}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, {0}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -34084,27 +26979,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -34115,27 +26990,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -34151,91 +27025,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 196608, .offset = 0x05c00, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -34247,24 +27099,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000040f, .clock_map = { {0}, {0}, {0}, {0}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -34302,27 +27154,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -34333,27 +27165,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -34369,91 +27200,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 196608, .offset = 0x05c00, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -34465,24 +27274,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000040f, .clock_map = { {0}, {0}, {0}, {0}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, {0}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -34520,27 +27329,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -34551,27 +27340,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -34587,91 +27375,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x05c00, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -34683,24 +27449,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000040f, .clock_map = { {0}, {0}, {0}, {0}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -34738,27 +27504,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -34769,27 +27515,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -34805,91 +27550,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x05c00, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -34901,24 +27624,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000040f, .clock_map = { {0}, {0}, {0}, {0}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -34956,27 +27679,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -34987,27 +27690,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -35023,91 +27725,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x05c00, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -35119,24 +27799,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, {0}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"USB", 0x03}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"USB", 0x40}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -35174,27 +27854,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -35205,27 +27865,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -35241,102 +27900,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -35348,24 +27985,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, - {"DAC12", 0x32}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, + {"DAC12", 0xc0}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, {0}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"USB", 0x03}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"USB", 0x40}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -35403,27 +28040,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -35434,27 +28051,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -35470,102 +28086,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -35577,24 +28171,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, - {"DAC12", 0x32}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, + {"DAC12", 0xc0}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, {0}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"USB", 0x03}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"USB", 0x40}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -35632,27 +28226,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -35663,27 +28237,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -35699,102 +28272,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 196608, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 3, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -35806,24 +28357,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, - {"DAC12", 0x32}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, + {"DAC12", 0xc0}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, {0}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"USB", 0x03}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"USB", 0x40}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -35861,27 +28412,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -35892,27 +28423,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -35928,102 +28458,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -36035,24 +28543,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000041f, .clock_map = { {0}, - {"LCDB", 0x2c}, + {"LCDB", 0xb0}, {0}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, {0}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"USB", 0x03}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"USB", 0x40}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -36090,27 +28598,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -36121,27 +28609,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -36157,102 +28644,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -36264,24 +28729,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000041f, .clock_map = { {0}, - {"LCDB", 0x2c}, - {"DAC12", 0x32}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, + {"LCDB", 0xb0}, + {"DAC12", 0xc0}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, {0}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"USB", 0x03}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"USB", 0x40}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -36319,27 +28784,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -36350,27 +28795,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -36386,102 +28830,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -36493,24 +28915,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000041f, .clock_map = { {0}, - {"LCDB", 0x2c}, - {"DAC12", 0x32}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, + {"LCDB", 0xb0}, + {"DAC12", 0xc0}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, {0}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"USB", 0x03}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"USB", 0x40}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -36548,27 +28970,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -36579,27 +28981,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -36615,102 +29016,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 196608, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 3, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -36722,24 +29101,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000041f, .clock_map = { {0}, - {"LCDB", 0x2c}, - {"DAC12", 0x32}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, + {"LCDB", 0xb0}, + {"DAC12", 0xc0}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, {0}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"USB", 0x03}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"USB", 0x40}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -36777,27 +29156,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -36808,27 +29167,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -36844,102 +29202,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -36951,24 +29287,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041d, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, + {"Comparator B", 0xa8}, {0}, - {"RTC", 0x28}, + {"RTC", 0x8a}, {0}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer1_D3", 0x13}, - {"Timer0_D3", 0x12}, - {"Timer0_A3", 0x08}, + {"Timer1_D3", 0x75}, + {"Timer0_D3", 0x74}, + {"Timer0_A3", 0x8e}, {0}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -37006,27 +29342,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -37037,27 +29353,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -37073,91 +29388,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -37169,24 +29462,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041d, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, - {"ADC10", 0x36}, - {"RTC", 0x28}, + {"Comparator B", 0xa8}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, {0}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer1_D3", 0x13}, - {"Timer0_D3", 0x12}, - {"Timer0_A3", 0x08}, + {"Timer1_D3", 0x75}, + {"Timer0_D3", 0x74}, + {"Timer0_A3", 0x8e}, {0}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -37224,27 +29517,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -37255,27 +29528,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -37291,91 +29563,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -37387,24 +29637,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041d, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, + {"Comparator B", 0xa8}, {0}, - {"RTC", 0x28}, + {"RTC", 0x8a}, {0}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer1_D3", 0x13}, - {"Timer0_D3", 0x12}, - {"Timer0_A3", 0x08}, + {"Timer1_D3", 0x75}, + {"Timer0_D3", 0x74}, + {"Timer0_A3", 0x8e}, {0}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -37442,27 +29692,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -37473,27 +29703,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -37509,91 +29738,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -37605,24 +29812,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041d, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, - {"ADC10", 0x36}, - {"RTC", 0x28}, + {"Comparator B", 0xa8}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, {0}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer1_D3", 0x13}, - {"Timer0_D3", 0x12}, - {"Timer0_A3", 0x08}, + {"Timer1_D3", 0x75}, + {"Timer0_D3", 0x74}, + {"Timer0_A3", 0x8e}, {0}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -37660,27 +29867,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -37691,27 +29878,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -37727,91 +29913,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -37823,24 +29987,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041d, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, + {"Comparator B", 0xa8}, {0}, - {"RTC", 0x28}, + {"RTC", 0x8a}, {0}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer1_D3", 0x13}, - {"Timer0_D3", 0x12}, - {"Timer0_A3", 0x08}, + {"Timer1_D3", 0x75}, + {"Timer0_D3", 0x74}, + {"Timer0_A3", 0x8e}, {0}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -37878,27 +30042,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -37909,27 +30053,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -37945,91 +30088,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -38041,24 +30162,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041d, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, - {"ADC10", 0x36}, - {"RTC", 0x28}, + {"Comparator B", 0xa8}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, {0}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer1_D3", 0x13}, - {"Timer0_D3", 0x12}, - {"Timer0_A3", 0x08}, + {"Timer1_D3", 0x75}, + {"Timer0_D3", 0x74}, + {"Timer0_A3", 0x8e}, {0}, - {"Watchdog Timer", 0x01}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -38096,27 +30217,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -38127,27 +30228,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -38163,91 +30263,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -38259,24 +30337,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, - {"ADC10", 0x36}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"USB", 0x03}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Comparator B", 0xa8}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"USB", 0x40}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -38314,27 +30392,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -38345,27 +30403,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -38381,102 +30438,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x02400, .seg_size = 1, - .bank_size = 2, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -38488,24 +30523,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, - {"ADC10", 0x36}, - {"RTC", 0x28}, + {"Comparator B", 0xa8}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, {0}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"USB", 0x03}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"USB", 0x40}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -38543,27 +30578,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -38574,27 +30589,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -38610,102 +30624,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x02400, .seg_size = 1, - .bank_size = 2, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -38717,24 +30709,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, - {"ADC10", 0x36}, - {"RTC", 0x28}, + {"Comparator B", 0xa8}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, {0}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"USB", 0x03}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"USB", 0x40}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -38772,27 +30764,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -38803,27 +30775,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -38839,102 +30810,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 24576, .offset = 0x0a000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x02400, .seg_size = 1, - .bank_size = 2, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -38946,24 +30895,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, - {"ADC10", 0x36}, - {"RTC", 0x28}, + {"Comparator B", 0xa8}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, {0}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"USB", 0x03}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"USB", 0x40}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -39001,27 +30950,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -39032,27 +30961,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -39068,102 +30996,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x02400, .seg_size = 1, - .bank_size = 2, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -39175,24 +31081,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, {0}, - {"ADC10", 0x36}, - {"RTC", 0x28}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, {0}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"USB", 0x03}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"USB", 0x40}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -39230,27 +31136,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -39261,27 +31147,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -39297,102 +31182,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x02400, .seg_size = 1, - .bank_size = 2, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -39404,24 +31267,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, {0}, - {"ADC10", 0x36}, - {"RTC", 0x28}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, {0}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"USB", 0x03}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"USB", 0x40}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -39459,27 +31322,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -39490,27 +31333,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -39526,102 +31368,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x02400, .seg_size = 1, - .bank_size = 2, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -39633,24 +31453,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, {0}, - {"ADC10", 0x36}, - {"RTC", 0x28}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, {0}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"USB", 0x03}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"USB", 0x40}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -39688,27 +31508,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -39719,27 +31519,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -39755,102 +31554,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 24576, .offset = 0x0a000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x02400, .seg_size = 1, - .bank_size = 2, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -39862,24 +31639,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, {0}, - {"ADC10", 0x36}, - {"RTC", 0x28}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, {0}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"USB", 0x03}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"USB", 0x40}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -39917,27 +31694,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -39948,27 +31705,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -39984,102 +31740,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x02400, .seg_size = 1, - .bank_size = 2, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -40091,24 +31825,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, - {"ADC10", 0x36}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"USB", 0x03}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Comparator B", 0xa8}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"USB", 0x40}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -40146,27 +31880,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -40177,27 +31891,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -40213,102 +31926,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x02400, .seg_size = 1, - .bank_size = 2, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -40320,24 +32011,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, - {"ADC10", 0x36}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"USB", 0x03}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Comparator B", 0xa8}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"USB", 0x40}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -40375,27 +32066,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -40406,27 +32077,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -40442,102 +32112,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 24576, .offset = 0x0a000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x02400, .seg_size = 1, - .bank_size = 2, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -40549,24 +32197,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, - {"ADC10", 0x36}, - {"RTC", 0x28}, + {"Comparator B", 0xa8}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, {0}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"USB", 0x03}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"USB", 0x40}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -40604,27 +32252,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -40635,27 +32263,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -40671,102 +32298,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x02400, .seg_size = 1, - .bank_size = 2, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -40778,24 +32383,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, + {"Comparator B", 0xa8}, {0}, - {"RTC", 0x28}, + {"RTC", 0x8a}, {0}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"USB", 0x03}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"USB", 0x40}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -40833,27 +32438,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -40864,27 +32449,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -40900,102 +32484,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -41007,24 +32569,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, + {"Comparator B", 0xa8}, {0}, - {"RTC", 0x28}, + {"RTC", 0x8a}, {0}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"USB", 0x03}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"USB", 0x40}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -41062,27 +32624,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -41093,27 +32635,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -41129,102 +32670,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 196608, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 3, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -41236,24 +32755,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, + {"Comparator B", 0xa8}, {0}, - {"RTC", 0x28}, + {"RTC", 0x8a}, {0}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"USB", 0x03}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"USB", 0x40}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -41291,27 +32810,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -41322,27 +32821,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -41358,102 +32856,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -41465,24 +32941,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, {0}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"USB", 0x03}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"USB", 0x40}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -41520,27 +32996,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -41551,27 +33007,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -41587,102 +33042,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -41694,24 +33127,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, {0}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"USB", 0x03}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"USB", 0x40}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -41749,27 +33182,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -41780,27 +33193,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -41816,102 +33228,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 196608, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 3, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -41923,24 +33313,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000041f, .clock_map = { {0}, - {"LCDB", 0x2c}, + {"LCDB", 0xb0}, {0}, - {"Comparator B", 0x2a}, + {"Comparator B", 0xa8}, {0}, - {"RTC", 0x28}, + {"RTC", 0x8a}, {0}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"USB", 0x03}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"USB", 0x40}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -41978,27 +33368,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -42009,27 +33379,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -42045,102 +33414,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -42152,24 +33499,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000041f, .clock_map = { {0}, - {"LCDB", 0x2c}, + {"LCDB", 0xb0}, {0}, - {"Comparator B", 0x2a}, + {"Comparator B", 0xa8}, {0}, - {"RTC", 0x28}, + {"RTC", 0x8a}, {0}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"USB", 0x03}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"USB", 0x40}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -42207,27 +33554,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -42238,27 +33565,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -42274,102 +33600,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 196608, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 3, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -42381,24 +33685,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000041f, .clock_map = { {0}, - {"LCDB", 0x2c}, + {"LCDB", 0xb0}, {0}, - {"Comparator B", 0x2a}, + {"Comparator B", 0xa8}, {0}, - {"RTC", 0x28}, + {"RTC", 0x8a}, {0}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"USB", 0x03}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"USB", 0x40}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -42436,27 +33740,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -42467,27 +33751,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -42503,102 +33786,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -42610,24 +33871,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000041f, .clock_map = { {0}, - {"LCDB", 0x2c}, + {"LCDB", 0xb0}, {0}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, {0}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"USB", 0x03}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"USB", 0x40}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -42665,27 +33926,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -42696,27 +33937,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -42732,102 +33972,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -42839,24 +34057,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000041f, .clock_map = { {0}, - {"LCDB", 0x2c}, + {"LCDB", 0xb0}, {0}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, {0}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"USB", 0x03}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"USB", 0x40}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -42894,27 +34112,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -42925,27 +34123,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -42961,102 +34158,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 196608, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 3, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -43068,24 +34243,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"SD24B", 0x35}, - {"ADC10", 0x36}, - {"RTC", 0x28}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, {0}, {0}, - {"Timer0_A3", 0x08}, - {"Timer1_A2", 0x06}, - {"Timer2_A2", 0x07}, - {"Timer3_A2", 0x0b}, - {"Watchdog Timer", 0x01}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -43123,27 +34298,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -43154,27 +34309,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -43184,97 +34338,75 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -43286,24 +34418,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"SD24B", 0x35}, - {"ADC10", 0x36}, - {"RTC", 0x28}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, {0}, {0}, - {"Timer0_A3", 0x08}, - {"Timer1_A2", 0x06}, - {"Timer2_A2", 0x07}, - {"Timer3_A2", 0x0b}, - {"Watchdog Timer", 0x01}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -43341,27 +34473,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -43372,27 +34484,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -43402,97 +34513,75 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -43504,24 +34593,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"SD24B", 0x35}, - {"ADC10", 0x36}, - {"RTC", 0x28}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, {0}, {0}, - {"Timer0_A3", 0x08}, - {"Timer1_A2", 0x06}, - {"Timer2_A2", 0x07}, - {"Timer3_A2", 0x0b}, - {"Watchdog Timer", 0x01}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -43559,27 +34648,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -43590,27 +34659,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -43620,97 +34688,75 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 49152, .offset = 0x04000, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -43722,24 +34768,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"SD24B", 0x35}, - {"ADC10", 0x36}, - {"RTC", 0x28}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, {0}, {0}, - {"Timer0_A3", 0x08}, - {"Timer1_A2", 0x06}, - {"Timer2_A2", 0x07}, - {"Timer3_A2", 0x0b}, - {"Watchdog Timer", 0x01}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -43777,27 +34823,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -43808,27 +34834,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -43838,97 +34863,75 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 65536, .offset = 0x04000, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -43940,24 +34943,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"SD24B", 0x35}, - {"ADC10", 0x36}, - {"RTC", 0x28}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, {0}, {0}, - {"Timer0_A3", 0x08}, - {"Timer1_A2", 0x06}, - {"Timer2_A2", 0x07}, - {"Timer3_A2", 0x0b}, - {"Watchdog Timer", 0x01}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -43995,27 +34998,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -44026,27 +35009,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -44056,97 +35038,75 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -44158,24 +35118,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"SD24B", 0x35}, - {"ADC10", 0x36}, - {"RTC", 0x28}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, {0}, {0}, - {"Timer0_A3", 0x08}, - {"Timer1_A2", 0x06}, - {"Timer2_A2", 0x07}, - {"Timer3_A2", 0x0b}, - {"Watchdog Timer", 0x01}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -44213,27 +35173,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -44244,27 +35184,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -44274,97 +35213,75 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -44376,24 +35293,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"SD24B", 0x35}, - {"ADC10", 0x36}, - {"RTC", 0x28}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, {0}, {0}, - {"Timer0_A3", 0x08}, - {"Timer1_A2", 0x06}, - {"Timer2_A2", 0x07}, - {"Timer3_A2", 0x0b}, - {"Watchdog Timer", 0x01}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -44431,27 +35348,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -44462,27 +35359,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -44492,97 +35388,75 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 49152, .offset = 0x04000, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -44594,24 +35468,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"SD24B", 0x35}, - {"ADC10", 0x36}, - {"RTC", 0x28}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, {0}, {0}, - {"Timer0_A3", 0x08}, - {"Timer1_A2", 0x06}, - {"Timer2_A2", 0x07}, - {"Timer3_A2", 0x0b}, - {"Watchdog Timer", 0x01}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -44649,27 +35523,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -44680,27 +35534,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -44710,97 +35563,75 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 65536, .offset = 0x04000, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -44812,24 +35643,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000043f, .clock_map = { {0}, {0}, {0}, - {"Comparator D", 0x2b}, - {"ADC10B", 0x37}, - {"RTC", 0x28}, + {"Comparator D", 0xa8}, + {"ADC10B", 0xd6}, + {"RTC", 0x8a}, {0}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"Timer0_B3", 0x16}, - {"Timer1_B3", 0x17}, - {"Timer2_B3", 0x18}, - {"Timer0_A3", 0x08}, - {"Timer1_A3", 0x09}, - {"Watchdog Timer", 0x01}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B3", 0x97}, + {"Timer1_B3", 0x98}, + {"Timer2_B3", 0x99}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -44867,27 +35698,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -44898,23 +35709,23 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x38, - [0x11] = 0x39, + [0x09] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, @@ -44924,100 +35735,100 @@ const struct chipinfo chipinfo_db[] = { { | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { - .reg_mask = 0x10018, - .enable_lpm5 = 0x10010, - .disable_lpm5 = 0x00018, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x0f000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01800, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, - .size = 4096, - .offset = 0x00000, + .size = 4064, + .offset = 0x00020, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "EEM", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, + .bits = 16, + .mapped = 1, + .size = 6, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -45029,24 +35840,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000043f, .clock_map = { {0}, {0}, {0}, - {"Comparator D", 0x2b}, - {"ADC10B", 0x37}, - {"RTC", 0x28}, + {"Comparator D", 0xa8}, + {"ADC10B", 0xd6}, + {"RTC", 0x8a}, {0}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"Timer0_B3", 0x16}, - {"Timer1_B3", 0x17}, - {"Timer2_B3", 0x18}, - {"Timer0_A3", 0x08}, - {"Timer1_A3", 0x09}, - {"Watchdog Timer", 0x01}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B3", 0x97}, + {"Timer1_B3", 0x98}, + {"Timer2_B3", 0x99}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -45084,27 +35895,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -45115,23 +35906,23 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x38, - [0x11] = 0x39, + [0x09] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, @@ -45141,100 +35932,100 @@ const struct chipinfo chipinfo_db[] = { { | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { - .reg_mask = 0x10018, - .enable_lpm5 = 0x10010, - .disable_lpm5 = 0x00018, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01800, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, - .size = 4096, - .offset = 0x00000, + .size = 4064, + .offset = 0x00020, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "EEM", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, + .bits = 16, + .mapped = 1, + .size = 6, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -45246,24 +36037,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000043f, .clock_map = { {0}, {0}, {0}, - {"Comparator D", 0x2b}, + {"Comparator D", 0xa8}, {0}, - {"RTC", 0x28}, + {"RTC", 0x8a}, {0}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"Timer0_B3", 0x16}, - {"Timer1_B3", 0x17}, - {"Timer2_B3", 0x18}, - {"Timer0_A3", 0x08}, - {"Timer1_A3", 0x09}, - {"Watchdog Timer", 0x01}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B3", 0x97}, + {"Timer1_B3", 0x98}, + {"Timer2_B3", 0x99}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -45301,27 +36092,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -45332,23 +36103,23 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x38, - [0x11] = 0x39, + [0x09] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, @@ -45358,100 +36129,100 @@ const struct chipinfo chipinfo_db[] = { { | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { - .reg_mask = 0x10018, - .enable_lpm5 = 0x10010, - .disable_lpm5 = 0x00018, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 15872, .offset = 0x0c200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01800, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, - .size = 4096, - .offset = 0x00000, + .size = 4064, + .offset = 0x00020, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "EEM", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, + .bits = 16, + .mapped = 1, + .size = 6, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -45463,24 +36234,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x00000427, .clock_map = { {0}, {0}, {0}, - {"Comparator D", 0x2b}, - {"ADC10B", 0x37}, - {"RTC", 0x28}, + {"Comparator D", 0xa8}, + {"ADC10B", 0xd6}, + {"RTC", 0x8a}, {0}, - {"eUSCIB0", 0x27}, + {"eUSCIB0", 0x30}, {0}, - {"eUSCIA0", 0x23}, - {"Timer0_B3", 0x16}, + {"eUSCIA0", 0x2c}, + {"Timer0_B3", 0x97}, {0}, {0}, - {"Timer0_A3", 0x08}, - {"Timer1_A3", 0x09}, - {"Watchdog Timer", 0x01}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -45518,27 +36289,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -45549,23 +36300,23 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x38, - [0x11] = 0x39, + [0x09] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, @@ -45575,100 +36326,100 @@ const struct chipinfo chipinfo_db[] = { { | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { - .reg_mask = 0x10018, - .enable_lpm5 = 0x10010, - .disable_lpm5 = 0x00018, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 15872, .offset = 0x0c200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01800, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, - .size = 4096, - .offset = 0x00000, + .size = 4064, + .offset = 0x00020, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "EEM", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, + .bits = 16, + .mapped = 1, + .size = 6, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -45680,24 +36431,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000043f, .clock_map = { {0}, {0}, {0}, - {"Comparator D", 0x2b}, - {"ADC10B", 0x37}, - {"RTC", 0x28}, + {"Comparator D", 0xa8}, + {"ADC10B", 0xd6}, + {"RTC", 0x8a}, {0}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"Timer0_B3", 0x16}, - {"Timer1_B3", 0x17}, - {"Timer2_B3", 0x18}, - {"Timer0_A3", 0x08}, - {"Timer1_A3", 0x09}, - {"Watchdog Timer", 0x01}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B3", 0x97}, + {"Timer1_B3", 0x98}, + {"Timer2_B3", 0x99}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -45735,27 +36486,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -45766,23 +36497,23 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x38, - [0x11] = 0x39, + [0x09] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, @@ -45792,100 +36523,100 @@ const struct chipinfo chipinfo_db[] = { { | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { - .reg_mask = 0x10018, - .enable_lpm5 = 0x10010, - .disable_lpm5 = 0x00018, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 15872, .offset = 0x0c200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01800, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, - .size = 4096, - .offset = 0x00000, + .size = 4064, + .offset = 0x00020, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "EEM", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, + .bits = 16, + .mapped = 1, + .size = 6, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -45897,24 +36628,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x00000427, .clock_map = { {0}, {0}, {0}, - {"Comparator D", 0x2b}, - {"ADC10B", 0x37}, - {"RTC", 0x28}, + {"Comparator D", 0xa8}, + {"ADC10B", 0xd6}, + {"RTC", 0x8a}, {0}, - {"eUSCIB0", 0x27}, + {"eUSCIB0", 0x30}, {0}, - {"eUSCIA0", 0x23}, - {"Timer0_B3", 0x16}, + {"eUSCIA0", 0x2c}, + {"Timer0_B3", 0x97}, {0}, {0}, - {"Timer0_A3", 0x08}, - {"Timer1_A3", 0x09}, - {"Watchdog Timer", 0x01}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -45952,27 +36683,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -45983,23 +36694,23 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x38, - [0x11] = 0x39, + [0x09] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, @@ -46009,100 +36720,100 @@ const struct chipinfo chipinfo_db[] = { { | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { - .reg_mask = 0x10018, - .enable_lpm5 = 0x10010, - .disable_lpm5 = 0x00018, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x0f000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01800, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, - .size = 4096, - .offset = 0x00000, + .size = 4064, + .offset = 0x00020, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "EEM", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, + .bits = 16, + .mapped = 1, + .size = 6, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -46114,24 +36825,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000043f, .clock_map = { {0}, {0}, {0}, - {"Comparator D", 0x2b}, - {"ADC10B", 0x37}, - {"RTC", 0x28}, + {"Comparator D", 0xa8}, + {"ADC10B", 0xd6}, + {"RTC", 0x8a}, {0}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"Timer0_B3", 0x16}, - {"Timer1_B3", 0x17}, - {"Timer2_B3", 0x18}, - {"Timer0_A3", 0x08}, - {"Timer1_A3", 0x09}, - {"Watchdog Timer", 0x01}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B3", 0x97}, + {"Timer1_B3", 0x98}, + {"Timer2_B3", 0x99}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -46169,27 +36880,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -46200,23 +36891,23 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x38, - [0x11] = 0x39, + [0x09] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, @@ -46226,100 +36917,100 @@ const struct chipinfo chipinfo_db[] = { { | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { - .reg_mask = 0x10018, - .enable_lpm5 = 0x10010, - .disable_lpm5 = 0x00018, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x0f000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01800, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, - .size = 4096, - .offset = 0x00000, + .size = 4064, + .offset = 0x00020, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "EEM", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, + .bits = 16, + .mapped = 1, + .size = 6, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -46331,24 +37022,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000043f, .clock_map = { {0}, {0}, {0}, - {"Comparator D", 0x2b}, + {"Comparator D", 0xa8}, {0}, - {"RTC", 0x28}, + {"RTC", 0x8a}, {0}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"Timer0_B3", 0x16}, - {"Timer1_B3", 0x17}, - {"Timer2_B3", 0x18}, - {"Timer0_A3", 0x08}, - {"Timer1_A3", 0x09}, - {"Watchdog Timer", 0x01}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B3", 0x97}, + {"Timer1_B3", 0x98}, + {"Timer2_B3", 0x99}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -46386,27 +37077,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -46417,23 +37088,23 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x38, - [0x11] = 0x39, + [0x09] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, @@ -46443,100 +37114,100 @@ const struct chipinfo chipinfo_db[] = { { | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { - .reg_mask = 0x10018, - .enable_lpm5 = 0x10010, - .disable_lpm5 = 0x00018, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01800, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, - .size = 4096, - .offset = 0x00000, + .size = 4064, + .offset = 0x00020, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "EEM", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, + .bits = 16, + .mapped = 1, + .size = 6, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -46548,24 +37219,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x00000427, .clock_map = { {0}, {0}, {0}, - {"Comparator D", 0x2b}, - {"ADC10B", 0x37}, - {"RTC", 0x28}, + {"Comparator D", 0xa8}, + {"ADC10B", 0xd6}, + {"RTC", 0x8a}, {0}, - {"eUSCIB0", 0x27}, + {"eUSCIB0", 0x30}, {0}, - {"eUSCIA0", 0x23}, - {"Timer0_B3", 0x16}, + {"eUSCIA0", 0x2c}, + {"Timer0_B3", 0x97}, {0}, {0}, - {"Timer0_A3", 0x08}, - {"Timer1_A3", 0x09}, - {"Watchdog Timer", 0x01}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -46603,27 +37274,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -46634,23 +37285,23 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x38, - [0x11] = 0x39, + [0x09] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, @@ -46660,100 +37311,100 @@ const struct chipinfo chipinfo_db[] = { { | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { - .reg_mask = 0x10018, - .enable_lpm5 = 0x10010, - .disable_lpm5 = 0x00018, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01800, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, - .size = 4096, - .offset = 0x00000, + .size = 4064, + .offset = 0x00020, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "EEM", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, + .bits = 16, + .mapped = 1, + .size = 6, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -46765,24 +37416,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000043f, .clock_map = { {0}, {0}, {0}, - {"Comparator D", 0x2b}, + {"Comparator D", 0xa8}, {0}, - {"RTC", 0x28}, + {"RTC", 0x8a}, {0}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"Timer0_B3", 0x16}, - {"Timer1_B3", 0x17}, - {"Timer2_B3", 0x18}, - {"Timer0_A3", 0x08}, - {"Timer1_A3", 0x09}, - {"Watchdog Timer", 0x01}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B3", 0x97}, + {"Timer1_B3", 0x98}, + {"Timer2_B3", 0x99}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -46820,27 +37471,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -46851,23 +37482,23 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x38, - [0x11] = 0x39, + [0x09] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, @@ -46877,100 +37508,100 @@ const struct chipinfo chipinfo_db[] = { { | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { - .reg_mask = 0x10018, - .enable_lpm5 = 0x10010, - .disable_lpm5 = 0x00018, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 15872, .offset = 0x0c200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01800, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, - .size = 4096, - .offset = 0x00000, + .size = 4064, + .offset = 0x00020, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "EEM", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, + .bits = 16, + .mapped = 1, + .size = 6, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -46982,24 +37613,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x00000427, .clock_map = { {0}, {0}, {0}, - {"Comparator D", 0x2b}, - {"ADC10B", 0x37}, - {"RTC", 0x28}, + {"Comparator D", 0xa8}, + {"ADC10B", 0xd6}, + {"RTC", 0x8a}, {0}, - {"eUSCIB0", 0x27}, + {"eUSCIB0", 0x30}, {0}, - {"eUSCIA0", 0x23}, - {"Timer0_B3", 0x16}, + {"eUSCIA0", 0x2c}, + {"Timer0_B3", 0x97}, {0}, {0}, - {"Timer0_A3", 0x08}, - {"Timer1_A3", 0x09}, - {"Watchdog Timer", 0x01}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -47037,27 +37668,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -47068,23 +37679,23 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x38, - [0x11] = 0x39, + [0x09] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, @@ -47094,100 +37705,100 @@ const struct chipinfo chipinfo_db[] = { { | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { - .reg_mask = 0x10018, - .enable_lpm5 = 0x10010, - .disable_lpm5 = 0x00018, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 15872, .offset = 0x0c200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01800, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, - .size = 4096, - .offset = 0x00000, + .size = 4064, + .offset = 0x00020, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "EEM", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, + .bits = 16, + .mapped = 1, + .size = 6, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -47199,24 +37810,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000043f, .clock_map = { {0}, {0}, {0}, - {"Comparator D", 0x2b}, - {"ADC10B", 0x37}, - {"RTC", 0x28}, + {"Comparator D", 0xa8}, + {"ADC10B", 0xd6}, + {"RTC", 0x8a}, {0}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"Timer0_B3", 0x16}, - {"Timer1_B3", 0x17}, - {"Timer2_B3", 0x18}, - {"Timer0_A3", 0x08}, - {"Timer1_A3", 0x09}, - {"Watchdog Timer", 0x01}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B3", 0x97}, + {"Timer1_B3", 0x98}, + {"Timer2_B3", 0x99}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -47254,27 +37865,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -47285,23 +37876,23 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x38, - [0x11] = 0x39, + [0x09] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, @@ -47311,100 +37902,100 @@ const struct chipinfo chipinfo_db[] = { { | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { - .reg_mask = 0x10018, - .enable_lpm5 = 0x10010, - .disable_lpm5 = 0x00018, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 15872, .offset = 0x0c200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01800, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, - .size = 4096, - .offset = 0x00000, + .size = 4064, + .offset = 0x00020, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "EEM", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, + .bits = 16, + .mapped = 1, + .size = 6, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -47416,24 +38007,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, {0}, - {"ADC10", 0x36}, - {"RTC", 0x28}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, {0}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -47471,27 +38062,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -47502,27 +38073,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -47538,102 +38108,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -47645,24 +38193,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, - {"ADC10", 0x36}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"Comparator B", 0xa8}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -47700,27 +38248,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -47731,27 +38259,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -47767,102 +38294,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -47874,24 +38379,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, - {"ADC10", 0x36}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"Comparator B", 0xa8}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -47929,27 +38434,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -47960,27 +38445,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -47996,102 +38480,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 24576, .offset = 0x0a000, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -48103,24 +38565,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, - {"ADC10", 0x36}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"Comparator B", 0xa8}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -48158,27 +38620,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -48189,27 +38631,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -48225,102 +38666,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -48332,24 +38751,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -48387,27 +38806,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -48418,27 +38817,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -48454,102 +38852,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 65536, .offset = 0x04400, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -48561,24 +38937,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -48616,27 +38992,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -48647,27 +39003,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -48683,102 +39038,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 65536, .offset = 0x04400, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -48790,24 +39123,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -48845,27 +39178,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -48876,27 +39189,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -48912,102 +39224,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 98304, .offset = 0x04400, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 3, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 6144, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -49019,24 +39309,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -49074,27 +39364,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -49105,27 +39375,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -49141,102 +39410,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 98304, .offset = 0x04400, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 3, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 6144, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -49248,24 +39495,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -49303,27 +39550,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -49334,27 +39561,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -49370,102 +39596,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x04400, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -49477,24 +39681,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -49532,27 +39736,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -49563,27 +39747,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -49599,102 +39782,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x04400, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -49706,24 +39867,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -49761,27 +39922,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -49792,27 +39933,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -49828,102 +39968,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 65536, .offset = 0x04400, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -49935,24 +40053,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -49990,27 +40108,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -50021,27 +40119,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -50057,102 +40154,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 98304, .offset = 0x04400, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 3, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 6144, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -50164,24 +40239,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -50219,27 +40294,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -50250,27 +40305,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -50286,102 +40340,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x04400, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -50393,24 +40425,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000041f, .clock_map = { {0}, - {"LCDB", 0x2c}, + {"LCDB", 0xb0}, {0}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -50448,27 +40480,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -50479,27 +40491,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -50515,102 +40526,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -50622,24 +40611,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000041f, .clock_map = { {0}, - {"LCDB", 0x2c}, + {"LCDB", 0xb0}, {0}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -50677,27 +40666,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -50708,27 +40677,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -50744,102 +40712,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -50851,24 +40797,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000041f, .clock_map = { {0}, - {"LCDB", 0x2c}, - {"DAC12", 0x32}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"LCDB", 0xb0}, + {"DAC12", 0xc0}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -50906,27 +40852,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -50937,27 +40863,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -50973,102 +40898,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -51080,24 +40983,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000041f, .clock_map = { {0}, - {"LCDB", 0x2c}, - {"DAC12", 0x32}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"LCDB", 0xb0}, + {"DAC12", 0xc0}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -51135,27 +41038,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -51166,27 +41049,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -51202,102 +41084,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -51309,24 +41169,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -51364,27 +41224,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -51395,27 +41235,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -51431,102 +41270,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -51538,24 +41355,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -51593,27 +41410,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -51624,27 +41421,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -51660,102 +41456,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -51767,24 +41541,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, - {"DAC12", 0x32}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"DAC12", 0xc0}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -51822,27 +41596,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -51853,27 +41607,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -51889,102 +41642,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -51996,24 +41727,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, - {"DAC12", 0x32}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"DAC12", 0xc0}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -52051,27 +41782,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -52082,27 +41793,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -52118,102 +41828,80 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -52225,24 +41913,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000041f, .clock_map = { {0}, - {"LCDB", 0x2c}, - {"DAC12", 0x32}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, + {"LCDB", 0xb0}, + {"DAC12", 0xc0}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, {0}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"USB", 0x03}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"USB", 0x40}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -52280,27 +41968,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -52311,27 +41979,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -52341,119 +42008,108 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 524288, - .offset = 0x08000, - .seg_size = 512, - .bank_size = 131072, - .banks = 4, - }, - { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 16384, - .offset = 0x02400, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram2", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 65536, .offset = 0xf0000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 524288, + .offset = 0x08000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "MidRom", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x06c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 16384, + .offset = 0x02400, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -52465,24 +42121,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000041f, .clock_map = { {0}, - {"LCDB", 0x2c}, - {"DAC12", 0x32}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, + {"LCDB", 0xb0}, + {"DAC12", 0xc0}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, {0}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"USB", 0x03}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"USB", 0x40}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -52520,27 +42176,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -52551,27 +42187,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -52581,119 +42216,108 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 393216, - .offset = 0x08000, - .seg_size = 512, - .bank_size = 131072, - .banks = 3, - }, - { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 16384, - .offset = 0x02400, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram2", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32768, .offset = 0xf8000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 393216, + .offset = 0x08000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 3, + }, + { + .name = "MidRom", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x06c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 16384, + .offset = 0x02400, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -52705,24 +42329,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000041f, .clock_map = { {0}, - {"LCDB", 0x2c}, + {"LCDB", 0xb0}, {0}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, {0}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -52760,27 +42384,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -52791,27 +42395,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -52827,113 +42430,102 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 524288, - .offset = 0x08000, - .seg_size = 512, - .bank_size = 131072, - .banks = 4, - }, - { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 16384, - .offset = 0x02400, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram2", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 65536, .offset = 0xf0000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 524288, + .offset = 0x08000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "MidRom", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x06c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 16384, + .offset = 0x02400, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -52945,24 +42537,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000041f, .clock_map = { {0}, - {"LCDB", 0x2c}, + {"LCDB", 0xb0}, {0}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, {0}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -53000,27 +42592,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -53031,27 +42603,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -53067,113 +42638,102 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 393216, - .offset = 0x08000, - .seg_size = 512, - .bank_size = 131072, - .banks = 3, - }, - { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 16384, - .offset = 0x02400, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram2", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32768, .offset = 0xf8000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 393216, + .offset = 0x08000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 3, + }, + { + .name = "MidRom", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x06c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 16384, + .offset = 0x02400, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -53185,24 +42745,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, - {"DAC12", 0x32}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, + {"DAC12", 0xc0}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, {0}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"USB", 0x03}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"USB", 0x40}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -53240,27 +42800,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -53271,27 +42811,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -53301,119 +42840,108 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 524288, - .offset = 0x08000, - .seg_size = 512, - .bank_size = 131072, - .banks = 4, - }, - { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 16384, - .offset = 0x02400, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram2", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 65536, .offset = 0xf0000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 524288, + .offset = 0x08000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "MidRom", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x06c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 16384, + .offset = 0x02400, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -53425,24 +42953,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, - {"DAC12", 0x32}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, + {"DAC12", 0xc0}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, {0}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"USB", 0x03}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"USB", 0x40}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -53480,27 +43008,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -53511,27 +43019,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -53541,119 +43048,108 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 393216, - .offset = 0x08000, - .seg_size = 512, - .bank_size = 131072, - .banks = 3, - }, - { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 16384, - .offset = 0x02400, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram2", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32768, .offset = 0xf8000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 393216, + .offset = 0x08000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 3, + }, + { + .name = "MidRom", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x06c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 16384, + .offset = 0x02400, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -53665,24 +43161,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, - {"DAC12", 0x32}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, + {"DAC12", 0xc0}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, {0}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -53720,27 +43216,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -53751,27 +43227,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -53781,119 +43256,108 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 524288, - .offset = 0x08000, - .seg_size = 512, - .bank_size = 131072, - .banks = 4, - }, - { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 16384, - .offset = 0x02400, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram2", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 65536, .offset = 0xf0000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 524288, + .offset = 0x08000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "MidRom", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x06c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 16384, + .offset = 0x02400, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -53905,24 +43369,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, - {"DAC12", 0x32}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, + {"DAC12", 0xc0}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, {0}, {0}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -53960,27 +43424,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -53991,27 +43435,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2_word, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -54021,119 +43464,108 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 393216, - .offset = 0x08000, - .seg_size = 512, - .bank_size = 131072, - .banks = 3, - }, - { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "usbram", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 16384, - .offset = 0x02400, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram2", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32768, .offset = 0xf8000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 393216, + .offset = 0x08000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 3, + }, + { + .name = "MidRom", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x06c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 16384, + .offset = 0x02400, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -54145,24 +43577,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x00002407, .clock_map = { {0}, {0}, - {"AES128", 0x04}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"LCDB", 0x2c}, + {"AES128", 0x60}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"LCDB", 0xb0}, {0}, {0}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -54200,27 +43632,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -54231,27 +43643,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -54260,108 +43671,86 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 3968, .offset = 0x01c80, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "system", + .name = "Ram2", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 128, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -54373,24 +43762,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x00002407, .clock_map = { {0}, {0}, - {"AES128", 0x04}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"LCDB", 0x2c}, + {"AES128", 0x60}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"LCDB", 0xb0}, {0}, {0}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -54428,27 +43817,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -54459,27 +43828,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -54488,108 +43856,86 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1920, .offset = 0x01c80, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "system", + .name = "Ram2", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 128, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -54601,24 +43947,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x00002407, .clock_map = { {0}, {0}, - {"AES128", 0x04}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, - {"LCDB", 0x2c}, + {"AES128", 0x60}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {"LCDB", 0xb0}, {0}, {0}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -54656,27 +44002,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -54687,27 +44013,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -54716,108 +44041,86 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1920, .offset = 0x01c80, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "system", + .name = "Ram2", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 128, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -54829,24 +44132,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x00002407, .clock_map = { {0}, {0}, - {"AES128", 0x04}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"AES128", 0x60}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, {0}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -54884,27 +44187,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -54915,27 +44198,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -54944,108 +44226,86 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x08000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 3968, .offset = 0x01c80, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "system", + .name = "Ram2", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 128, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -55057,24 +44317,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x00002407, .clock_map = { {0}, {0}, - {"AES128", 0x04}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"AES128", 0x60}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, {0}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -55112,27 +44372,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -55143,27 +44383,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -55172,108 +44411,86 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1920, .offset = 0x01c80, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "system", + .name = "Ram2", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 128, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -55285,24 +44502,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x00002407, .clock_map = { {0}, {0}, - {"AES128", 0x04}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"AES128", 0x60}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, {0}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -55340,27 +44557,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -55371,27 +44568,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -55400,108 +44596,86 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1920, .offset = 0x01c80, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "system", + .name = "Ram2", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 128, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -55513,24 +44687,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x00002407, .clock_map = { {0}, {0}, - {"AES128", 0x04}, - {"Comparator B", 0x2a}, + {"AES128", 0x60}, + {"Comparator B", 0xa8}, {0}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, {0}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -55568,27 +44742,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -55599,27 +44753,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -55628,108 +44781,86 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x0c000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1920, .offset = 0x01c80, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "system", + .name = "Ram2", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 128, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -55741,24 +44872,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x00002407, .clock_map = { {0}, {0}, - {"AES128", 0x04}, - {"Comparator B", 0x2a}, + {"AES128", 0x60}, + {"Comparator B", 0xa8}, {0}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, {0}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -55796,27 +44927,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -55827,27 +44938,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -55856,108 +44966,86 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1920, .offset = 0x01c80, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "system", + .name = "Ram2", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 128, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -55969,24 +45057,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, + {"Comparator B", 0xa8}, {0}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -56024,27 +45112,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -56055,27 +45123,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -56091,91 +45158,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 65536, .offset = 0x04400, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -56187,24 +45232,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, + {"Comparator B", 0xa8}, {0}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -56242,27 +45287,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -56273,27 +45298,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -56309,91 +45333,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 98304, .offset = 0x04400, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 3, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -56405,24 +45407,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, + {"Comparator B", 0xa8}, {0}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -56460,27 +45462,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -56491,27 +45473,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -56527,91 +45508,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x04400, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -56623,24 +45582,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, + {"Comparator B", 0xa8}, {0}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -56678,27 +45637,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -56709,27 +45648,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -56745,91 +45683,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 65536, .offset = 0x04400, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -56841,24 +45757,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, + {"Comparator B", 0xa8}, {0}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -56896,27 +45812,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -56927,27 +45823,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -56963,91 +45858,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 98304, .offset = 0x04400, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 3, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -57059,24 +45932,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, + {"Comparator B", 0xa8}, {0}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -57114,27 +45987,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -57145,27 +45998,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -57181,91 +46033,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x04400, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -57277,24 +46107,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -57332,27 +46162,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -57363,27 +46173,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -57399,91 +46208,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 65536, .offset = 0x04400, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -57495,24 +46282,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -57550,27 +46337,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -57581,27 +46348,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -57617,91 +46383,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 98304, .offset = 0x04400, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 3, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -57713,24 +46457,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -57768,27 +46512,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -57799,27 +46523,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -57835,91 +46558,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x04400, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -57931,24 +46632,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -57986,27 +46687,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -58017,27 +46698,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -58053,91 +46733,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 65536, .offset = 0x04400, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -58149,24 +46807,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -58204,27 +46862,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -58235,27 +46873,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -58271,91 +46908,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 98304, .offset = 0x04400, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 3, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -58367,24 +46982,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -58422,27 +47037,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -58453,27 +47048,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -58489,308 +47083,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x04400, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "peripheral16bit", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 16, - .mapped = 1, - .size = 4096, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - {0} - }, - }, - - { - .name = "MSP430FR5949", - .bits = 20, - .psa = CHIPINFO_PSA_REGULAR, - .clock_control = 0x02, - .mclk_control = 0xbdff, - .clock_map = { - {"Timer1_A2", 0x06}, - {0}, - {"AES128", 0x04}, - {"Comparator D", 0x2b}, - {"ADC12B", 0x38}, - {"RTC", 0x28}, - {0}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"Timer0_B7", 0x1c}, - {"Timer0_A3", 0x08}, - {"Timer1_A3", 0x09}, - {"Timer2_A3", 0x0a}, - {"Timer0_A2", 0x05}, - {"Watchdog Timer", 0x01}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - }, - .id = { - .ver_id = 0x8161, - .ver_sub_id = 0x0000, - .revision = 0x12, - .fab = 0x00, - .self = 0x0000, - .config = 0x00, - .fuses = 0x00, - .activation_key = 0x00000000, - }, - .id_mask = { - .ver_id = 0xffff, - .ver_sub_id = 0xffff, - .revision = 0xff, - .fab = 0x00, - .self = 0x0000, - .config = 0x00, - .fuses = 0x00, - .activation_key = 0x00000000, - }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, - .voltage = { - .vcc_min = 1800, - .vcc_max = 3600, - .vcc_flash_min = 1800, - .vcc_secure_min = 2500, - .vpp_secure_min = 6000, - .vpp_secure_max = 7000, - .has_test_vpp = 1, - }, - .v3_functions = { - [0x09] = 0x38, - [0x0a] = 0x0a, - [0x11] = 0x39, - [0x12] = 0x3a, - [0x13] = 0x3b, - [0x14] = 0x3c, - [0x15] = 0x3c, - [0x16] = 0x3d, - [0x17] = 0x3e, - [0x18] = 0x3e, - [0x19] = 0x3f, - [0x1b] = 0x40, - [0x1c] = 0x41, - [0x1d] = 0x42, - [0x1e] = 0x43, - [0x1f] = 0x44, - [0x25] = 0x36, - }, - .v3_erase = &erase_xv2_fram, - .v3_write = &write_xv2_fram, - .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, - .features = 0 - | CHIPINFO_FEATURE_LCFE - | CHIPINFO_FEATURE_QUICK_MEM_READ - | CHIPINFO_FEATURE_FRAM, - .power = { - .reg_mask = 0x10018, - .enable_lpm5 = 0x10018, - .disable_lpm5 = 0x10000, - .reg_mask_3v = 0x0c020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, - }, - .memory = { - { - .name = "main", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 64512, - .offset = 0x04400, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "information", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "bootcode", + .name = "BootCode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, }, { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -58798,28 +47153,28 @@ const struct chipinfo chipinfo_db[] = { { }, { - .name = "MSP430FR5949", + .name = "Legacy", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, - .clock_control = 0x02, - .mclk_control = 0xbdff, + .clock_control = 0x00, + .mclk_control = 0x00000000, .clock_map = { - {"Timer1_A2", 0x06}, {0}, - {"AES128", 0x04}, - {"Comparator D", 0x2b}, - {"ADC12B", 0x38}, - {"RTC", 0x28}, {0}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"Timer0_B7", 0x1c}, - {"Timer0_A3", 0x08}, - {"Timer1_A3", 0x09}, - {"Timer2_A3", 0x0a}, - {"Timer0_A2", 0x05}, - {"Watchdog Timer", 0x01}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, {0}, {0}, {0}, @@ -58838,9 +47193,9 @@ const struct chipinfo chipinfo_db[] = { { {0}, }, .id = { - .ver_id = 0x8161, + .ver_id = 0x8153, .ver_sub_id = 0x0000, - .revision = 0x20, + .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, @@ -58857,27 +47212,108 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 2700, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 0, }, + .v3_functions = { + }, + .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_NO_BSL, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "None", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 0, + .offset = 0x00000, + .seg_size = 0, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR5847", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x0000043f, + .clock_map = { + {0}, + {0}, + {0}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {0}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer3_A2", 0x8c}, + {"Timer2_A2", 0x8b}, + {"Timer1_A3", 0x8f}, + {"Timer0_A3", 0x8e}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8153, + .ver_sub_id = 0x0000, + .revision = 0x21, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -58888,23 +47324,23 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x38, - [0x0a] = 0x49, - [0x11] = 0x39, + [0x09] = 0x39, + [0x0a] = 0x4a, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x4f, - [0x1c] = 0x41, + [0x1a] = 0x40, + [0x1c] = 0x50, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, + [0x20] = 0x45, + [0x26] = 0x37, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, @@ -58917,97 +47353,3178 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x10018, .enable_lpm5 = 0x10018, .disable_lpm5 = 0x10000, - .reg_mask_3v = 0x0c020, + .reg_mask_3v = 0x0c0a0, .enable_lpm5_3v = 0x0c020, - .disable_lpm5_3v = 0x04020, + .disable_lpm5_3v = 0x040a0, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, - .size = 64512, - .offset = 0x04400, + .size = 32768, + .offset = 0x08000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, - .size = 512, - .offset = 0x01800, + .size = 1024, + .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "boot", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "bootcode", + .name = "BootCode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "system", + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4064, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 6, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "Legacy", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x00, + .mclk_control = 0x00000000, + .clock_map = { + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8154, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 2700, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 0, + }, + .v3_functions = { + }, + .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_NO_BSL, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "None", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 0, + .offset = 0x00000, + .seg_size = 0, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR5848", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x0000043f, + .clock_map = { + {0}, + {0}, + {0}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {0}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer3_A2", 0x8c}, + {"Timer2_A2", 0x8b}, + {"Timer1_A3", 0x8f}, + {"Timer0_A3", 0x8e}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8154, + .ver_sub_id = 0x0000, + .revision = 0x21, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 48128, + .offset = 0x04400, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, - .size = 4096, - .offset = 0x00000, + .size = 4064, + .offset = 0x00020, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "EEM", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, + .bits = 16, + .mapped = 1, + .size = 6, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "Legacy", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x00, + .mclk_control = 0x00000000, + .clock_map = { + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8155, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 2700, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 0, + }, + .v3_functions = { + }, + .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_NO_BSL, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "None", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 0, + .offset = 0x00000, + .seg_size = 0, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR5849", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x0000043f, + .clock_map = { + {0}, + {0}, + {0}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {0}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer3_A2", 0x8c}, + {"Timer2_A2", 0x8b}, + {"Timer1_A3", 0x8f}, + {"Timer0_A3", 0x8e}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8155, + .ver_sub_id = 0x0000, + .revision = 0x21, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 64512, + .offset = 0x04400, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4064, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 6, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "Legacy", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x00, + .mclk_control = 0x00000000, + .clock_map = { + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8157, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 2700, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 0, + }, + .v3_functions = { + }, + .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_NO_BSL, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "None", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 0, + .offset = 0x00000, + .seg_size = 0, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR5857", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x0000043f, + .clock_map = { + {0}, + {0}, + {0}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {0}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer3_A2", 0x8c}, + {"Timer2_A2", 0x8b}, + {"Timer1_A3", 0x8f}, + {"Timer0_A3", 0x8e}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8157, + .ver_sub_id = 0x0000, + .revision = 0x21, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 32768, + .offset = 0x08000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4064, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 6, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "Legacy", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x00, + .mclk_control = 0x00000000, + .clock_map = { + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8158, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 2700, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 0, + }, + .v3_functions = { + }, + .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_NO_BSL, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "None", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 0, + .offset = 0x00000, + .seg_size = 0, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR5858", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x0000043f, + .clock_map = { + {0}, + {0}, + {0}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {0}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer3_A2", 0x8c}, + {"Timer2_A2", 0x8b}, + {"Timer1_A3", 0x8f}, + {"Timer0_A3", 0x8e}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8158, + .ver_sub_id = 0x0000, + .revision = 0x21, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 48128, + .offset = 0x04400, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4064, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 6, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "Legacy", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x00, + .mclk_control = 0x00000000, + .clock_map = { + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8159, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 2700, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 0, + }, + .v3_functions = { + }, + .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_NO_BSL, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "None", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 0, + .offset = 0x00000, + .seg_size = 0, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR5859", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x0000043f, + .clock_map = { + {0}, + {0}, + {0}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {0}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer3_A2", 0x8c}, + {"Timer2_A2", 0x8b}, + {"Timer1_A3", 0x8f}, + {"Timer0_A3", 0x8e}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8159, + .ver_sub_id = 0x0000, + .revision = 0x21, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 64512, + .offset = 0x04400, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4064, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 6, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "Legacy", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x00, + .mclk_control = 0x00000000, + .clock_map = { + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x815b, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 2700, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 0, + }, + .v3_functions = { + }, + .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_NO_BSL, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "None", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 0, + .offset = 0x00000, + .seg_size = 0, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR5867", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x0000043f, + .clock_map = { + {0}, + {0}, + {0}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {0}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer3_A2", 0x8c}, + {"Timer2_A2", 0x8b}, + {"Timer1_A3", 0x8f}, + {"Timer0_A3", 0x8e}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x815b, + .ver_sub_id = 0x0000, + .revision = 0x21, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 32768, + .offset = 0x08000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4064, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 6, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "Legacy", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x00, + .mclk_control = 0x00000000, + .clock_map = { + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x815c, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 2700, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 0, + }, + .v3_functions = { + }, + .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_NO_BSL, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "None", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 0, + .offset = 0x00000, + .seg_size = 0, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR5868", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x0000043f, + .clock_map = { + {0}, + {0}, + {0}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {0}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer3_A2", 0x8c}, + {"Timer2_A2", 0x8b}, + {"Timer1_A3", 0x8f}, + {"Timer0_A3", 0x8e}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x815c, + .ver_sub_id = 0x0000, + .revision = 0x21, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 48128, + .offset = 0x04400, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4064, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 6, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "Legacy", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x00, + .mclk_control = 0x00000000, + .clock_map = { + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x815d, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 2700, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 0, + }, + .v3_functions = { + }, + .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_NO_BSL, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "None", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 0, + .offset = 0x00000, + .seg_size = 0, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR5869", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x0000043f, + .clock_map = { + {0}, + {0}, + {0}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {0}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer3_A2", 0x8c}, + {"Timer2_A2", 0x8b}, + {"Timer1_A3", 0x8f}, + {"Timer0_A3", 0x8e}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x815d, + .ver_sub_id = 0x0000, + .revision = 0x21, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 64512, + .offset = 0x04400, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4064, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 6, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "Legacy", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x00, + .mclk_control = 0x00000000, + .clock_map = { + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x815f, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 2700, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 0, + }, + .v3_functions = { + }, + .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_NO_BSL, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "None", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 0, + .offset = 0x00000, + .seg_size = 0, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR5947", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x0000043f, + .clock_map = { + {0}, + {0}, + {0}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {0}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer3_A2", 0x8c}, + {"Timer2_A2", 0x8b}, + {"Timer1_A3", 0x8f}, + {"Timer0_A3", 0x8e}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x815f, + .ver_sub_id = 0x0000, + .revision = 0x21, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 32768, + .offset = 0x08000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4064, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 6, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "Legacy", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x00, + .mclk_control = 0x00000000, + .clock_map = { + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8160, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 2700, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 0, + }, + .v3_functions = { + }, + .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_NO_BSL, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "None", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 0, + .offset = 0x00000, + .seg_size = 0, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR5948", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x0000043f, + .clock_map = { + {0}, + {0}, + {0}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {0}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer3_A2", 0x8c}, + {"Timer2_A2", 0x8b}, + {"Timer1_A3", 0x8f}, + {"Timer0_A3", 0x8e}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8160, + .ver_sub_id = 0x0000, + .revision = 0x21, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 48128, + .offset = 0x04400, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4064, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 6, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "Legacy", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x00, + .mclk_control = 0x00000000, + .clock_map = { + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8161, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 2700, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 0, + }, + .v3_functions = { + }, + .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_NO_BSL, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "None", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 0, + .offset = 0x00000, + .seg_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -59019,24 +50536,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0xbdff, + .mclk_control = 0x0000043f, .clock_map = { - {"Timer1_A2", 0x06}, {0}, - {"AES128", 0x04}, - {"Comparator D", 0x2b}, - {"ADC12B", 0x38}, - {"RTC", 0x28}, {0}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"Timer0_B7", 0x1c}, - {"Timer0_A3", 0x08}, - {"Timer1_A3", 0x09}, - {"Timer2_A3", 0x0a}, - {"Timer0_A2", 0x05}, - {"Watchdog Timer", 0x01}, + {0}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {0}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer3_A2", 0x8c}, + {"Timer2_A2", 0x8b}, + {"Timer1_A3", 0x8f}, + {"Timer0_A3", 0x8e}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -59074,27 +50591,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -59105,23 +50602,23 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x38, - [0x0a] = 0x49, - [0x11] = 0x39, + [0x09] = 0x39, + [0x0a] = 0x4a, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x4f, - [0x1c] = 0x41, + [0x1a] = 0x40, + [0x1c] = 0x50, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, + [0x20] = 0x45, + [0x26] = 0x37, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, @@ -59134,97 +50631,97 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x10018, .enable_lpm5 = 0x10018, .disable_lpm5 = 0x10000, - .reg_mask_3v = 0x0c020, + .reg_mask_3v = 0x0c0a0, .enable_lpm5_3v = 0x0c020, - .disable_lpm5_3v = 0x04020, + .disable_lpm5_3v = 0x040a0, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 64512, .offset = 0x04400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, - .size = 4096, - .offset = 0x00000, + .size = 4064, + .offset = 0x00020, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "EEM", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, + .bits = 16, + .mapped = 1, + .size = 6, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -59232,28 +50729,624 @@ const struct chipinfo chipinfo_db[] = { { }, { - .name = "MSP430FR5959", + .name = "Legacy", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x00, + .mclk_control = 0x00000000, + .clock_map = { + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8163, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 2700, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 0, + }, + .v3_functions = { + }, + .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_NO_BSL, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "None", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 0, + .offset = 0x00000, + .seg_size = 0, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR5957", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0xbdff, + .mclk_control = 0x0000043f, .clock_map = { - {"Timer1_A2", 0x06}, {0}, - {"AES128", 0x04}, - {"Comparator D", 0x2b}, - {"ADC12B", 0x38}, - {"RTC", 0x28}, {0}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"Timer0_B7", 0x1c}, - {"Timer0_A3", 0x08}, - {"Timer1_A3", 0x09}, - {"Timer2_A3", 0x0a}, - {"Timer0_A2", 0x05}, - {"Watchdog Timer", 0x01}, + {0}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {0}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer3_A2", 0x8c}, + {"Timer2_A2", 0x8b}, + {"Timer1_A3", 0x8f}, + {"Timer0_A3", 0x8e}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8163, + .ver_sub_id = 0x0000, + .revision = 0x21, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 32768, + .offset = 0x08000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4064, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 6, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "Legacy", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x00, + .mclk_control = 0x00000000, + .clock_map = { + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8164, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 2700, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 0, + }, + .v3_functions = { + }, + .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_NO_BSL, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "None", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 0, + .offset = 0x00000, + .seg_size = 0, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR5958", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x0000043f, + .clock_map = { + {0}, + {0}, + {0}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {0}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer3_A2", 0x8c}, + {"Timer2_A2", 0x8b}, + {"Timer1_A3", 0x8f}, + {"Timer0_A3", 0x8e}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8164, + .ver_sub_id = 0x0000, + .revision = 0x21, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 48128, + .offset = 0x04400, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4064, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 6, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "Legacy", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x00, + .mclk_control = 0x00000000, + .clock_map = { + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, {0}, {0}, {0}, @@ -59274,7 +51367,7 @@ const struct chipinfo chipinfo_db[] = { { .id = { .ver_id = 0x8165, .ver_sub_id = 0x0000, - .revision = 0x30, + .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, @@ -59291,157 +51384,41 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, - .vcc_flash_min = 1800, + .vcc_flash_min = 2700, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, - .has_test_vpp = 1, + .has_test_vpp = 0, }, .v3_functions = { - [0x09] = 0x38, - [0x0a] = 0x0a, - [0x11] = 0x39, - [0x12] = 0x3a, - [0x13] = 0x3b, - [0x14] = 0x3c, - [0x15] = 0x3c, - [0x16] = 0x3d, - [0x17] = 0x3e, - [0x18] = 0x3e, - [0x19] = 0x3f, - [0x1b] = 0x40, - [0x1c] = 0x41, - [0x1d] = 0x42, - [0x1e] = 0x43, - [0x1f] = 0x44, - [0x25] = 0x36, }, - .v3_erase = &erase_xv2_fram, - .v3_write = &write_xv2_fram, - .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ - | CHIPINFO_FEATURE_FRAM, + | CHIPINFO_FEATURE_NO_BSL, .power = { - .reg_mask = 0x10018, - .enable_lpm5 = 0x10018, - .disable_lpm5 = 0x10000, - .reg_mask_3v = 0x0c020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", - .type = CHIPINFO_MEMTYPE_RAM, + .name = "None", + .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, - .size = 64512, - .offset = 0x04400, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "information", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "peripheral16bit", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 16, - .mapped = 1, - .size = 4096, + .size = 0, .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .seg_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -59453,24 +51430,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0xbdff, + .mclk_control = 0x0000043f, .clock_map = { - {"Timer1_A2", 0x06}, {0}, - {"AES128", 0x04}, - {"Comparator D", 0x2b}, - {"ADC12B", 0x38}, - {"RTC", 0x28}, {0}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"Timer0_B7", 0x1c}, - {"Timer0_A3", 0x08}, - {"Timer1_A3", 0x09}, - {"Timer2_A3", 0x0a}, - {"Timer0_A2", 0x05}, - {"Watchdog Timer", 0x01}, + {0}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {0}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer3_A2", 0x8c}, + {"Timer2_A2", 0x8b}, + {"Timer1_A3", 0x8f}, + {"Timer0_A3", 0x8e}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -59491,7 +51468,7 @@ const struct chipinfo chipinfo_db[] = { { .id = { .ver_id = 0x8165, .ver_sub_id = 0x0000, - .revision = 0x31, + .revision = 0x21, .fab = 0x00, .self = 0x0000, .config = 0x00, @@ -59508,27 +51485,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -59539,23 +51496,23 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x38, - [0x0a] = 0x49, - [0x11] = 0x39, + [0x09] = 0x39, + [0x0a] = 0x4a, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x4f, - [0x1c] = 0x41, + [0x1a] = 0x40, + [0x1c] = 0x50, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, + [0x20] = 0x45, + [0x26] = 0x37, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, @@ -59568,97 +51525,97 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x10018, .enable_lpm5 = 0x10018, .disable_lpm5 = 0x10000, - .reg_mask_3v = 0x0c020, + .reg_mask_3v = 0x0c0a0, .enable_lpm5_3v = 0x0c020, - .disable_lpm5_3v = 0x04020, + .disable_lpm5_3v = 0x040a0, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 64512, .offset = 0x04400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, - .size = 4096, - .offset = 0x00000, + .size = 4064, + .offset = 0x00020, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "EEM", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, + .bits = 16, + .mapped = 1, + .size = 6, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -59666,28 +51623,28 @@ const struct chipinfo chipinfo_db[] = { { }, { - .name = "MSP430FR5959", + .name = "Legacy", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, - .clock_control = 0x02, - .mclk_control = 0xbdff, + .clock_control = 0x00, + .mclk_control = 0x00000000, .clock_map = { - {"Timer1_A2", 0x06}, {0}, - {"AES128", 0x04}, - {"Comparator D", 0x2b}, - {"ADC12B", 0x38}, - {"RTC", 0x28}, {0}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"Timer0_B7", 0x1c}, - {"Timer0_A3", 0x08}, - {"Timer1_A3", 0x09}, - {"Timer2_A3", 0x0a}, - {"Timer0_A2", 0x05}, - {"Watchdog Timer", 0x01}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, {0}, {0}, {0}, @@ -59706,9 +51663,9 @@ const struct chipinfo chipinfo_db[] = { { {0}, }, .id = { - .ver_id = 0x8165, + .ver_id = 0x8167, .ver_sub_id = 0x0000, - .revision = 0x40, + .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, @@ -59725,27 +51682,108 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 2700, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 0, }, + .v3_functions = { + }, + .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_NO_BSL, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "None", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 0, + .offset = 0x00000, + .seg_size = 0, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR5967", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x0000043f, + .clock_map = { + {0}, + {0}, + {0}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {0}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer3_A2", 0x8c}, + {"Timer2_A2", 0x8b}, + {"Timer1_A3", 0x8f}, + {"Timer0_A3", 0x8e}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8167, + .ver_sub_id = 0x0000, + .revision = 0x21, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -59756,23 +51794,23 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x38, - [0x0a] = 0x49, - [0x11] = 0x39, + [0x09] = 0x39, + [0x0a] = 0x4a, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x4f, - [0x1c] = 0x41, + [0x1a] = 0x40, + [0x1c] = 0x50, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, + [0x20] = 0x45, + [0x26] = 0x37, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, @@ -59785,97 +51823,97 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x10018, .enable_lpm5 = 0x10018, .disable_lpm5 = 0x10000, - .reg_mask_3v = 0x0c020, + .reg_mask_3v = 0x0c0a0, .enable_lpm5_3v = 0x0c020, - .disable_lpm5_3v = 0x04020, + .disable_lpm5_3v = 0x040a0, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, - .size = 64512, - .offset = 0x04400, + .size = 32768, + .offset = 0x08000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, - .size = 512, - .offset = 0x01800, + .size = 1024, + .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "boot", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "bootcode", + .name = "BootCode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "system", + .name = "Info", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, - .size = 2048, - .offset = 0x01c00, + .size = 512, + .offset = 0x01800, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, - .size = 4096, - .offset = 0x00000, + .size = 4064, + .offset = 0x00020, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "EEM", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, + .bits = 16, + .mapped = 1, + .size = 6, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -59883,28 +51921,326 @@ const struct chipinfo chipinfo_db[] = { { }, { - .name = "MSP430FR5969", + .name = "Legacy", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x00, + .mclk_control = 0x00000000, + .clock_map = { + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8168, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 2700, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 0, + }, + .v3_functions = { + }, + .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_NO_BSL, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "None", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 0, + .offset = 0x00000, + .seg_size = 0, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR5968", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0xbdff, + .mclk_control = 0x0000043f, .clock_map = { - {"Timer1_A2", 0x06}, {0}, - {"AES128", 0x04}, - {"Comparator D", 0x2b}, - {"ADC12B", 0x38}, - {"RTC", 0x28}, {0}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"Timer0_B7", 0x1c}, - {"Timer0_A3", 0x08}, - {"Timer1_A3", 0x09}, - {"Timer2_A3", 0x0a}, - {"Timer0_A2", 0x05}, - {"Watchdog Timer", 0x01}, + {0}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {0}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer3_A2", 0x8c}, + {"Timer2_A2", 0x8b}, + {"Timer1_A3", 0x8f}, + {"Timer0_A3", 0x8e}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8168, + .ver_sub_id = 0x0000, + .revision = 0x21, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 48128, + .offset = 0x04400, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4064, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 6, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "Legacy", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x00, + .mclk_control = 0x00000000, + .clock_map = { + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, {0}, {0}, {0}, @@ -59925,7 +52261,7 @@ const struct chipinfo chipinfo_db[] = { { .id = { .ver_id = 0x8169, .ver_sub_id = 0x0000, - .revision = 0x30, + .revision = 0x00, .fab = 0x00, .self = 0x0000, .config = 0x00, @@ -59942,157 +52278,41 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, - .vcc_flash_min = 1800, + .vcc_flash_min = 2700, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, - .has_test_vpp = 1, + .has_test_vpp = 0, }, .v3_functions = { - [0x09] = 0x38, - [0x0a] = 0x0a, - [0x11] = 0x39, - [0x12] = 0x3a, - [0x13] = 0x3b, - [0x14] = 0x3c, - [0x15] = 0x3c, - [0x16] = 0x3d, - [0x17] = 0x3e, - [0x18] = 0x3e, - [0x19] = 0x3f, - [0x1b] = 0x40, - [0x1c] = 0x41, - [0x1d] = 0x42, - [0x1e] = 0x43, - [0x1f] = 0x44, - [0x25] = 0x36, }, - .v3_erase = &erase_xv2_fram, - .v3_write = &write_xv2_fram, - .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ - | CHIPINFO_FEATURE_FRAM, + | CHIPINFO_FEATURE_NO_BSL, .power = { - .reg_mask = 0x10018, - .enable_lpm5 = 0x10018, - .disable_lpm5 = 0x10000, - .reg_mask_3v = 0x0c020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", - .type = CHIPINFO_MEMTYPE_RAM, + .name = "None", + .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, - .size = 64512, - .offset = 0x04400, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "information", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "peripheral16bit", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 16, - .mapped = 1, - .size = 4096, + .size = 0, .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .seg_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -60104,24 +52324,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0xbdff, + .mclk_control = 0x0000043f, .clock_map = { - {"Timer1_A2", 0x06}, {0}, - {"AES128", 0x04}, - {"Comparator D", 0x2b}, - {"ADC12B", 0x38}, - {"RTC", 0x28}, {0}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"Timer0_B7", 0x1c}, - {"Timer0_A3", 0x08}, - {"Timer1_A3", 0x09}, - {"Timer2_A3", 0x0a}, - {"Timer0_A2", 0x05}, - {"Watchdog Timer", 0x01}, + {0}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {0}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer3_A2", 0x8c}, + {"Timer2_A2", 0x8b}, + {"Timer1_A3", 0x8f}, + {"Timer0_A3", 0x8e}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -60142,7 +52362,7 @@ const struct chipinfo chipinfo_db[] = { { .id = { .ver_id = 0x8169, .ver_sub_id = 0x0000, - .revision = 0x31, + .revision = 0x21, .fab = 0x00, .self = 0x0000, .config = 0x00, @@ -60159,27 +52379,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -60190,23 +52390,23 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x38, - [0x0a] = 0x49, - [0x11] = 0x39, + [0x09] = 0x39, + [0x0a] = 0x4a, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x4f, - [0x1c] = 0x41, + [0x1a] = 0x40, + [0x1c] = 0x50, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, + [0x20] = 0x45, + [0x26] = 0x37, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, @@ -60219,344 +52419,126 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x10018, .enable_lpm5 = 0x10018, .disable_lpm5 = 0x10000, - .reg_mask_3v = 0x0c020, + .reg_mask_3v = 0x0c0a0, .enable_lpm5_3v = 0x0c020, - .disable_lpm5_3v = 0x04020, + .disable_lpm5_3v = 0x040a0, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 64512, .offset = 0x04400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 16, - .mapped = 1, - .size = 4096, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - {0} - }, - }, - - { - .name = "MSP430FR5969", - .bits = 20, - .psa = CHIPINFO_PSA_REGULAR, - .clock_control = 0x02, - .mclk_control = 0xbdff, - .clock_map = { - {"Timer1_A2", 0x06}, - {0}, - {"AES128", 0x04}, - {"Comparator D", 0x2b}, - {"ADC12B", 0x38}, - {"RTC", 0x28}, - {0}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"Timer0_B7", 0x1c}, - {"Timer0_A3", 0x08}, - {"Timer1_A3", 0x09}, - {"Timer2_A3", 0x0a}, - {"Timer0_A2", 0x05}, - {"Watchdog Timer", 0x01}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - }, - .id = { - .ver_id = 0x8169, - .ver_sub_id = 0x0000, - .revision = 0x40, - .fab = 0x00, - .self = 0x0000, - .config = 0x00, - .fuses = 0x00, - .activation_key = 0x00000000, - }, - .id_mask = { - .ver_id = 0xffff, - .ver_sub_id = 0xffff, - .revision = 0xff, - .fab = 0x00, - .self = 0x0000, - .config = 0x00, - .fuses = 0x00, - .activation_key = 0x00000000, - }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, - .voltage = { - .vcc_min = 1800, - .vcc_max = 3600, - .vcc_flash_min = 1800, - .vcc_secure_min = 2500, - .vpp_secure_min = 6000, - .vpp_secure_max = 7000, - .has_test_vpp = 1, - }, - .v3_functions = { - [0x09] = 0x38, - [0x0a] = 0x49, - [0x11] = 0x39, - [0x12] = 0x3a, - [0x13] = 0x3b, - [0x14] = 0x3c, - [0x15] = 0x3c, - [0x16] = 0x3d, - [0x17] = 0x3e, - [0x18] = 0x3e, - [0x19] = 0x3f, - [0x1b] = 0x4f, - [0x1c] = 0x41, - [0x1d] = 0x42, - [0x1e] = 0x43, - [0x1f] = 0x44, - [0x25] = 0x36, - }, - .v3_erase = &erase_xv2_fram, - .v3_write = &write_xv2_fram, - .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, - .features = 0 - | CHIPINFO_FEATURE_LCFE - | CHIPINFO_FEATURE_QUICK_MEM_READ - | CHIPINFO_FEATURE_FRAM, - .power = { - .reg_mask = 0x10018, - .enable_lpm5 = 0x10018, - .disable_lpm5 = 0x10000, - .reg_mask_3v = 0x0c020, - .enable_lpm5_3v = 0x0c020, - .disable_lpm5_3v = 0x04020, - }, - .memory = { - { - .name = "main", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 64512, - .offset = 0x04400, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "information", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "bootcode", + .name = "BootCode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "system", + .name = "Info", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, - .size = 2048, - .offset = 0x01c00, + .size = 512, + .offset = 0x01800, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, - .size = 4096, - .offset = 0x00000, + .size = 4064, + .offset = 0x00020, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "EEM", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, + .bits = 16, + .mapped = 1, + .size = 6, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} }, }, - { .name = "MSP430F6734", .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"SD24B", 0x35}, - {"ADC10", 0x36}, - {"RTC", 0x28}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, {0}, {0}, - {"Timer0_A3", 0x08}, - {"Timer1_A2", 0x06}, - {"Timer2_A2", 0x07}, - {"Timer3_A2", 0x0b}, - {"Watchdog Timer", 0x01}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -60594,27 +52576,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -60625,27 +52587,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -60655,97 +52616,75 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 98304, .offset = 0x04000, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 3, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -60757,24 +52696,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"SD24B", 0x35}, - {"ADC10", 0x36}, - {"RTC", 0x28}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, {0}, {0}, - {"Timer0_A3", 0x08}, - {"Timer1_A2", 0x06}, - {"Timer2_A2", 0x07}, - {"Timer3_A2", 0x0b}, - {"Watchdog Timer", 0x01}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -60812,27 +52751,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -60843,27 +52762,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -60873,97 +52791,75 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x04000, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -60975,24 +52871,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"SD24B", 0x35}, - {"ADC10", 0x36}, - {"RTC", 0x28}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, {0}, {0}, - {"Timer0_A3", 0x08}, - {"Timer1_A2", 0x06}, - {"Timer2_A2", 0x07}, - {"Timer3_A2", 0x0b}, - {"Watchdog Timer", 0x01}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -61030,27 +52926,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -61061,27 +52937,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -61091,97 +52966,75 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x04000, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -61193,24 +53046,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"SD24B", 0x35}, - {"ADC10", 0x36}, - {"RTC", 0x28}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, {0}, {0}, - {"Timer0_A3", 0x08}, - {"Timer1_A2", 0x06}, - {"Timer2_A2", 0x07}, - {"Timer3_A2", 0x0b}, - {"Watchdog Timer", 0x01}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -61248,27 +53101,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -61279,27 +53112,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -61309,97 +53141,75 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 98304, .offset = 0x04000, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 3, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -61411,24 +53221,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"SD24B", 0x35}, - {"ADC10", 0x36}, - {"RTC", 0x28}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, {0}, {0}, - {"Timer0_A3", 0x08}, - {"Timer1_A2", 0x06}, - {"Timer2_A2", 0x07}, - {"Timer3_A2", 0x0b}, - {"Watchdog Timer", 0x01}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -61466,27 +53276,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -61497,27 +53287,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -61527,97 +53316,75 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x04000, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -61629,24 +53396,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"SD24B", 0x35}, - {"ADC10", 0x36}, - {"RTC", 0x28}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, {0}, {0}, - {"Timer0_A3", 0x08}, - {"Timer1_A2", 0x06}, - {"Timer2_A2", 0x07}, - {"Timer3_A2", 0x0b}, - {"Watchdog Timer", 0x01}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -61684,27 +53451,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -61715,27 +53462,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -61745,97 +53491,75 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x04000, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -61847,24 +53571,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x00000427, .clock_map = { {0}, {0}, {0}, - {"Comparator D", 0x2b}, - {"ADC10B", 0x37}, - {"RTC", 0x28}, + {"Comparator D", 0xa8}, + {"ADC10B", 0xd6}, + {"RTC", 0x8a}, {0}, - {"eUSCIB0", 0x27}, + {"eUSCIB0", 0x30}, {0}, - {"eUSCIA0", 0x23}, - {"Timer0_B3", 0x16}, + {"eUSCIA0", 0x2c}, + {"Timer0_B3", 0x97}, {0}, {0}, - {"Timer0_A3", 0x08}, - {"Timer1_A3", 0x09}, - {"Watchdog Timer", 0x01}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -61902,27 +53626,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -61933,23 +53637,23 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x38, - [0x11] = 0x39, + [0x09] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, @@ -61959,100 +53663,100 @@ const struct chipinfo chipinfo_db[] = { { | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { - .reg_mask = 0x10018, - .enable_lpm5 = 0x10010, - .disable_lpm5 = 0x00018, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x0f000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01800, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, - .size = 4096, - .offset = 0x00000, + .size = 4064, + .offset = 0x00020, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "EEM", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, + .bits = 16, + .mapped = 1, + .size = 6, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -62064,24 +53768,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x00000427, .clock_map = { {0}, {0}, {0}, - {"Comparator D", 0x2b}, + {"Comparator D", 0xa8}, {0}, - {"RTC", 0x28}, + {"RTC", 0x8a}, {0}, - {"eUSCIB0", 0x27}, + {"eUSCIB0", 0x30}, {0}, - {"eUSCIA0", 0x23}, - {"Timer0_B3", 0x16}, + {"eUSCIA0", 0x2c}, + {"Timer0_B3", 0x97}, {0}, {0}, - {"Timer0_A3", 0x08}, - {"Timer1_A3", 0x09}, - {"Watchdog Timer", 0x01}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -62119,27 +53823,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -62150,23 +53834,23 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x38, - [0x11] = 0x39, + [0x09] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, @@ -62176,100 +53860,100 @@ const struct chipinfo chipinfo_db[] = { { | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { - .reg_mask = 0x10018, - .enable_lpm5 = 0x10010, - .disable_lpm5 = 0x00018, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01800, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, - .size = 4096, - .offset = 0x00000, + .size = 4064, + .offset = 0x00020, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "EEM", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, + .bits = 16, + .mapped = 1, + .size = 6, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -62281,24 +53965,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000043f, .clock_map = { {0}, {0}, {0}, - {"Comparator D", 0x2b}, + {"Comparator D", 0xa8}, {0}, - {"RTC", 0x28}, + {"RTC", 0x8a}, {0}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"Timer0_B3", 0x16}, - {"Timer1_B3", 0x17}, - {"Timer2_B3", 0x18}, - {"Timer0_A3", 0x08}, - {"Timer1_A3", 0x09}, - {"Watchdog Timer", 0x01}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B3", 0x97}, + {"Timer1_B3", 0x98}, + {"Timer2_B3", 0x99}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -62336,27 +54020,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -62367,23 +54031,23 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x38, - [0x11] = 0x39, + [0x09] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, @@ -62393,100 +54057,100 @@ const struct chipinfo chipinfo_db[] = { { | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { - .reg_mask = 0x10018, - .enable_lpm5 = 0x10010, - .disable_lpm5 = 0x00018, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01800, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, - .size = 4096, - .offset = 0x00000, + .size = 4064, + .offset = 0x00020, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "EEM", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, + .bits = 16, + .mapped = 1, + .size = 6, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -62498,24 +54162,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x00000427, .clock_map = { {0}, {0}, {0}, - {"Comparator D", 0x2b}, - {"ADC10B", 0x37}, - {"RTC", 0x28}, + {"Comparator D", 0xa8}, + {"ADC10B", 0xd6}, + {"RTC", 0x8a}, {0}, - {"eUSCIB0", 0x27}, + {"eUSCIB0", 0x30}, {0}, - {"eUSCIA0", 0x23}, - {"Timer0_B3", 0x16}, + {"eUSCIA0", 0x2c}, + {"Timer0_B3", 0x97}, {0}, {0}, - {"Timer0_A3", 0x08}, - {"Timer1_A3", 0x09}, - {"Watchdog Timer", 0x01}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -62553,27 +54217,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -62584,23 +54228,23 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x38, - [0x11] = 0x39, + [0x09] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, @@ -62610,100 +54254,100 @@ const struct chipinfo chipinfo_db[] = { { | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { - .reg_mask = 0x10018, - .enable_lpm5 = 0x10010, - .disable_lpm5 = 0x00018, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01800, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, - .size = 4096, - .offset = 0x00000, + .size = 4064, + .offset = 0x00020, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "EEM", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, + .bits = 16, + .mapped = 1, + .size = 6, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -62715,24 +54359,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x00000427, .clock_map = { {0}, {0}, {0}, - {"Comparator D", 0x2b}, + {"Comparator D", 0xa8}, {0}, - {"RTC", 0x28}, + {"RTC", 0x8a}, {0}, - {"eUSCIB0", 0x27}, + {"eUSCIB0", 0x30}, {0}, - {"eUSCIA0", 0x23}, - {"Timer0_B3", 0x16}, + {"eUSCIA0", 0x2c}, + {"Timer0_B3", 0x97}, {0}, {0}, - {"Timer0_A3", 0x08}, - {"Timer1_A3", 0x09}, - {"Watchdog Timer", 0x01}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -62770,27 +54414,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -62801,23 +54425,23 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x38, - [0x11] = 0x39, + [0x09] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, @@ -62827,100 +54451,100 @@ const struct chipinfo chipinfo_db[] = { { | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { - .reg_mask = 0x10018, - .enable_lpm5 = 0x10010, - .disable_lpm5 = 0x00018, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 15872, .offset = 0x0c200, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01800, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, - .size = 4096, - .offset = 0x00000, + .size = 4064, + .offset = 0x00020, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "EEM", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, + .bits = 16, + .mapped = 1, + .size = 6, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -62932,24 +54556,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x00000427, .clock_map = { {0}, {0}, {0}, - {"Comparator D", 0x2b}, + {"Comparator D", 0xa8}, {0}, - {"RTC", 0x28}, + {"RTC", 0x8a}, {0}, - {"eUSCIB0", 0x27}, + {"eUSCIB0", 0x30}, {0}, - {"eUSCIA0", 0x23}, - {"Timer0_B3", 0x16}, + {"eUSCIA0", 0x2c}, + {"Timer0_B3", 0x97}, {0}, {0}, - {"Timer0_A3", 0x08}, - {"Timer1_A3", 0x09}, - {"Watchdog Timer", 0x01}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -62987,27 +54611,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -63018,23 +54622,23 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x38, - [0x11] = 0x39, + [0x09] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, @@ -63044,100 +54648,100 @@ const struct chipinfo chipinfo_db[] = { { | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { - .reg_mask = 0x10018, - .enable_lpm5 = 0x10010, - .disable_lpm5 = 0x00018, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01800, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, - .size = 4096, - .offset = 0x00000, + .size = 4064, + .offset = 0x00020, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "EEM", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, + .bits = 16, + .mapped = 1, + .size = 6, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -63149,24 +54753,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000043f, .clock_map = { {0}, {0}, {0}, - {"Comparator D", 0x2b}, - {"ADC10B", 0x37}, - {"RTC", 0x28}, + {"Comparator D", 0xa8}, + {"ADC10B", 0xd6}, + {"RTC", 0x8a}, {0}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"Timer0_B3", 0x16}, - {"Timer1_B3", 0x17}, - {"Timer2_B3", 0x18}, - {"Timer0_A3", 0x08}, - {"Timer1_A3", 0x09}, - {"Watchdog Timer", 0x01}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B3", 0x97}, + {"Timer1_B3", 0x98}, + {"Timer2_B3", 0x99}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -63204,27 +54808,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -63235,23 +54819,23 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x38, - [0x11] = 0x39, + [0x09] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, @@ -63261,100 +54845,100 @@ const struct chipinfo chipinfo_db[] = { { | CHIPINFO_FEATURE_QUICK_MEM_READ | CHIPINFO_FEATURE_FRAM, .power = { - .reg_mask = 0x10018, - .enable_lpm5 = 0x10010, - .disable_lpm5 = 0x00018, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x0e000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01800, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 1024, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, - .size = 4096, - .offset = 0x00000, + .size = 4064, + .offset = 0x00020, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "EEM", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, + .bits = 16, + .mapped = 1, + .size = 6, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -63366,24 +54950,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x00000427, .clock_map = { {0}, {0}, {0}, - {"Comparator D", 0x2b}, + {"Comparator D", 0xa8}, {0}, - {"RTC", 0x28}, + {"RTC", 0x8a}, {0}, - {"eUSCIB0", 0x27}, + {"eUSCIB0", 0x30}, {0}, - {"eUSCIA0", 0x23}, - {"Timer0_B3", 0x16}, + {"eUSCIA0", 0x2c}, + {"Timer0_B3", 0x97}, {0}, {0}, - {"Timer0_A3", 0x08}, - {"Timer1_A3", 0x09}, - {"Watchdog Timer", 0x01}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -63421,27 +55005,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x01, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -63452,23 +55016,321 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x38, - [0x11] = 0x39, + [0x09] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 15872, + .offset = 0x0c200, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4064, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 6, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "Legacy", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x00, + .mclk_control = 0x00000000, + .clock_map = { + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8187, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 2700, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 0, + }, + .v3_functions = { + }, + .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_NO_BSL, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "None", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 0, + .offset = 0x00000, + .seg_size = 0, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR5929", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x0000043f, + .clock_map = { + {0}, + {0}, + {0}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {0}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer3_A2", 0x8c}, + {"Timer2_A2", 0x8b}, + {"Timer1_A3", 0x8f}, + {"Timer0_A3", 0x8e}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8187, + .ver_sub_id = 0x0000, + .revision = 0x21, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, @@ -63479,99 +55341,99 @@ const struct chipinfo chipinfo_db[] = { { | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, - .enable_lpm5 = 0x10010, - .disable_lpm5 = 0x00018, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, - .size = 15872, - .offset = 0x0c200, + .size = 64512, + .offset = 0x04400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, - .size = 256, - .offset = 0x01800, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, .size = 2048, - .offset = 0x01000, + .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "bootcode", + .name = "BootCode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "system", + .name = "Info", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, - .size = 1024, - .offset = 0x01c00, + .size = 512, + .offset = 0x01800, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, - .size = 4096, - .offset = 0x00000, + .size = 4064, + .offset = 0x00020, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "EEM", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, + .bits = 16, + .mapped = 1, + .size = 6, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -63583,24 +55445,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x0000841f, .clock_map = { - {"AES128", 0x04}, - {"eUSCIA3", 0x26}, - {"eUSCIA2", 0x25}, - {"SD24B", 0x35}, - {"ADC10", 0x36}, - {"RTC", 0x28}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"eUSCIB1", 0x3b}, - {"Comparator B", 0x2a}, - {"Timer0_A3", 0x08}, - {"Timer1_A2", 0x06}, - {"Timer2_A2", 0x07}, - {"Timer3_A2", 0x0b}, - {"Watchdog Timer", 0x01}, + {"AES128", 0x60}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -63638,27 +55500,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -63669,27 +55511,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -63699,97 +55540,75 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x0c000, .seg_size = 512, - .bank_size = 131072, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -63801,24 +55620,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x0000841f, .clock_map = { - {"AES128", 0x04}, - {"eUSCIA3", 0x26}, - {"eUSCIA2", 0x25}, - {"SD24B", 0x35}, - {"ADC10", 0x36}, - {"RTC", 0x28}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"eUSCIB1", 0x3b}, - {"Comparator B", 0x2a}, - {"Timer0_A3", 0x08}, - {"Timer1_A2", 0x06}, - {"Timer2_A2", 0x07}, - {"Timer3_A2", 0x0b}, - {"Watchdog Timer", 0x01}, + {"AES128", 0x60}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -63856,27 +55675,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -63887,27 +55686,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -63917,97 +55715,75 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x0c000, .seg_size = 512, - .bank_size = 131072, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -64019,24 +55795,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x0000841f, .clock_map = { - {"AES128", 0x04}, - {"eUSCIA3", 0x26}, - {"eUSCIA2", 0x25}, - {"SD24B", 0x35}, - {"ADC10", 0x36}, - {"RTC", 0x28}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"eUSCIB1", 0x3b}, - {"Comparator B", 0x2a}, - {"Timer0_A3", 0x08}, - {"Timer1_A2", 0x06}, - {"Timer2_A2", 0x07}, - {"Timer3_A2", 0x0b}, - {"Watchdog Timer", 0x01}, + {"AES128", 0x60}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -64074,27 +55850,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -64105,27 +55861,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -64135,97 +55890,75 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x0c000, .seg_size = 512, - .bank_size = 131072, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -64237,24 +55970,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x0000841f, .clock_map = { - {"AES128", 0x04}, - {"eUSCIA3", 0x26}, - {"eUSCIA2", 0x25}, - {"SD24B", 0x35}, - {"ADC10", 0x36}, - {"RTC", 0x28}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"eUSCIB1", 0x3b}, - {"Comparator B", 0x2a}, - {"Timer0_A3", 0x08}, - {"Timer1_A2", 0x06}, - {"Timer2_A2", 0x07}, - {"Timer3_A2", 0x0b}, - {"Watchdog Timer", 0x01}, + {"AES128", 0x60}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -64292,27 +56025,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -64323,27 +56036,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -64353,97 +56065,75 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 524288, .offset = 0x0c000, .seg_size = 512, - .bank_size = 131072, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -64455,24 +56145,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x0000841f, .clock_map = { - {"AES128", 0x04}, - {"eUSCIA3", 0x26}, - {"eUSCIA2", 0x25}, - {"SD24B", 0x35}, - {"ADC10", 0x36}, - {"RTC", 0x28}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"eUSCIB1", 0x3b}, - {"Comparator B", 0x2a}, - {"Timer0_A3", 0x08}, - {"Timer1_A2", 0x06}, - {"Timer2_A2", 0x07}, - {"Timer3_A2", 0x0b}, - {"Watchdog Timer", 0x01}, + {"AES128", 0x60}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -64510,27 +56200,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -64541,27 +56211,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -64571,97 +56240,75 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 524288, .offset = 0x0c000, .seg_size = 512, - .bank_size = 131072, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -64673,24 +56320,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x0000841f, .clock_map = { - {"AES128", 0x04}, - {"eUSCIA3", 0x26}, - {"eUSCIA2", 0x25}, - {"SD24B", 0x35}, - {"ADC10", 0x36}, - {"RTC", 0x28}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"eUSCIB1", 0x3b}, - {"Comparator B", 0x2a}, - {"Timer0_A3", 0x08}, - {"Timer1_A2", 0x06}, - {"Timer2_A2", 0x07}, - {"Timer3_A2", 0x0b}, - {"Watchdog Timer", 0x01}, + {"AES128", 0x60}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -64728,27 +56375,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -64759,27 +56386,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -64789,97 +56415,75 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x0c000, .seg_size = 512, - .bank_size = 131072, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -64891,24 +56495,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x0000841f, .clock_map = { - {"AES128", 0x04}, - {"eUSCIA3", 0x26}, - {"eUSCIA2", 0x25}, - {"SD24B", 0x35}, - {"ADC10", 0x36}, - {"RTC", 0x28}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"eUSCIB1", 0x3b}, - {"Comparator B", 0x2a}, - {"Timer0_A3", 0x08}, - {"Timer1_A2", 0x06}, - {"Timer2_A2", 0x07}, - {"Timer3_A2", 0x0b}, - {"Watchdog Timer", 0x01}, + {"AES128", 0x60}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -64946,27 +56550,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -64977,27 +56561,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -65007,97 +56590,75 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x0c000, .seg_size = 512, - .bank_size = 131072, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -65109,24 +56670,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x0000841f, .clock_map = { - {"AES128", 0x04}, - {"eUSCIA3", 0x26}, - {"eUSCIA2", 0x25}, - {"SD24B", 0x35}, - {"ADC10", 0x36}, - {"RTC", 0x28}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"eUSCIB1", 0x3b}, - {"Comparator B", 0x2a}, - {"Timer0_A3", 0x08}, - {"Timer1_A2", 0x06}, - {"Timer2_A2", 0x07}, - {"Timer3_A2", 0x0b}, - {"Watchdog Timer", 0x01}, + {"AES128", 0x60}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -65164,27 +56725,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -65195,27 +56736,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -65225,97 +56765,75 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x0c000, .seg_size = 512, - .bank_size = 131072, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -65327,24 +56845,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x0000841f, .clock_map = { - {"AES128", 0x04}, - {"eUSCIA3", 0x26}, - {"eUSCIA2", 0x25}, - {"SD24B", 0x35}, - {"ADC10", 0x36}, - {"RTC", 0x28}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"eUSCIB1", 0x3b}, - {"Comparator B", 0x2a}, - {"Timer0_A3", 0x08}, - {"Timer1_A2", 0x06}, - {"Timer2_A2", 0x07}, - {"Timer3_A2", 0x0b}, - {"Watchdog Timer", 0x01}, + {"AES128", 0x60}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -65382,27 +56900,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -65413,27 +56911,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -65443,97 +56940,75 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 524288, .offset = 0x0c000, .seg_size = 512, - .bank_size = 131072, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -65545,24 +57020,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x0000841f, .clock_map = { - {"AES128", 0x04}, - {"eUSCIA3", 0x26}, - {"eUSCIA2", 0x25}, - {"SD24B", 0x35}, - {"ADC10", 0x36}, - {"RTC", 0x28}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"eUSCIB1", 0x3b}, - {"Comparator B", 0x2a}, - {"Timer0_A3", 0x08}, - {"Timer1_A2", 0x06}, - {"Timer2_A2", 0x07}, - {"Timer3_A2", 0x0b}, - {"Watchdog Timer", 0x01}, + {"AES128", 0x60}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -65600,27 +57075,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -65631,27 +57086,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -65661,97 +57115,75 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 524288, .offset = 0x0c000, .seg_size = 512, - .bank_size = 131072, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -65763,24 +57195,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x0000841f, .clock_map = { - {"AES128", 0x04}, - {"eUSCIA3", 0x26}, - {"eUSCIA2", 0x25}, - {"SD24B", 0x35}, - {"ADC10", 0x36}, - {"RTC", 0x28}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"eUSCIB1", 0x3b}, - {"Comparator B", 0x2a}, - {"Timer0_A3", 0x08}, - {"Timer1_A2", 0x06}, - {"Timer2_A2", 0x07}, - {"Timer3_A2", 0x0b}, - {"Watchdog Timer", 0x01}, + {"AES128", 0x60}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -65818,27 +57250,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -65849,27 +57261,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -65879,97 +57290,75 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x0c000, .seg_size = 512, - .bank_size = 131072, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -65981,24 +57370,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x0000841f, .clock_map = { - {"AES128", 0x04}, - {"eUSCIA3", 0x26}, - {"eUSCIA2", 0x25}, - {"SD24B", 0x35}, - {"ADC10", 0x36}, - {"RTC", 0x28}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"eUSCIB1", 0x3b}, - {"Comparator B", 0x2a}, - {"Timer0_A3", 0x08}, - {"Timer1_A2", 0x06}, - {"Timer2_A2", 0x07}, - {"Timer3_A2", 0x0b}, - {"Watchdog Timer", 0x01}, + {"AES128", 0x60}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -66036,27 +57425,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -66067,27 +57436,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -66097,97 +57465,75 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x0c000, .seg_size = 512, - .bank_size = 131072, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -66199,24 +57545,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x0000841f, .clock_map = { - {"AES128", 0x04}, - {"eUSCIA3", 0x26}, - {"eUSCIA2", 0x25}, - {"SD24B", 0x35}, - {"ADC10", 0x36}, - {"RTC", 0x28}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"eUSCIB1", 0x3b}, - {"Comparator B", 0x2a}, - {"Timer0_A3", 0x08}, - {"Timer1_A2", 0x06}, - {"Timer2_A2", 0x07}, - {"Timer3_A2", 0x0b}, - {"Watchdog Timer", 0x01}, + {"AES128", 0x60}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -66254,27 +57600,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -66285,27 +57611,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -66315,97 +57640,75 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x0c000, .seg_size = 512, - .bank_size = 131072, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -66417,24 +57720,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x0000841f, .clock_map = { - {"AES128", 0x04}, - {"eUSCIA3", 0x26}, - {"eUSCIA2", 0x25}, - {"SD24B", 0x35}, - {"ADC10", 0x36}, - {"RTC", 0x28}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"eUSCIB1", 0x3b}, - {"Comparator B", 0x2a}, - {"Timer0_A3", 0x08}, - {"Timer1_A2", 0x06}, - {"Timer2_A2", 0x07}, - {"Timer3_A2", 0x0b}, - {"Watchdog Timer", 0x01}, + {"AES128", 0x60}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -66472,27 +57775,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -66503,27 +57786,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -66533,97 +57815,75 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 524288, .offset = 0x0c000, .seg_size = 512, - .bank_size = 131072, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -66635,24 +57895,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x0000841f, .clock_map = { - {"AES128", 0x04}, - {"eUSCIA3", 0x26}, - {"eUSCIA2", 0x25}, - {"SD24B", 0x35}, - {"ADC10", 0x36}, - {"RTC", 0x28}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"eUSCIB1", 0x3b}, - {"Comparator B", 0x2a}, - {"Timer0_A3", 0x08}, - {"Timer1_A2", 0x06}, - {"Timer2_A2", 0x07}, - {"Timer3_A2", 0x0b}, - {"Watchdog Timer", 0x01}, + {"AES128", 0x60}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -66690,27 +57950,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -66721,27 +57961,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -66751,97 +57990,75 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 524288, .offset = 0x0c000, .seg_size = 512, - .bank_size = 131072, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -66853,24 +58070,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x0000041f, .clock_map = { {0}, - {"eUSCIA3", 0x26}, - {"eUSCIA2", 0x25}, - {"SD24B", 0x35}, - {"ADC10", 0x36}, - {"RTC", 0x28}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"eUSCIB1", 0x3b}, - {"Comparator B", 0x2a}, - {"Timer0_A3", 0x08}, - {"Timer1_A2", 0x06}, - {"Timer2_A2", 0x07}, - {"Timer3_A2", 0x0b}, - {"Watchdog Timer", 0x01}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -66908,27 +58125,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -66939,27 +58136,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -66969,97 +58165,75 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x0c000, .seg_size = 512, - .bank_size = 131072, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -67071,24 +58245,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x0000041f, .clock_map = { {0}, - {"eUSCIA3", 0x26}, - {"eUSCIA2", 0x25}, - {"SD24B", 0x35}, - {"ADC10", 0x36}, - {"RTC", 0x28}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"eUSCIB1", 0x3b}, - {"Comparator B", 0x2a}, - {"Timer0_A3", 0x08}, - {"Timer1_A2", 0x06}, - {"Timer2_A2", 0x07}, - {"Timer3_A2", 0x0b}, - {"Watchdog Timer", 0x01}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -67126,27 +58300,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -67157,27 +58311,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -67187,97 +58340,75 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x0c000, .seg_size = 512, - .bank_size = 131072, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -67289,24 +58420,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x0000041f, .clock_map = { {0}, - {"eUSCIA3", 0x26}, - {"eUSCIA2", 0x25}, - {"SD24B", 0x35}, - {"ADC10", 0x36}, - {"RTC", 0x28}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"eUSCIB1", 0x3b}, - {"Comparator B", 0x2a}, - {"Timer0_A3", 0x08}, - {"Timer1_A2", 0x06}, - {"Timer2_A2", 0x07}, - {"Timer3_A2", 0x0b}, - {"Watchdog Timer", 0x01}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -67344,27 +58475,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -67375,27 +58486,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -67405,97 +58515,75 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x0c000, .seg_size = 512, - .bank_size = 131072, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -67507,24 +58595,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x0000041f, .clock_map = { {0}, - {"eUSCIA3", 0x26}, - {"eUSCIA2", 0x25}, - {"SD24B", 0x35}, - {"ADC10", 0x36}, - {"RTC", 0x28}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"eUSCIB1", 0x3b}, - {"Comparator B", 0x2a}, - {"Timer0_A3", 0x08}, - {"Timer1_A2", 0x06}, - {"Timer2_A2", 0x07}, - {"Timer3_A2", 0x0b}, - {"Watchdog Timer", 0x01}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -67562,27 +58650,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -67593,27 +58661,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -67623,97 +58690,75 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 524288, .offset = 0x0c000, .seg_size = 512, - .bank_size = 131072, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -67725,24 +58770,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x0000041f, .clock_map = { {0}, - {"eUSCIA3", 0x26}, - {"eUSCIA2", 0x25}, - {"SD24B", 0x35}, - {"ADC10", 0x36}, - {"RTC", 0x28}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"eUSCIB1", 0x3b}, - {"Comparator B", 0x2a}, - {"Timer0_A3", 0x08}, - {"Timer1_A2", 0x06}, - {"Timer2_A2", 0x07}, - {"Timer3_A2", 0x0b}, - {"Watchdog Timer", 0x01}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -67780,27 +58825,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -67811,27 +58836,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -67841,97 +58865,75 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 524288, .offset = 0x0c000, .seg_size = 512, - .bank_size = 131072, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -67943,24 +58945,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x0000041f, .clock_map = { {0}, - {"eUSCIA3", 0x26}, - {"eUSCIA2", 0x25}, - {"SD24B", 0x35}, - {"ADC10", 0x36}, - {"RTC", 0x28}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"eUSCIB1", 0x3b}, - {"Comparator B", 0x2a}, - {"Timer0_A3", 0x08}, - {"Timer1_A2", 0x06}, - {"Timer2_A2", 0x07}, - {"Timer3_A2", 0x0b}, - {"Watchdog Timer", 0x01}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -67998,27 +59000,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -68029,27 +59011,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -68059,97 +59040,75 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x0c000, .seg_size = 512, - .bank_size = 131072, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -68161,24 +59120,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x0000041f, .clock_map = { {0}, - {"eUSCIA3", 0x26}, - {"eUSCIA2", 0x25}, - {"SD24B", 0x35}, - {"ADC10", 0x36}, - {"RTC", 0x28}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"eUSCIB1", 0x3b}, - {"Comparator B", 0x2a}, - {"Timer0_A3", 0x08}, - {"Timer1_A2", 0x06}, - {"Timer2_A2", 0x07}, - {"Timer3_A2", 0x0b}, - {"Watchdog Timer", 0x01}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -68216,27 +59175,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -68247,27 +59186,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -68277,97 +59215,75 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x0c000, .seg_size = 512, - .bank_size = 131072, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -68379,24 +59295,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x0000041f, .clock_map = { {0}, - {"eUSCIA3", 0x26}, - {"eUSCIA2", 0x25}, - {"SD24B", 0x35}, - {"ADC10", 0x36}, - {"RTC", 0x28}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"eUSCIB1", 0x3b}, - {"Comparator B", 0x2a}, - {"Timer0_A3", 0x08}, - {"Timer1_A2", 0x06}, - {"Timer2_A2", 0x07}, - {"Timer3_A2", 0x0b}, - {"Watchdog Timer", 0x01}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -68434,27 +59350,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -68465,27 +59361,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -68495,97 +59390,75 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x0c000, .seg_size = 512, - .bank_size = 131072, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -68597,24 +59470,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x0000041f, .clock_map = { {0}, - {"eUSCIA3", 0x26}, - {"eUSCIA2", 0x25}, - {"SD24B", 0x35}, - {"ADC10", 0x36}, - {"RTC", 0x28}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"eUSCIB1", 0x3b}, - {"Comparator B", 0x2a}, - {"Timer0_A3", 0x08}, - {"Timer1_A2", 0x06}, - {"Timer2_A2", 0x07}, - {"Timer3_A2", 0x0b}, - {"Watchdog Timer", 0x01}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -68652,27 +59525,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -68683,27 +59536,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -68713,97 +59565,75 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 524288, .offset = 0x0c000, .seg_size = 512, - .bank_size = 131072, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -68815,24 +59645,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x0000041f, .clock_map = { {0}, - {"eUSCIA3", 0x26}, - {"eUSCIA2", 0x25}, - {"SD24B", 0x35}, - {"ADC10", 0x36}, - {"RTC", 0x28}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"eUSCIB1", 0x3b}, - {"Comparator B", 0x2a}, - {"Timer0_A3", 0x08}, - {"Timer1_A2", 0x06}, - {"Timer2_A2", 0x07}, - {"Timer3_A2", 0x0b}, - {"Watchdog Timer", 0x01}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -68870,27 +59700,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -68901,27 +59711,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -68931,97 +59740,75 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 524288, .offset = 0x0c000, .seg_size = 512, - .bank_size = 131072, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -69033,24 +59820,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x0000041f, .clock_map = { {0}, - {"eUSCIA3", 0x26}, - {"eUSCIA2", 0x25}, - {"SD24B", 0x35}, - {"ADC10", 0x36}, - {"RTC", 0x28}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"eUSCIB1", 0x3b}, - {"Comparator B", 0x2a}, - {"Timer0_A3", 0x08}, - {"Timer1_A2", 0x06}, - {"Timer2_A2", 0x07}, - {"Timer3_A2", 0x0b}, - {"Watchdog Timer", 0x01}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -69088,27 +59875,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -69119,27 +59886,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -69149,97 +59915,75 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x0c000, .seg_size = 512, - .bank_size = 131072, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -69251,24 +59995,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x0000041f, .clock_map = { {0}, - {"eUSCIA3", 0x26}, - {"eUSCIA2", 0x25}, - {"SD24B", 0x35}, - {"ADC10", 0x36}, - {"RTC", 0x28}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"eUSCIB1", 0x3b}, - {"Comparator B", 0x2a}, - {"Timer0_A3", 0x08}, - {"Timer1_A2", 0x06}, - {"Timer2_A2", 0x07}, - {"Timer3_A2", 0x0b}, - {"Watchdog Timer", 0x01}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -69306,27 +60050,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -69337,27 +60061,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -69367,97 +60090,75 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x0c000, .seg_size = 512, - .bank_size = 131072, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -69469,24 +60170,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x0000041f, .clock_map = { {0}, - {"eUSCIA3", 0x26}, - {"eUSCIA2", 0x25}, - {"SD24B", 0x35}, - {"ADC10", 0x36}, - {"RTC", 0x28}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"eUSCIB1", 0x3b}, - {"Comparator B", 0x2a}, - {"Timer0_A3", 0x08}, - {"Timer1_A2", 0x06}, - {"Timer2_A2", 0x07}, - {"Timer3_A2", 0x0b}, - {"Watchdog Timer", 0x01}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -69524,27 +60225,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -69555,27 +60236,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -69585,97 +60265,75 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x0c000, .seg_size = 512, - .bank_size = 131072, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -69687,24 +60345,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x0000041f, .clock_map = { {0}, - {"eUSCIA3", 0x26}, - {"eUSCIA2", 0x25}, - {"SD24B", 0x35}, - {"ADC10", 0x36}, - {"RTC", 0x28}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"eUSCIB1", 0x3b}, - {"Comparator B", 0x2a}, - {"Timer0_A3", 0x08}, - {"Timer1_A2", 0x06}, - {"Timer2_A2", 0x07}, - {"Timer3_A2", 0x0b}, - {"Watchdog Timer", 0x01}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -69742,27 +60400,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -69773,27 +60411,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -69803,97 +60440,75 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 524288, .offset = 0x0c000, .seg_size = 512, - .bank_size = 131072, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -69905,24 +60520,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x2407, + .mclk_control = 0x0000041f, .clock_map = { {0}, - {"eUSCIA3", 0x26}, - {"eUSCIA2", 0x25}, - {"SD24B", 0x35}, - {"ADC10", 0x36}, - {"RTC", 0x28}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"eUSCIB1", 0x3b}, - {"Comparator B", 0x2a}, - {"Timer0_A3", 0x08}, - {"Timer1_A2", 0x06}, - {"Timer2_A2", 0x07}, - {"Timer3_A2", 0x0b}, - {"Watchdog Timer", 0x01}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -69960,27 +60575,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -69991,27 +60586,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -70021,97 +60615,75 @@ const struct chipinfo chipinfo_db[] = { { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, .disable_lpm5 = 0x00000, - .reg_mask_3v = 0x04020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 524288, .offset = 0x0c000, .seg_size = 512, - .bank_size = 131072, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -70119,28 +60691,28 @@ const struct chipinfo chipinfo_db[] = { { }, { - .name = "MSP430FR6987", + .name = "Legacy", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, - .clock_control = 0x02, - .mclk_control = 0xbdff, + .clock_control = 0x00, + .mclk_control = 0x00000000, .clock_map = { - {"Timer1_A2", 0x06}, - {"LCDB", 0x2c}, - {"AES128", 0x04}, - {"Comparator D", 0x2b}, - {"ADC12B", 0x38}, - {"RTC", 0x28}, {0}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"Timer0_B7", 0x1c}, - {"Timer0_A3", 0x08}, - {"Timer1_A3", 0x09}, - {"Timer2_A3", 0x0a}, - {"Timer0_A2", 0x05}, - {"Watchdog Timer", 0x01}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, {0}, {0}, {0}, @@ -70171,34 +60743,115 @@ const struct chipinfo chipinfo_db[] = { { .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, - .revision = 0x00, + .revision = 0xff, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 2700, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 0, }, + .v3_functions = { + }, + .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_NO_BSL, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "None", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 0, + .offset = 0x00000, + .seg_size = 0, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR6987", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x0000043f, + .clock_map = { + {"PORT", 0x50}, + {"LCDC", 0xb0}, + {0}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {"eUSCIB1", 0x31}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A5", 0x91}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x81a6, + .ver_sub_id = 0x0000, + .revision = 0x21, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -70209,22 +60862,23 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x38, - [0x11] = 0x39, + [0x09] = 0x39, + [0x0a] = 0x4a, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, - [0x1c] = 0x41, + [0x1a] = 0x40, + [0x1c] = 0x50, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, + [0x20] = 0x45, + [0x26] = 0x37, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, @@ -70235,110 +60889,99 @@ const struct chipinfo chipinfo_db[] = { { | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, - .enable_lpm5 = 0x10000, + .enable_lpm5 = 0x10018, .disable_lpm5 = 0x10000, - .reg_mask_3v = 0x0c020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 64512, .offset = 0x04400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "system", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, - .size = 128, - .offset = 0x03c00, + .size = 512, + .offset = 0x01800, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, - .size = 4096, - .offset = 0x00000, + .size = 4064, + .offset = 0x00020, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "EEM", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, + .bits = 16, + .mapped = 1, + .size = 6, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -70346,28 +60989,28 @@ const struct chipinfo chipinfo_db[] = { { }, { - .name = "MSP430FR6988", + .name = "Legacy", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, - .clock_control = 0x02, - .mclk_control = 0xbdff, + .clock_control = 0x00, + .mclk_control = 0x00000000, .clock_map = { - {"Timer1_A2", 0x06}, - {"LCDB", 0x2c}, - {"AES128", 0x04}, - {"Comparator D", 0x2b}, - {"ADC12B", 0x38}, - {"RTC", 0x28}, {0}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"Timer0_B7", 0x1c}, - {"Timer0_A3", 0x08}, - {"Timer1_A3", 0x09}, - {"Timer2_A3", 0x0a}, - {"Timer0_A2", 0x05}, - {"Watchdog Timer", 0x01}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, {0}, {0}, {0}, @@ -70398,34 +61041,115 @@ const struct chipinfo chipinfo_db[] = { { .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, - .revision = 0x00, + .revision = 0xff, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 2700, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 0, }, + .v3_functions = { + }, + .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_NO_BSL, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "None", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 0, + .offset = 0x00000, + .seg_size = 0, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR6988", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x0000043f, + .clock_map = { + {"PORT", 0x50}, + {"LCDC", 0xb0}, + {0}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {"eUSCIB1", 0x31}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A5", 0x91}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x81a7, + .ver_sub_id = 0x0000, + .revision = 0x21, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -70436,22 +61160,23 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x38, - [0x11] = 0x39, + [0x09] = 0x39, + [0x0a] = 0x4a, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, - [0x1c] = 0x41, + [0x1a] = 0x40, + [0x1c] = 0x50, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, + [0x20] = 0x45, + [0x26] = 0x37, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, @@ -70462,110 +61187,99 @@ const struct chipinfo chipinfo_db[] = { { | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, - .enable_lpm5 = 0x10000, + .enable_lpm5 = 0x10018, .disable_lpm5 = 0x10000, - .reg_mask_3v = 0x0c020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 97280, .offset = 0x04400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "system", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, - .size = 128, - .offset = 0x03c00, + .size = 512, + .offset = 0x01800, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, - .size = 4096, - .offset = 0x00000, + .size = 4064, + .offset = 0x00020, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "EEM", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, + .bits = 16, + .mapped = 1, + .size = 6, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -70573,28 +61287,28 @@ const struct chipinfo chipinfo_db[] = { { }, { - .name = "MSP430FR6989", + .name = "Legacy", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, - .clock_control = 0x02, - .mclk_control = 0xbdff, + .clock_control = 0x00, + .mclk_control = 0x00000000, .clock_map = { - {"Timer1_A2", 0x06}, - {"LCDB", 0x2c}, - {"AES128", 0x04}, - {"Comparator D", 0x2b}, - {"ADC12B", 0x38}, - {"RTC", 0x28}, {0}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"Timer0_B7", 0x1c}, - {"Timer0_A3", 0x08}, - {"Timer1_A3", 0x09}, - {"Timer2_A3", 0x0a}, - {"Timer0_A2", 0x05}, - {"Watchdog Timer", 0x01}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, {0}, {0}, {0}, @@ -70625,34 +61339,115 @@ const struct chipinfo chipinfo_db[] = { { .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, - .revision = 0x00, + .revision = 0xff, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 2700, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 0, }, + .v3_functions = { + }, + .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_NO_BSL, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "None", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 0, + .offset = 0x00000, + .seg_size = 0, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR6989", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x0000043f, + .clock_map = { + {"PORT", 0x50}, + {"LCDC", 0xb0}, + {0}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {"eUSCIB1", 0x31}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A5", 0x91}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x81a8, + .ver_sub_id = 0x0000, + .revision = 0x21, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -70663,22 +61458,23 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x38, - [0x11] = 0x39, + [0x09] = 0x39, + [0x0a] = 0x4a, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, - [0x1c] = 0x41, + [0x1a] = 0x40, + [0x1c] = 0x50, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, + [0x20] = 0x45, + [0x26] = 0x37, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, @@ -70689,110 +61485,99 @@ const struct chipinfo chipinfo_db[] = { { | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, - .enable_lpm5 = 0x10000, + .enable_lpm5 = 0x10018, .disable_lpm5 = 0x10000, - .reg_mask_3v = 0x0c020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 130048, .offset = 0x04400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "system", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, - .size = 128, - .offset = 0x03c00, + .size = 512, + .offset = 0x01800, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, - .size = 4096, - .offset = 0x00000, + .size = 4064, + .offset = 0x00020, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "EEM", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, + .bits = 16, + .mapped = 1, + .size = 6, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -70800,28 +61585,326 @@ const struct chipinfo chipinfo_db[] = { { }, { - .name = "MSP430FR5988", + .name = "Legacy", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x00, + .mclk_control = 0x00000000, + .clock_map = { + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x81a9, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 2700, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 0, + }, + .v3_functions = { + }, + .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_NO_BSL, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "None", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 0, + .offset = 0x00000, + .seg_size = 0, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR5987", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0xbdff, + .mclk_control = 0x0000043f, .clock_map = { - {"Timer1_A2", 0x06}, + {"PORT", 0x50}, + {0}, + {0}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {"eUSCIB1", 0x31}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A5", 0x91}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x81a9, + .ver_sub_id = 0x0000, + .revision = 0x21, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 64512, + .offset = 0x04400, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4064, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 6, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "Legacy", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x00, + .mclk_control = 0x00000000, + .clock_map = { + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, {0}, - {"AES128", 0x04}, - {"Comparator D", 0x2b}, - {"ADC12B", 0x38}, - {"RTC", 0x28}, {0}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"Timer0_B7", 0x1c}, - {"Timer0_A3", 0x08}, - {"Timer1_A3", 0x09}, - {"Timer2_A3", 0x0a}, - {"Timer0_A2", 0x05}, - {"Watchdog Timer", 0x01}, {0}, {0}, {0}, @@ -70852,34 +61935,115 @@ const struct chipinfo chipinfo_db[] = { { .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, - .revision = 0x00, + .revision = 0xff, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 2700, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 0, }, + .v3_functions = { + }, + .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_NO_BSL, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "None", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 0, + .offset = 0x00000, + .seg_size = 0, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR5988", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x0000043f, + .clock_map = { + {"PORT", 0x50}, + {0}, + {0}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {"eUSCIB1", 0x31}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A5", 0x91}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x81aa, + .ver_sub_id = 0x0000, + .revision = 0x21, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -70890,22 +62054,23 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x38, - [0x11] = 0x39, + [0x09] = 0x39, + [0x0a] = 0x4a, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, - [0x1c] = 0x41, + [0x1a] = 0x40, + [0x1c] = 0x50, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, + [0x20] = 0x45, + [0x26] = 0x37, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, @@ -70916,110 +62081,99 @@ const struct chipinfo chipinfo_db[] = { { | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, - .enable_lpm5 = 0x10000, + .enable_lpm5 = 0x10018, .disable_lpm5 = 0x10000, - .reg_mask_3v = 0x0c020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 97280, .offset = 0x04400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "system", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, - .size = 128, - .offset = 0x03c00, + .size = 512, + .offset = 0x01800, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, - .size = 4096, - .offset = 0x00000, + .size = 4064, + .offset = 0x00020, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "EEM", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, + .bits = 16, + .mapped = 1, + .size = 6, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -71027,28 +62181,28 @@ const struct chipinfo chipinfo_db[] = { { }, { - .name = "MSP430FR5989", + .name = "Legacy", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, - .clock_control = 0x02, - .mclk_control = 0xbdff, + .clock_control = 0x00, + .mclk_control = 0x00000000, .clock_map = { - {"Timer1_A2", 0x06}, {0}, - {"AES128", 0x04}, - {"Comparator D", 0x2b}, - {"ADC12B", 0x38}, - {"RTC", 0x28}, {0}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"Timer0_B7", 0x1c}, - {"Timer0_A3", 0x08}, - {"Timer1_A3", 0x09}, - {"Timer2_A3", 0x0a}, - {"Timer0_A2", 0x05}, - {"Watchdog Timer", 0x01}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, {0}, {0}, {0}, @@ -71079,34 +62233,115 @@ const struct chipinfo chipinfo_db[] = { { .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, - .revision = 0x00, + .revision = 0xff, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 2700, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 0, }, + .v3_functions = { + }, + .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_NO_BSL, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "None", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 0, + .offset = 0x00000, + .seg_size = 0, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR5989", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x0000043f, + .clock_map = { + {"PORT", 0x50}, + {0}, + {0}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {"eUSCIB1", 0x31}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A5", 0x91}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x81ab, + .ver_sub_id = 0x0000, + .revision = 0x21, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -71117,22 +62352,23 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x38, - [0x11] = 0x39, + [0x09] = 0x39, + [0x0a] = 0x4a, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, - [0x1c] = 0x41, + [0x1a] = 0x40, + [0x1c] = 0x50, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, + [0x20] = 0x45, + [0x26] = 0x37, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, @@ -71143,110 +62379,99 @@ const struct chipinfo chipinfo_db[] = { { | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, - .enable_lpm5 = 0x10000, + .enable_lpm5 = 0x10018, .disable_lpm5 = 0x10000, - .reg_mask_3v = 0x0c020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 130048, .offset = 0x04400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "system", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, - .size = 128, - .offset = 0x03c00, + .size = 512, + .offset = 0x01800, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, - .size = 4096, - .offset = 0x00000, + .size = 4064, + .offset = 0x00020, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "EEM", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, + .bits = 16, + .mapped = 1, + .size = 6, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -71254,28 +62479,28 @@ const struct chipinfo chipinfo_db[] = { { }, { - .name = "MSP430FR6977", + .name = "Legacy", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, - .clock_control = 0x02, - .mclk_control = 0xbdff, + .clock_control = 0x00, + .mclk_control = 0x00000000, .clock_map = { - {"Timer1_A2", 0x06}, - {"LCDB", 0x2c}, - {"AES128", 0x04}, - {"Comparator D", 0x2b}, - {"ADC12B", 0x38}, - {"RTC", 0x28}, {0}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"Timer0_B7", 0x1c}, - {"Timer0_A3", 0x08}, - {"Timer1_A3", 0x09}, - {"Timer2_A3", 0x0a}, - {"Timer0_A2", 0x05}, - {"Watchdog Timer", 0x01}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, {0}, {0}, {0}, @@ -71306,174 +62531,48 @@ const struct chipinfo chipinfo_db[] = { { .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, - .revision = 0x00, + .revision = 0xff, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, - .vcc_flash_min = 1800, + .vcc_flash_min = 2700, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, - .has_test_vpp = 1, + .has_test_vpp = 0, }, .v3_functions = { - [0x09] = 0x38, - [0x11] = 0x39, - [0x12] = 0x3a, - [0x13] = 0x3b, - [0x14] = 0x3c, - [0x15] = 0x3c, - [0x16] = 0x3d, - [0x17] = 0x3e, - [0x18] = 0x3e, - [0x19] = 0x3f, - [0x1b] = 0x40, - [0x1c] = 0x41, - [0x1d] = 0x42, - [0x1e] = 0x43, - [0x1f] = 0x44, - [0x25] = 0x36, }, - .v3_erase = &erase_xv2_fram, - .v3_write = &write_xv2_fram, - .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ - | CHIPINFO_FEATURE_FRAM, + | CHIPINFO_FEATURE_NO_BSL, .power = { - .reg_mask = 0x10018, - .enable_lpm5 = 0x10000, - .disable_lpm5 = 0x10000, - .reg_mask_3v = 0x0c020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", - .type = CHIPINFO_MEMTYPE_RAM, + .name = "None", + .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, - .size = 64512, - .offset = 0x04400, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "information", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 128, - .offset = 0x03c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "peripheral16bit", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 16, - .mapped = 1, - .size = 4096, + .size = 0, .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .seg_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -71481,28 +62580,28 @@ const struct chipinfo chipinfo_db[] = { { }, { - .name = "MSP430FR6978", + .name = "MSP430FR6977", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0xbdff, + .mclk_control = 0x0000043f, .clock_map = { - {"Timer1_A2", 0x06}, - {"LCDB", 0x2c}, - {"AES128", 0x04}, - {"Comparator D", 0x2b}, - {"ADC12B", 0x38}, - {"RTC", 0x28}, + {"PORT", 0x50}, + {"LCDC", 0xb0}, {0}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"Timer0_B7", 0x1c}, - {"Timer0_A3", 0x08}, - {"Timer1_A3", 0x09}, - {"Timer2_A3", 0x0a}, - {"Timer0_A2", 0x05}, - {"Watchdog Timer", 0x01}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {"eUSCIB1", 0x31}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -71521,9 +62620,9 @@ const struct chipinfo chipinfo_db[] = { { {0}, }, .id = { - .ver_id = 0x81ad, + .ver_id = 0x81ac, .ver_sub_id = 0x0000, - .revision = 0x00, + .revision = 0x21, .fab = 0x00, .self = 0x0000, .config = 0x00, @@ -71533,34 +62632,14 @@ const struct chipinfo chipinfo_db[] = { { .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, - .revision = 0x00, + .revision = 0xff, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -71571,22 +62650,23 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x38, - [0x11] = 0x39, + [0x09] = 0x39, + [0x0a] = 0x4a, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, - [0x1c] = 0x41, + [0x1a] = 0x40, + [0x1c] = 0x50, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, + [0x20] = 0x45, + [0x26] = 0x37, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, @@ -71597,110 +62677,99 @@ const struct chipinfo chipinfo_db[] = { { | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, - .enable_lpm5 = 0x10000, + .enable_lpm5 = 0x10018, .disable_lpm5 = 0x10000, - .reg_mask_3v = 0x0c020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, - .size = 97280, + .size = 64512, .offset = 0x04400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "system", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, - .size = 128, - .offset = 0x03c00, + .size = 512, + .offset = 0x01800, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, - .size = 4096, - .offset = 0x00000, + .size = 4064, + .offset = 0x00020, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "EEM", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, + .bits = 16, + .mapped = 1, + .size = 6, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -71708,28 +62777,28 @@ const struct chipinfo chipinfo_db[] = { { }, { - .name = "MSP430FR6979", + .name = "Legacy", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, - .clock_control = 0x02, - .mclk_control = 0xbdff, + .clock_control = 0x00, + .mclk_control = 0x00000000, .clock_map = { - {"Timer1_A2", 0x06}, - {"LCDB", 0x2c}, - {"AES128", 0x04}, - {"Comparator D", 0x2b}, - {"ADC12B", 0x38}, - {"RTC", 0x28}, {0}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"Timer0_B7", 0x1c}, - {"Timer0_A3", 0x08}, - {"Timer1_A3", 0x09}, - {"Timer2_A3", 0x0a}, - {"Timer0_A2", 0x05}, - {"Watchdog Timer", 0x01}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, {0}, {0}, {0}, @@ -71760,174 +62829,48 @@ const struct chipinfo chipinfo_db[] = { { .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, - .revision = 0x00, + .revision = 0xff, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, - .vcc_flash_min = 1800, + .vcc_flash_min = 2700, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, - .has_test_vpp = 1, + .has_test_vpp = 0, }, .v3_functions = { - [0x09] = 0x38, - [0x11] = 0x39, - [0x12] = 0x3a, - [0x13] = 0x3b, - [0x14] = 0x3c, - [0x15] = 0x3c, - [0x16] = 0x3d, - [0x17] = 0x3e, - [0x18] = 0x3e, - [0x19] = 0x3f, - [0x1b] = 0x40, - [0x1c] = 0x41, - [0x1d] = 0x42, - [0x1e] = 0x43, - [0x1f] = 0x44, - [0x25] = 0x36, }, - .v3_erase = &erase_xv2_fram, - .v3_write = &write_xv2_fram, - .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ - | CHIPINFO_FEATURE_FRAM, + | CHIPINFO_FEATURE_NO_BSL, .power = { - .reg_mask = 0x10018, - .enable_lpm5 = 0x10000, - .disable_lpm5 = 0x10000, - .reg_mask_3v = 0x0c020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", - .type = CHIPINFO_MEMTYPE_RAM, + .name = "None", + .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, - .size = 130048, - .offset = 0x04400, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "information", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 128, - .offset = 0x03c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "peripheral16bit", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 16, - .mapped = 1, - .size = 4096, + .size = 0, .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .seg_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -71935,28 +62878,28 @@ const struct chipinfo chipinfo_db[] = { { }, { - .name = "MSP430FR5977", + .name = "MSP430FR6979", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0xbdff, + .mclk_control = 0x0000043f, .clock_map = { - {"Timer1_A2", 0x06}, + {"PORT", 0x50}, + {"LCDC", 0xb0}, {0}, - {"AES128", 0x04}, - {"Comparator D", 0x2b}, - {"ADC12B", 0x38}, - {"RTC", 0x28}, - {0}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"Timer0_B7", 0x1c}, - {"Timer0_A3", 0x08}, - {"Timer1_A3", 0x09}, - {"Timer2_A3", 0x0a}, - {"Timer0_A2", 0x05}, - {"Watchdog Timer", 0x01}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {"eUSCIB1", 0x31}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -71975,7 +62918,204 @@ const struct chipinfo chipinfo_db[] = { { {0}, }, .id = { - .ver_id = 0x81af, + .ver_id = 0x81ae, + .ver_sub_id = 0x0000, + .revision = 0x21, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 130048, + .offset = 0x04400, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4064, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 6, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "Legacy", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x00, + .mclk_control = 0x00000000, + .clock_map = { + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x81b2, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, @@ -71987,34 +63127,115 @@ const struct chipinfo chipinfo_db[] = { { .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, - .revision = 0x00, + .revision = 0xff, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 2700, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 0, }, + .v3_functions = { + }, + .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_NO_BSL, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "None", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 0, + .offset = 0x00000, + .seg_size = 0, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR6927", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x0000043f, + .clock_map = { + {"PORT", 0x50}, + {"LCDC", 0xb0}, + {0}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {"eUSCIB1", 0x31}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A5", 0x91}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x81b2, + .ver_sub_id = 0x0000, + .revision = 0x21, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -72025,22 +63246,23 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x38, - [0x11] = 0x39, + [0x09] = 0x39, + [0x0a] = 0x4a, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, - [0x1c] = 0x41, + [0x1a] = 0x40, + [0x1c] = 0x50, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, + [0x20] = 0x45, + [0x26] = 0x37, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, @@ -72051,110 +63273,99 @@ const struct chipinfo chipinfo_db[] = { { | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, - .enable_lpm5 = 0x10000, + .enable_lpm5 = 0x10018, .disable_lpm5 = 0x10000, - .reg_mask_3v = 0x0c020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 64512, .offset = 0x04400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "system", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, - .size = 128, - .offset = 0x03c00, + .size = 512, + .offset = 0x01800, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, - .size = 4096, - .offset = 0x00000, + .size = 4064, + .offset = 0x00020, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "EEM", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, + .bits = 16, + .mapped = 1, + .size = 6, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -72162,28 +63373,12 @@ const struct chipinfo chipinfo_db[] = { { }, { - .name = "MSP430FR5978", + .name = "Legacy", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, - .clock_control = 0x02, - .mclk_control = 0xbdff, + .clock_control = 0x00, + .mclk_control = 0x00000000, .clock_map = { - {"Timer1_A2", 0x06}, - {0}, - {"AES128", 0x04}, - {"Comparator D", 0x2b}, - {"ADC12B", 0x38}, - {"RTC", 0x28}, - {0}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"Timer0_B7", 0x1c}, - {"Timer0_A3", 0x08}, - {"Timer1_A3", 0x09}, - {"Timer2_A3", 0x0a}, - {"Timer0_A2", 0x05}, - {"Watchdog Timer", 0x01}, {0}, {0}, {0}, @@ -72200,444 +63395,6 @@ const struct chipinfo chipinfo_db[] = { { {0}, {0}, {0}, - }, - .id = { - .ver_id = 0x81b0, - .ver_sub_id = 0x0000, - .revision = 0x00, - .fab = 0x00, - .self = 0x0000, - .config = 0x00, - .fuses = 0x00, - .activation_key = 0x00000000, - }, - .id_mask = { - .ver_id = 0xffff, - .ver_sub_id = 0xffff, - .revision = 0x00, - .fab = 0x00, - .self = 0x0000, - .config = 0x00, - .fuses = 0x00, - .activation_key = 0x00000000, - }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, - .voltage = { - .vcc_min = 1800, - .vcc_max = 3600, - .vcc_flash_min = 1800, - .vcc_secure_min = 2500, - .vpp_secure_min = 6000, - .vpp_secure_max = 7000, - .has_test_vpp = 1, - }, - .v3_functions = { - [0x09] = 0x38, - [0x11] = 0x39, - [0x12] = 0x3a, - [0x13] = 0x3b, - [0x14] = 0x3c, - [0x15] = 0x3c, - [0x16] = 0x3d, - [0x17] = 0x3e, - [0x18] = 0x3e, - [0x19] = 0x3f, - [0x1b] = 0x40, - [0x1c] = 0x41, - [0x1d] = 0x42, - [0x1e] = 0x43, - [0x1f] = 0x44, - [0x25] = 0x36, - }, - .v3_erase = &erase_xv2_fram, - .v3_write = &write_xv2_fram, - .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, - .features = 0 - | CHIPINFO_FEATURE_LCFE - | CHIPINFO_FEATURE_QUICK_MEM_READ - | CHIPINFO_FEATURE_FRAM, - .power = { - .reg_mask = 0x10018, - .enable_lpm5 = 0x10000, - .disable_lpm5 = 0x10000, - .reg_mask_3v = 0x0c020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, - }, - .memory = { - { - .name = "main", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 97280, - .offset = 0x04400, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "information", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 128, - .offset = 0x03c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "peripheral16bit", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 16, - .mapped = 1, - .size = 4096, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - {0} - }, - }, - - { - .name = "MSP430FR5979", - .bits = 20, - .psa = CHIPINFO_PSA_REGULAR, - .clock_control = 0x02, - .mclk_control = 0xbdff, - .clock_map = { - {"Timer1_A2", 0x06}, - {0}, - {"AES128", 0x04}, - {"Comparator D", 0x2b}, - {"ADC12B", 0x38}, - {"RTC", 0x28}, - {0}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"Timer0_B7", 0x1c}, - {"Timer0_A3", 0x08}, - {"Timer1_A3", 0x09}, - {"Timer2_A3", 0x0a}, - {"Timer0_A2", 0x05}, - {"Watchdog Timer", 0x01}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - {0}, - }, - .id = { - .ver_id = 0x81b1, - .ver_sub_id = 0x0000, - .revision = 0x00, - .fab = 0x00, - .self = 0x0000, - .config = 0x00, - .fuses = 0x00, - .activation_key = 0x00000000, - }, - .id_mask = { - .ver_id = 0xffff, - .ver_sub_id = 0xffff, - .revision = 0x00, - .fab = 0x00, - .self = 0x0000, - .config = 0x00, - .fuses = 0x00, - .activation_key = 0x00000000, - }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, - .voltage = { - .vcc_min = 1800, - .vcc_max = 3600, - .vcc_flash_min = 1800, - .vcc_secure_min = 2500, - .vpp_secure_min = 6000, - .vpp_secure_max = 7000, - .has_test_vpp = 1, - }, - .v3_functions = { - [0x09] = 0x38, - [0x11] = 0x39, - [0x12] = 0x3a, - [0x13] = 0x3b, - [0x14] = 0x3c, - [0x15] = 0x3c, - [0x16] = 0x3d, - [0x17] = 0x3e, - [0x18] = 0x3e, - [0x19] = 0x3f, - [0x1b] = 0x40, - [0x1c] = 0x41, - [0x1d] = 0x42, - [0x1e] = 0x43, - [0x1f] = 0x44, - [0x25] = 0x36, - }, - .v3_erase = &erase_xv2_fram, - .v3_write = &write_xv2_fram, - .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, - .features = 0 - | CHIPINFO_FEATURE_LCFE - | CHIPINFO_FEATURE_QUICK_MEM_READ - | CHIPINFO_FEATURE_FRAM, - .power = { - .reg_mask = 0x10018, - .enable_lpm5 = 0x10000, - .disable_lpm5 = 0x10000, - .reg_mask_3v = 0x0c020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, - }, - .memory = { - { - .name = "main", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 130048, - .offset = 0x04400, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "information", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 128, - .offset = 0x03c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "peripheral16bit", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 16, - .mapped = 1, - .size = 4096, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - {0} - }, - }, - - { - .name = "MSP430FR6928", - .bits = 20, - .psa = CHIPINFO_PSA_REGULAR, - .clock_control = 0x02, - .mclk_control = 0xbdff, - .clock_map = { - {"Timer1_A2", 0x06}, - {"LCDB", 0x2c}, - {"AES128", 0x04}, - {"Comparator D", 0x2b}, - {"ADC12B", 0x38}, - {"RTC", 0x28}, - {0}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"Timer0_B7", 0x1c}, - {"Timer0_A3", 0x08}, - {"Timer1_A3", 0x09}, - {"Timer2_A3", 0x0a}, - {"Timer0_A2", 0x05}, - {"Watchdog Timer", 0x01}, {0}, {0}, {0}, @@ -72668,174 +63425,48 @@ const struct chipinfo chipinfo_db[] = { { .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, - .revision = 0x00, + .revision = 0xff, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, - .vcc_flash_min = 1800, + .vcc_flash_min = 2700, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, - .has_test_vpp = 1, + .has_test_vpp = 0, }, .v3_functions = { - [0x09] = 0x38, - [0x11] = 0x39, - [0x12] = 0x3a, - [0x13] = 0x3b, - [0x14] = 0x3c, - [0x15] = 0x3c, - [0x16] = 0x3d, - [0x17] = 0x3e, - [0x18] = 0x3e, - [0x19] = 0x3f, - [0x1b] = 0x40, - [0x1c] = 0x41, - [0x1d] = 0x42, - [0x1e] = 0x43, - [0x1f] = 0x44, - [0x25] = 0x36, }, - .v3_erase = &erase_xv2_fram, - .v3_write = &write_xv2_fram, - .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ - | CHIPINFO_FEATURE_FRAM, + | CHIPINFO_FEATURE_NO_BSL, .power = { - .reg_mask = 0x10018, - .enable_lpm5 = 0x10000, - .disable_lpm5 = 0x10000, - .reg_mask_3v = 0x0c020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", - .type = CHIPINFO_MEMTYPE_RAM, + .name = "None", + .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, - .size = 97280, - .offset = 0x04400, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "information", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 128, - .offset = 0x03c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "peripheral16bit", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 16, - .mapped = 1, - .size = 4096, + .size = 0, .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .seg_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -72843,28 +63474,28 @@ const struct chipinfo chipinfo_db[] = { { }, { - .name = "MSP430FR6929", + .name = "MSP430FR6928", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0xbdff, + .mclk_control = 0x0000043f, .clock_map = { - {"Timer1_A2", 0x06}, - {"LCDB", 0x2c}, - {"AES128", 0x04}, - {"Comparator D", 0x2b}, - {"ADC12B", 0x38}, - {"RTC", 0x28}, + {"PORT", 0x50}, + {"LCDC", 0xb0}, {0}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"Timer0_B7", 0x1c}, - {"Timer0_A3", 0x08}, - {"Timer1_A3", 0x09}, - {"Timer2_A3", 0x0a}, - {"Timer0_A2", 0x05}, - {"Watchdog Timer", 0x01}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {"eUSCIB1", 0x31}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -72883,9 +63514,9 @@ const struct chipinfo chipinfo_db[] = { { {0}, }, .id = { - .ver_id = 0x81b4, + .ver_id = 0x81b3, .ver_sub_id = 0x0000, - .revision = 0x00, + .revision = 0x21, .fab = 0x00, .self = 0x0000, .config = 0x00, @@ -72895,34 +63526,14 @@ const struct chipinfo chipinfo_db[] = { { .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, - .revision = 0x00, + .revision = 0xff, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -72933,22 +63544,23 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x38, - [0x11] = 0x39, + [0x09] = 0x39, + [0x0a] = 0x4a, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, - [0x1c] = 0x41, + [0x1a] = 0x40, + [0x1c] = 0x50, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, + [0x20] = 0x45, + [0x26] = 0x37, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, @@ -72959,110 +63571,99 @@ const struct chipinfo chipinfo_db[] = { { | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, - .enable_lpm5 = 0x10000, + .enable_lpm5 = 0x10018, .disable_lpm5 = 0x10000, - .reg_mask_3v = 0x0c020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, - .size = 130048, + .size = 97280, .offset = 0x04400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "system", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, - .size = 128, - .offset = 0x03c00, + .size = 512, + .offset = 0x01800, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, - .size = 4096, - .offset = 0x00000, + .size = 4064, + .offset = 0x00020, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "EEM", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, + .bits = 16, + .mapped = 1, + .size = 6, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -73070,28 +63671,28 @@ const struct chipinfo chipinfo_db[] = { { }, { - .name = "MSP430FR6887", + .name = "Legacy", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, - .clock_control = 0x02, - .mclk_control = 0xbdff, + .clock_control = 0x00, + .mclk_control = 0x00000000, .clock_map = { - {"Timer1_A2", 0x06}, - {"LCDB", 0x2c}, {0}, - {"Comparator D", 0x2b}, - {"ADC12B", 0x38}, - {"RTC", 0x28}, {0}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"Timer0_B7", 0x1c}, - {"Timer0_A3", 0x08}, - {"Timer1_A3", 0x09}, - {"Timer2_A3", 0x0a}, - {"Timer0_A2", 0x05}, - {"Watchdog Timer", 0x01}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, {0}, {0}, {0}, @@ -73122,34 +63723,115 @@ const struct chipinfo chipinfo_db[] = { { .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, - .revision = 0x00, + .revision = 0xff, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 2700, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 0, }, + .v3_functions = { + }, + .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_NO_BSL, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "None", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 0, + .offset = 0x00000, + .seg_size = 0, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR6887", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x0000043f, + .clock_map = { + {"PORT", 0x50}, + {"LCDC", 0xb0}, + {0}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {"eUSCIB1", 0x31}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A5", 0x91}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x81be, + .ver_sub_id = 0x0000, + .revision = 0x21, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -73160,22 +63842,23 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x38, - [0x11] = 0x39, + [0x09] = 0x39, + [0x0a] = 0x4a, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, - [0x1c] = 0x41, + [0x1a] = 0x40, + [0x1c] = 0x50, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, + [0x20] = 0x45, + [0x26] = 0x37, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, @@ -73186,110 +63869,99 @@ const struct chipinfo chipinfo_db[] = { { | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, - .enable_lpm5 = 0x10000, + .enable_lpm5 = 0x10018, .disable_lpm5 = 0x10000, - .reg_mask_3v = 0x0c020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 64512, .offset = 0x04400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "system", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, - .size = 128, - .offset = 0x03c00, + .size = 512, + .offset = 0x01800, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, - .size = 4096, - .offset = 0x00000, + .size = 4064, + .offset = 0x00020, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "EEM", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, + .bits = 16, + .mapped = 1, + .size = 6, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -73297,28 +63969,28 @@ const struct chipinfo chipinfo_db[] = { { }, { - .name = "MSP430FR6888", + .name = "Legacy", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, - .clock_control = 0x02, - .mclk_control = 0xbdff, + .clock_control = 0x00, + .mclk_control = 0x00000000, .clock_map = { - {"Timer1_A2", 0x06}, - {"LCDB", 0x2c}, {0}, - {"Comparator D", 0x2b}, - {"ADC12B", 0x38}, - {"RTC", 0x28}, {0}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"Timer0_B7", 0x1c}, - {"Timer0_A3", 0x08}, - {"Timer1_A3", 0x09}, - {"Timer2_A3", 0x0a}, - {"Timer0_A2", 0x05}, - {"Watchdog Timer", 0x01}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, {0}, {0}, {0}, @@ -73349,34 +64021,115 @@ const struct chipinfo chipinfo_db[] = { { .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, - .revision = 0x00, + .revision = 0xff, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 2700, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 0, }, + .v3_functions = { + }, + .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_NO_BSL, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "None", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 0, + .offset = 0x00000, + .seg_size = 0, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR6888", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x0000043f, + .clock_map = { + {"PORT", 0x50}, + {"LCDC", 0xb0}, + {0}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {"eUSCIB1", 0x31}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A5", 0x91}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x81bf, + .ver_sub_id = 0x0000, + .revision = 0x21, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -73387,22 +64140,23 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x38, - [0x11] = 0x39, + [0x09] = 0x39, + [0x0a] = 0x4a, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, - [0x1c] = 0x41, + [0x1a] = 0x40, + [0x1c] = 0x50, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, + [0x20] = 0x45, + [0x26] = 0x37, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, @@ -73413,110 +64167,99 @@ const struct chipinfo chipinfo_db[] = { { | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, - .enable_lpm5 = 0x10000, + .enable_lpm5 = 0x10018, .disable_lpm5 = 0x10000, - .reg_mask_3v = 0x0c020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 97280, .offset = 0x04400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "system", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, - .size = 128, - .offset = 0x03c00, + .size = 512, + .offset = 0x01800, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, - .size = 4096, - .offset = 0x00000, + .size = 4064, + .offset = 0x00020, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "EEM", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, + .bits = 16, + .mapped = 1, + .size = 6, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -73524,28 +64267,28 @@ const struct chipinfo chipinfo_db[] = { { }, { - .name = "MSP430FR6889", + .name = "Legacy", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, - .clock_control = 0x02, - .mclk_control = 0xbdff, + .clock_control = 0x00, + .mclk_control = 0x00000000, .clock_map = { - {"Timer1_A2", 0x06}, - {"LCDB", 0x2c}, {0}, - {"Comparator D", 0x2b}, - {"ADC12B", 0x38}, - {"RTC", 0x28}, {0}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"Timer0_B7", 0x1c}, - {"Timer0_A3", 0x08}, - {"Timer1_A3", 0x09}, - {"Timer2_A3", 0x0a}, - {"Timer0_A2", 0x05}, - {"Watchdog Timer", 0x01}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, {0}, {0}, {0}, @@ -73576,34 +64319,115 @@ const struct chipinfo chipinfo_db[] = { { .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, - .revision = 0x00, + .revision = 0xff, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 2700, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 0, }, + .v3_functions = { + }, + .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_NO_BSL, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "None", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 0, + .offset = 0x00000, + .seg_size = 0, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR6889", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x0000043f, + .clock_map = { + {"PORT", 0x50}, + {"LCDC", 0xb0}, + {0}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {"eUSCIB1", 0x31}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A5", 0x91}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x81c0, + .ver_sub_id = 0x0000, + .revision = 0x21, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -73614,22 +64438,23 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x38, - [0x11] = 0x39, + [0x09] = 0x39, + [0x0a] = 0x4a, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, - [0x1c] = 0x41, + [0x1a] = 0x40, + [0x1c] = 0x50, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, + [0x20] = 0x45, + [0x26] = 0x37, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, @@ -73640,110 +64465,99 @@ const struct chipinfo chipinfo_db[] = { { | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, - .enable_lpm5 = 0x10000, + .enable_lpm5 = 0x10018, .disable_lpm5 = 0x10000, - .reg_mask_3v = 0x0c020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 130048, .offset = 0x04400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "system", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, - .size = 128, - .offset = 0x03c00, + .size = 512, + .offset = 0x01800, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, - .size = 4096, - .offset = 0x00000, + .size = 4064, + .offset = 0x00020, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "EEM", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, + .bits = 16, + .mapped = 1, + .size = 6, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -73751,28 +64565,326 @@ const struct chipinfo chipinfo_db[] = { { }, { - .name = "MSP430FR5888", + .name = "Legacy", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x00, + .mclk_control = 0x00000000, + .clock_map = { + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x81c1, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 2700, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 0, + }, + .v3_functions = { + }, + .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_NO_BSL, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "None", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 0, + .offset = 0x00000, + .seg_size = 0, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR5887", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0xbdff, + .mclk_control = 0x0000043f, .clock_map = { - {"Timer1_A2", 0x06}, + {"PORT", 0x50}, + {0}, + {0}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {"eUSCIB1", 0x31}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A5", 0x91}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x81c1, + .ver_sub_id = 0x0000, + .revision = 0x21, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 64512, + .offset = 0x04400, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4064, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 6, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "Legacy", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x00, + .mclk_control = 0x00000000, + .clock_map = { + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, {0}, {0}, - {"Comparator D", 0x2b}, - {"ADC12B", 0x38}, - {"RTC", 0x28}, {0}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"Timer0_B7", 0x1c}, - {"Timer0_A3", 0x08}, - {"Timer1_A3", 0x09}, - {"Timer2_A3", 0x0a}, - {"Timer0_A2", 0x05}, - {"Watchdog Timer", 0x01}, {0}, {0}, {0}, @@ -73803,34 +64915,115 @@ const struct chipinfo chipinfo_db[] = { { .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, - .revision = 0x00, + .revision = 0xff, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 2700, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 0, }, + .v3_functions = { + }, + .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_NO_BSL, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "None", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 0, + .offset = 0x00000, + .seg_size = 0, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR5888", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x0000043f, + .clock_map = { + {"PORT", 0x50}, + {0}, + {0}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {"eUSCIB1", 0x31}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A5", 0x91}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x81c2, + .ver_sub_id = 0x0000, + .revision = 0x21, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -73841,22 +65034,23 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x38, - [0x11] = 0x39, + [0x09] = 0x39, + [0x0a] = 0x4a, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, - [0x1c] = 0x41, + [0x1a] = 0x40, + [0x1c] = 0x50, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, + [0x20] = 0x45, + [0x26] = 0x37, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, @@ -73867,110 +65061,99 @@ const struct chipinfo chipinfo_db[] = { { | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, - .enable_lpm5 = 0x10000, + .enable_lpm5 = 0x10018, .disable_lpm5 = 0x10000, - .reg_mask_3v = 0x0c020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 97280, .offset = 0x04400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "system", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, - .size = 128, - .offset = 0x03c00, + .size = 512, + .offset = 0x01800, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, - .size = 4096, - .offset = 0x00000, + .size = 4064, + .offset = 0x00020, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "EEM", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, + .bits = 16, + .mapped = 1, + .size = 6, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -73978,28 +65161,28 @@ const struct chipinfo chipinfo_db[] = { { }, { - .name = "MSP430FR5889", + .name = "Legacy", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, - .clock_control = 0x02, - .mclk_control = 0xbdff, + .clock_control = 0x00, + .mclk_control = 0x00000000, .clock_map = { - {"Timer1_A2", 0x06}, {0}, {0}, - {"Comparator D", 0x2b}, - {"ADC12B", 0x38}, - {"RTC", 0x28}, {0}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"Timer0_B7", 0x1c}, - {"Timer0_A3", 0x08}, - {"Timer1_A3", 0x09}, - {"Timer2_A3", 0x0a}, - {"Timer0_A2", 0x05}, - {"Watchdog Timer", 0x01}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, {0}, {0}, {0}, @@ -74030,174 +65213,48 @@ const struct chipinfo chipinfo_db[] = { { .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, - .revision = 0x00, + .revision = 0xff, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, - .vcc_flash_min = 1800, + .vcc_flash_min = 2700, .vcc_secure_min = 2500, .vpp_secure_min = 6000, .vpp_secure_max = 7000, - .has_test_vpp = 1, + .has_test_vpp = 0, }, .v3_functions = { - [0x09] = 0x38, - [0x11] = 0x39, - [0x12] = 0x3a, - [0x13] = 0x3b, - [0x14] = 0x3c, - [0x15] = 0x3c, - [0x16] = 0x3d, - [0x17] = 0x3e, - [0x18] = 0x3e, - [0x19] = 0x3f, - [0x1b] = 0x40, - [0x1c] = 0x41, - [0x1d] = 0x42, - [0x1e] = 0x43, - [0x1f] = 0x44, - [0x25] = 0x36, }, - .v3_erase = &erase_xv2_fram, - .v3_write = &write_xv2_fram, - .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ - | CHIPINFO_FEATURE_FRAM, + | CHIPINFO_FEATURE_NO_BSL, .power = { - .reg_mask = 0x10018, - .enable_lpm5 = 0x10000, - .disable_lpm5 = 0x10000, - .reg_mask_3v = 0x0c020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", - .type = CHIPINFO_MEMTYPE_RAM, + .name = "None", + .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, - .size = 130048, - .offset = 0x04400, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "information", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 128, - .offset = 0x03c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "peripheral16bit", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 16, - .mapped = 1, - .size = 4096, + .size = 0, .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .seg_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -74205,28 +65262,28 @@ const struct chipinfo chipinfo_db[] = { { }, { - .name = "MSP430FR5878", + .name = "MSP430FR5889", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0xbdff, + .mclk_control = 0x0000043f, .clock_map = { - {"Timer1_A2", 0x06}, + {"PORT", 0x50}, {0}, {0}, - {"Comparator D", 0x2b}, - {"ADC12B", 0x38}, - {"RTC", 0x28}, - {0}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"Timer0_B7", 0x1c}, - {"Timer0_A3", 0x08}, - {"Timer1_A3", 0x09}, - {"Timer2_A3", 0x0a}, - {"Timer0_A2", 0x05}, - {"Watchdog Timer", 0x01}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {"eUSCIB1", 0x31}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -74245,9 +65302,9 @@ const struct chipinfo chipinfo_db[] = { { {0}, }, .id = { - .ver_id = 0x81c8, + .ver_id = 0x81c3, .ver_sub_id = 0x0000, - .revision = 0x00, + .revision = 0x21, .fab = 0x00, .self = 0x0000, .config = 0x00, @@ -74257,34 +65314,14 @@ const struct chipinfo chipinfo_db[] = { { .id_mask = { .ver_id = 0xffff, .ver_sub_id = 0xffff, - .revision = 0x00, + .revision = 0xff, .fab = 0x00, .self = 0x0000, .config = 0x00, .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -74295,22 +65332,23 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x38, - [0x11] = 0x39, + [0x09] = 0x39, + [0x0a] = 0x4a, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, - [0x1c] = 0x41, + [0x1a] = 0x40, + [0x1c] = 0x50, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, + [0x20] = 0x45, + [0x26] = 0x37, }, .v3_erase = &erase_xv2_fram, .v3_write = &write_xv2_fram, @@ -74321,110 +65359,99 @@ const struct chipinfo chipinfo_db[] = { { | CHIPINFO_FEATURE_FRAM, .power = { .reg_mask = 0x10018, - .enable_lpm5 = 0x10000, + .enable_lpm5 = 0x10018, .disable_lpm5 = 0x10000, - .reg_mask_3v = 0x0c020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, - .size = 97280, + .size = 130048, .offset = 0x04400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 2048, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "system", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, - .size = 128, - .offset = 0x03c00, + .size = 512, + .offset = 0x01800, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, - .size = 4096, - .offset = 0x00000, + .size = 4064, + .offset = 0x00020, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "EEM", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, + .bits = 16, + .mapped = 1, + .size = 6, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -74432,28 +65459,28 @@ const struct chipinfo chipinfo_db[] = { { }, { - .name = "MSP430FR5879", + .name = "Legacy", .bits = 20, .psa = CHIPINFO_PSA_REGULAR, - .clock_control = 0x02, - .mclk_control = 0xbdff, + .clock_control = 0x00, + .mclk_control = 0x00000000, .clock_map = { - {"Timer1_A2", 0x06}, {0}, {0}, - {"Comparator D", 0x2b}, - {"ADC12B", 0x38}, - {"RTC", 0x28}, {0}, - {"eUSCIB0", 0x27}, - {"eUSCIA1", 0x24}, - {"eUSCIA0", 0x23}, - {"Timer0_B7", 0x1c}, - {"Timer0_A3", 0x08}, - {"Timer1_A3", 0x09}, - {"Timer2_A3", 0x0a}, - {"Timer0_A2", 0x05}, - {"Watchdog Timer", 0x01}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, {0}, {0}, {0}, @@ -74472,7 +65499,1240 @@ const struct chipinfo chipinfo_db[] = { { {0}, }, .id = { - .ver_id = 0x81c9, + .ver_id = 0x81c4, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 2700, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 0, + }, + .v3_functions = { + }, + .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_NO_BSL, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "None", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 0, + .offset = 0x00000, + .seg_size = 0, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR6877", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x0000043f, + .clock_map = { + {"PORT", 0x50}, + {"LCDC", 0xb0}, + {0}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {"eUSCIB1", 0x31}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A5", 0x91}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x81c4, + .ver_sub_id = 0x0000, + .revision = 0x21, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 64512, + .offset = 0x04400, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4064, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 6, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "Legacy", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x00, + .mclk_control = 0x00000000, + .clock_map = { + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x81c6, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 2700, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 0, + }, + .v3_functions = { + }, + .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_NO_BSL, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "None", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 0, + .offset = 0x00000, + .seg_size = 0, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR6879", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x0000043f, + .clock_map = { + {"PORT", 0x50}, + {"LCDC", 0xb0}, + {0}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {"eUSCIB1", 0x31}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A5", 0x91}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x81c6, + .ver_sub_id = 0x0000, + .revision = 0x21, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 130048, + .offset = 0x04400, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4064, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 6, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "Legacy", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x00, + .mclk_control = 0x00000000, + .clock_map = { + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x81df, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 2700, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 0, + }, + .v3_functions = { + }, + .clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_NO_BSL, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "None", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 0, + .offset = 0x00000, + .seg_size = 0, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR5986", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x0000043f, + .clock_map = { + {"PORT", 0x50}, + {0}, + {0}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {"eUSCIB1", 0x31}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A5", 0x91}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x81df, + .ver_sub_id = 0x0000, + .revision = 0x21, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 48128, + .offset = 0x04400, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4064, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 6, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "RF430FRL152H", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x00000005, + .clock_map = { + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {"RF13M", 0xbb}, + {"APOOL", 0xb5}, + {"eUSCIB0", 0x30}, + {"RFSD14", 0xd9}, + {0}, + {"Timer0_A3", 0x8e}, + {0}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x81e7, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x5aa55aa5, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0xffffffff, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1450, + .vcc_max = 1650, + .vcc_flash_min = 0, + .vcc_secure_min = 0, + .vpp_secure_min = 0, + .vpp_secure_max = 0, + .has_test_vpp = 0, + }, + .v3_functions = { + [0x09] = 0x39, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, + .features = 0 + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM + | CHIPINFO_FEATURE_NO_BSL, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 1984, + .offset = 0x0f840, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode2", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 3584, + .offset = 0x04400, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram2", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 3584, + .offset = 0x01e00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 64, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "RF430FRL152H", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x00000005, + .clock_map = { + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {"RF13M", 0xbb}, + {"APOOL", 0xb5}, + {"eUSCIB0", 0x30}, + {"RFSD14", 0xd9}, + {0}, + {"Timer0_A3", 0x8e}, + {0}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x81e7, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0xa55aa55a, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0xffffffff, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1450, + .vcc_max = 1650, + .vcc_flash_min = 0, + .vcc_secure_min = 0, + .vpp_secure_min = 0, + .vpp_secure_max = 0, + .has_test_vpp = 0, + }, + .v3_functions = { + [0x09] = 0x39, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, + .features = 0 + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM + | CHIPINFO_FEATURE_NO_BSL, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 1984, + .offset = 0x0f840, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode2", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 7168, + .offset = 0x04400, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 64, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "RF430F5144", + .bits = 20, + .psa = CHIPINFO_PSA_ENHANCED, + .clock_control = 0x02, + .mclk_control = 0x0000041d, + .clock_map = { + {0}, + {0}, + {0}, + {"Comparator B", 0xa8}, + {0}, + {"RTC", 0x8a}, + {0}, + {0}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {0}, + {"Timer1_D3", 0x75}, + {"Timer0_D3", 0x74}, + {"Timer0_A3", 0x8e}, + {0}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x81e9, .ver_sub_id = 0x0000, .revision = 0x00, .fab = 0x00, @@ -74491,27 +66751,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -74523,135 +66763,453 @@ const struct chipinfo chipinfo_db[] = { { }, .v3_functions = { [0x09] = 0x38, - [0x11] = 0x39, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, - .v3_erase = &erase_xv2_fram, - .v3_write = &write_xv2_fram, + .v3_erase = &erase_xv2, + .v3_write = &write_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE | CHIPINFO_FEATURE_QUICK_MEM_READ - | CHIPINFO_FEATURE_FRAM, + | CHIPINFO_FEATURE_1337, .power = { - .reg_mask = 0x10018, - .enable_lpm5 = 0x10000, - .disable_lpm5 = 0x10000, - .reg_mask_3v = 0x0c020, - .enable_lpm5_3v = 0x04020, - .disable_lpm5_3v = 0x04020, + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, }, .memory = { { - .name = "main", + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 16384, + .offset = 0x0c000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, - .size = 130048, - .offset = 0x04400, + .size = 1024, + .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "bootcode", + .name = "BootCode", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 256, .offset = 0x01a00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 2048, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, }, { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 128, - .offset = 0x03c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "peripheral16bit", + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "RF430F5155", + .bits = 20, + .psa = CHIPINFO_PSA_ENHANCED, + .clock_control = 0x02, + .mclk_control = 0x0000041d, + .clock_map = { + {0}, + {0}, + {0}, + {"Comparator B", 0xa8}, + {0}, + {"RTC", 0x8a}, + {0}, + {0}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {0}, + {"Timer1_D3", 0x75}, + {"Timer0_D3", 0x74}, + {"Timer0_A3", 0x8e}, + {0}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x81ea, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x38, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2, + .v3_write = &write_xv2, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_1337, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 16384, + .offset = 0x0c000, + .seg_size = 512, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "EEM", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, + .bits = 16, + .mapped = 1, + .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "RF430F5175", + .bits = 20, + .psa = CHIPINFO_PSA_ENHANCED, + .clock_control = 0x02, + .mclk_control = 0x0000041d, + .clock_map = { + {0}, + {0}, + {0}, + {"Comparator B", 0xa8}, + {0}, + {"RTC", 0x8a}, + {0}, + {0}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {0}, + {"Timer1_D3", 0x75}, + {"Timer0_D3", 0x74}, + {"Timer0_A3", 0x8e}, + {0}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x81eb, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x38, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2, + .v3_write = &write_xv2, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_1337, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 32768, + .offset = 0x08000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -74663,24 +67221,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x040f, + .mclk_control = 0x0000040f, .clock_map = { {0}, {0}, {0}, {0}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -74718,27 +67276,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x08, - .cycle_counter = 0x02, - .cycle_counter_ops = 0x01, - .trig_emulation_level = 0x07, - .trig_mem = 0x08, - .trig_reg = 0x02, - .trig_combinations = 0x0a, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x02, - .trig_mem_umask_level = 0x01, - .seq_states = 0x03, - .seq_start = 0x04, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -74749,27 +67287,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -74785,91 +67322,597 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 262144, .offset = 0x05c00, .seg_size = 512, - .bank_size = 65536, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x01c00, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR4133", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x00000407, + .clock_map = { + {"PORT", 0x50}, + {"LCDE", 0xb0}, + {0}, + {0}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {0}, + {"eUSCIB0", 0x30}, + {0}, + {"eUSCIA0", 0x2c}, + {0}, + {0}, + {0}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x81f0, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + [0x4e] = 0x3f, + }, + .v3_erase = &erase_xv2_fr41xx, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x00018, + .disable_lpm5 = 0x00018, + .reg_mask_3v = 0x04020, + .enable_lpm5_3v = 0x04020, + .disable_lpm5_3v = 0x04020, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 15360, + .offset = 0x0c400, + .seg_size = 1, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x02000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "EEM", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, + .bits = 16, + .mapped = 1, + .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR4132", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x00000407, + .clock_map = { + {"PORT", 0x50}, + {"LCDE", 0xb0}, + {0}, + {0}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {0}, + {"eUSCIB0", 0x30}, + {0}, + {"eUSCIA0", 0x2c}, + {0}, + {0}, + {0}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x81f1, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + [0x4e] = 0x3f, + }, + .v3_erase = &erase_xv2_fr41xx, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x00018, + .disable_lpm5 = 0x00018, + .reg_mask_3v = 0x04020, + .enable_lpm5_3v = 0x04020, + .disable_lpm5_3v = 0x04020, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 8192, + .offset = 0x0e000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x02000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR4131", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x00000407, + .clock_map = { + {"PORT", 0x50}, + {"LCDE", 0xb0}, + {0}, + {0}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {0}, + {"eUSCIB0", 0x30}, + {0}, + {"eUSCIA0", 0x2c}, + {0}, + {0}, + {0}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x81f2, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + [0x4e] = 0x3f, + }, + .v3_erase = &erase_xv2_fr41xx, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x00018, + .disable_lpm5 = 0x00018, + .reg_mask_3v = 0x04020, + .enable_lpm5_3v = 0x04020, + .disable_lpm5_3v = 0x04020, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x0f000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x02000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -74881,24 +67924,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -74936,27 +67979,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -74967,27 +67990,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -75003,91 +68025,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x04400, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -75099,24 +68099,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -75154,27 +68154,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -75185,27 +68165,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -75221,91 +68200,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 65536, .offset = 0x04400, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -75317,24 +68274,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -75372,27 +68329,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -75403,27 +68340,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -75439,91 +68375,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x04400, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -75535,24 +68449,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -75590,27 +68504,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -75621,27 +68515,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -75657,91 +68550,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 65536, .offset = 0x04400, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -75753,24 +68624,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, + {"Comparator B", 0xa8}, {0}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -75808,27 +68679,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -75839,27 +68690,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -75875,91 +68725,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x04400, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -75971,24 +68799,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, + {"Comparator B", 0xa8}, {0}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -76026,27 +68854,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -76057,27 +68865,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -76093,91 +68900,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 65536, .offset = 0x04400, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -76189,24 +68974,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, + {"Comparator B", 0xa8}, {0}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -76244,27 +69029,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -76275,27 +69040,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -76311,91 +69075,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x04400, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -76407,24 +69149,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, + {"Comparator B", 0xa8}, {0}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -76462,27 +69204,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -76493,27 +69215,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -76529,91 +69250,747 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 65536, .offset = 0x04400, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 2, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 8192, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "RF430FRL153H", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x00000005, + .clock_map = { + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {"RF13M", 0xbb}, + {"APOOL", 0xb5}, + {0}, + {"RFSD14", 0xd9}, + {0}, + {"Timer0_A3", 0x8e}, + {0}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x81fb, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x5aa55aa5, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0xffffffff, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1450, + .vcc_max = 1650, + .vcc_flash_min = 0, + .vcc_secure_min = 0, + .vpp_secure_min = 0, + .vpp_secure_max = 0, + .has_test_vpp = 0, + }, + .v3_functions = { + [0x09] = 0x39, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, + .features = 0 + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM + | CHIPINFO_FEATURE_NO_BSL, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 1984, + .offset = 0x0f840, + .seg_size = 1, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, + .name = "BootCode2", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 3584, + .offset = 0x04400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "EEM", + .name = "Ram2", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 3584, + .offset = 0x01e00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 64, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, + .bits = 16, + .mapped = 1, + .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "RF430FRL153H", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x00000005, + .clock_map = { + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {"RF13M", 0xbb}, + {"APOOL", 0xb5}, + {0}, + {"RFSD14", 0xd9}, + {0}, + {"Timer0_A3", 0x8e}, + {0}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x81fb, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0xa55aa55a, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0xffffffff, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1450, + .vcc_max = 1650, + .vcc_flash_min = 0, + .vcc_secure_min = 0, + .vpp_secure_min = 0, + .vpp_secure_max = 0, + .has_test_vpp = 0, + }, + .v3_functions = { + [0x09] = 0x39, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, + .features = 0 + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM + | CHIPINFO_FEATURE_NO_BSL, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 1984, + .offset = 0x0f840, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode2", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 7168, + .offset = 0x04400, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 64, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "RF430FRL154H", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x00000005, + .clock_map = { + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {"RF13M", 0xbb}, + {"APOOL", 0xb5}, + {"eUSCIB0", 0x30}, + {0}, + {0}, + {"Timer0_A3", 0x8e}, + {0}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x81fc, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x5aa55aa5, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0xffffffff, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1450, + .vcc_max = 1650, + .vcc_flash_min = 0, + .vcc_secure_min = 0, + .vpp_secure_min = 0, + .vpp_secure_max = 0, + .has_test_vpp = 0, + }, + .v3_functions = { + [0x09] = 0x39, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, + .features = 0 + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM + | CHIPINFO_FEATURE_NO_BSL, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 1984, + .offset = 0x0f840, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode2", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 3584, + .offset = 0x04400, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram2", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 3584, + .offset = 0x01e00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 64, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "RF430FRL154H", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x00000005, + .clock_map = { + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {"RF13M", 0xbb}, + {"APOOL", 0xb5}, + {"eUSCIB0", 0x30}, + {0}, + {0}, + {"Timer0_A3", 0x8e}, + {0}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x81fc, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0xa55aa55a, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0xffffffff, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1450, + .vcc_max = 1650, + .vcc_flash_min = 0, + .vcc_secure_min = 0, + .vpp_secure_min = 0, + .vpp_secure_max = 0, + .has_test_vpp = 0, + }, + .v3_functions = { + [0x09] = 0x39, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, + .features = 0 + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM + | CHIPINFO_FEATURE_NO_BSL, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 1984, + .offset = 0x0f840, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode2", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 7168, + .offset = 0x04400, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 64, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -76625,24 +70002,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -76680,27 +70057,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -76711,27 +70068,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -76747,91 +70103,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x0a400, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -76843,24 +70177,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, + {"Comparator B", 0xa8}, {0}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -76898,27 +70232,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -76929,27 +70243,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -76965,91 +70278,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x0a400, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -77061,24 +70352,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -77116,27 +70407,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -77147,27 +70418,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -77183,91 +70453,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x0a400, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -77279,24 +70527,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, + {"Comparator B", 0xa8}, {0}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -77334,27 +70582,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -77365,27 +70593,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -77401,91 +70628,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x0a400, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -77497,24 +70702,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -77552,27 +70757,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -77583,27 +70768,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -77619,91 +70803,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x0a400, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -77715,24 +70877,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, + {"Comparator B", 0xa8}, {0}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -77770,27 +70932,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -77801,27 +70943,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -77837,91 +70978,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x0a400, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32768, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -77933,24 +71052,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, - {"ADC12A", 0x38}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"Comparator B", 0xa8}, + {"ADC12A", 0xd8}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -77988,27 +71107,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -78019,27 +71118,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -78055,91 +71153,69 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x0a400, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -78151,24 +71227,24 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_ENHANCED, .clock_control = 0x02, - .mclk_control = 0x041f, + .mclk_control = 0x0000041f, .clock_map = { {0}, {0}, {0}, - {"Comparator B", 0x2a}, + {"Comparator B", 0xa8}, {0}, - {"RTC", 0x28}, - {"USCI3", 0x22}, - {"USCI2", 0x21}, - {"USCI1", 0x20}, - {"USCI0", 0x1f}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, {0}, - {"Timer0_B7", 0x1c}, - {"Timer2_A3", 0x3a}, - {"Timer1_A3", 0x39}, - {"Timer0_A5", 0x0c}, - {"Watchdog Timer", 0x01}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -78206,27 +71282,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0x00000000, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x05, - .trig_mem = 0x03, - .trig_reg = 0x01, - .trig_combinations = 0x04, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x01, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 1800, .vcc_max = 3600, @@ -78237,27 +71293,26 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 1, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, .features = 0 | CHIPINFO_FEATURE_LCFE @@ -78273,91 +71328,20778 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", + .name = "Main", .type = CHIPINFO_MEMTYPE_FLASH, .bits = 16, .mapped = 1, .size = 131072, .offset = 0x0a400, .seg_size = 512, - .bank_size = 32768, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "information", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 512, - .offset = 0x01800, - .seg_size = 128, - .bank_size = 128, - .banks = 4, - }, - { - .name = "boot", - .type = CHIPINFO_MEMTYPE_FLASH, - .bits = 16, - .mapped = 1, - .size = 2048, - .offset = 0x01000, - .seg_size = 512, - .bank_size = 0, - .banks = 4, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 256, - .offset = 0x01a00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", + .name = "Ram", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 16384, .offset = 0x02400, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, .banks = 4, }, { - .name = "peripheral16bit", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 16, .mapped = 1, .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430F6745A", + .bits = 20, + .psa = CHIPINFO_PSA_ENHANCED, + .clock_control = 0x02, + .mclk_control = 0x0000841f, + .clock_map = { + {"AES128", 0x60}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8216, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x38, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2, + .v3_write = &write_xv2, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_1337, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 131072, + .offset = 0x0c000, + .seg_size = 512, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "CPU", + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 16384, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, + .bits = 16, + .mapped = 1, + .size = 4096, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430F6746A", + .bits = 20, + .psa = CHIPINFO_PSA_ENHANCED, + .clock_control = 0x02, + .mclk_control = 0x0000841f, + .clock_map = { + {"AES128", 0x60}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8217, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x38, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2, + .v3_write = &write_xv2, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_1337, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 262144, + .offset = 0x0c000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 2, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 16384, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, .banks = 1, }, { - .name = "EEM", + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430F6747A", + .bits = 20, + .psa = CHIPINFO_PSA_ENHANCED, + .clock_control = 0x02, + .mclk_control = 0x0000841f, + .clock_map = { + {"AES128", 0x60}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8218, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x38, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2, + .v3_write = &write_xv2, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_1337, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 262144, + .offset = 0x0c000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 2, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 32768, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430F6748A", + .bits = 20, + .psa = CHIPINFO_PSA_ENHANCED, + .clock_control = 0x02, + .mclk_control = 0x0000841f, + .clock_map = { + {"AES128", 0x60}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8219, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x38, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2, + .v3_write = &write_xv2, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_1337, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 524288, + .offset = 0x0c000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 16384, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430F6749A", + .bits = 20, + .psa = CHIPINFO_PSA_ENHANCED, + .clock_control = 0x02, + .mclk_control = 0x0000841f, + .clock_map = { + {"AES128", 0x60}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x821a, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x38, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2, + .v3_write = &write_xv2, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_1337, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 524288, + .offset = 0x0c000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 32768, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430F6765A", + .bits = 20, + .psa = CHIPINFO_PSA_ENHANCED, + .clock_control = 0x02, + .mclk_control = 0x0000841f, + .clock_map = { + {"AES128", 0x60}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x821b, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x38, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2, + .v3_write = &write_xv2, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_1337, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 131072, + .offset = 0x0c000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 16384, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430F6766A", + .bits = 20, + .psa = CHIPINFO_PSA_ENHANCED, + .clock_control = 0x02, + .mclk_control = 0x0000841f, + .clock_map = { + {"AES128", 0x60}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x821c, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x38, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2, + .v3_write = &write_xv2, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_1337, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 262144, + .offset = 0x0c000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 2, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 16384, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430F6767A", + .bits = 20, + .psa = CHIPINFO_PSA_ENHANCED, + .clock_control = 0x02, + .mclk_control = 0x0000841f, + .clock_map = { + {"AES128", 0x60}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x821d, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x38, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2, + .v3_write = &write_xv2, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_1337, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 262144, + .offset = 0x0c000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 2, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 32768, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430F6768A", + .bits = 20, + .psa = CHIPINFO_PSA_ENHANCED, + .clock_control = 0x02, + .mclk_control = 0x0000841f, + .clock_map = { + {"AES128", 0x60}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x821e, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x38, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2, + .v3_write = &write_xv2, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_1337, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 524288, + .offset = 0x0c000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 16384, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430F6769A", + .bits = 20, + .psa = CHIPINFO_PSA_ENHANCED, + .clock_control = 0x02, + .mclk_control = 0x0000841f, + .clock_map = { + {"AES128", 0x60}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x821f, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x38, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2, + .v3_write = &write_xv2, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_1337, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 524288, + .offset = 0x0c000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 32768, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430F6775A", + .bits = 20, + .psa = CHIPINFO_PSA_ENHANCED, + .clock_control = 0x02, + .mclk_control = 0x0000841f, + .clock_map = { + {"AES128", 0x60}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8220, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x38, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2, + .v3_write = &write_xv2, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_1337, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 131072, + .offset = 0x0c000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 16384, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430F6776A", + .bits = 20, + .psa = CHIPINFO_PSA_ENHANCED, + .clock_control = 0x02, + .mclk_control = 0x0000841f, + .clock_map = { + {"AES128", 0x60}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8221, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x38, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2, + .v3_write = &write_xv2, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_1337, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 262144, + .offset = 0x0c000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 2, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 16384, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430F6777A", + .bits = 20, + .psa = CHIPINFO_PSA_ENHANCED, + .clock_control = 0x02, + .mclk_control = 0x0000841f, + .clock_map = { + {"AES128", 0x60}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8222, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x38, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2, + .v3_write = &write_xv2, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_1337, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 262144, + .offset = 0x0c000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 2, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 32768, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430F6778A", + .bits = 20, + .psa = CHIPINFO_PSA_ENHANCED, + .clock_control = 0x02, + .mclk_control = 0x0000841f, + .clock_map = { + {"AES128", 0x60}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8223, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x38, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2, + .v3_write = &write_xv2, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_1337, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 524288, + .offset = 0x0c000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 16384, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430F6779A", + .bits = 20, + .psa = CHIPINFO_PSA_ENHANCED, + .clock_control = 0x02, + .mclk_control = 0x0000841f, + .clock_map = { + {"AES128", 0x60}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8224, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x38, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2, + .v3_write = &write_xv2, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_1337, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 524288, + .offset = 0x0c000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 32768, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430F67451A", + .bits = 20, + .psa = CHIPINFO_PSA_ENHANCED, + .clock_control = 0x02, + .mclk_control = 0x0000041f, + .clock_map = { + {0}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8225, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x38, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2, + .v3_write = &write_xv2, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_1337, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 131072, + .offset = 0x0c000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 16384, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430F67461A", + .bits = 20, + .psa = CHIPINFO_PSA_ENHANCED, + .clock_control = 0x02, + .mclk_control = 0x0000041f, + .clock_map = { + {0}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8226, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x38, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2, + .v3_write = &write_xv2, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_1337, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 262144, + .offset = 0x0c000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 2, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 16384, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430F67471A", + .bits = 20, + .psa = CHIPINFO_PSA_ENHANCED, + .clock_control = 0x02, + .mclk_control = 0x0000041f, + .clock_map = { + {0}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8227, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x38, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2, + .v3_write = &write_xv2, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_1337, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 262144, + .offset = 0x0c000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 2, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 32768, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430F67481A", + .bits = 20, + .psa = CHIPINFO_PSA_ENHANCED, + .clock_control = 0x02, + .mclk_control = 0x0000041f, + .clock_map = { + {0}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8228, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x38, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2, + .v3_write = &write_xv2, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_1337, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 524288, + .offset = 0x0c000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 16384, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430F67491A", + .bits = 20, + .psa = CHIPINFO_PSA_ENHANCED, + .clock_control = 0x02, + .mclk_control = 0x0000041f, + .clock_map = { + {0}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8229, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x38, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2, + .v3_write = &write_xv2, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_1337, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 524288, + .offset = 0x0c000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 32768, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430F67651A", + .bits = 20, + .psa = CHIPINFO_PSA_ENHANCED, + .clock_control = 0x02, + .mclk_control = 0x0000041f, + .clock_map = { + {0}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x822a, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x38, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2, + .v3_write = &write_xv2, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_1337, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 131072, + .offset = 0x0c000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 16384, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430F67661A", + .bits = 20, + .psa = CHIPINFO_PSA_ENHANCED, + .clock_control = 0x02, + .mclk_control = 0x0000041f, + .clock_map = { + {0}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x822b, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x38, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2, + .v3_write = &write_xv2, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_1337, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 262144, + .offset = 0x0c000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 2, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 16384, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430F67671A", + .bits = 20, + .psa = CHIPINFO_PSA_ENHANCED, + .clock_control = 0x02, + .mclk_control = 0x0000041f, + .clock_map = { + {0}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x822c, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x38, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2, + .v3_write = &write_xv2, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_1337, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 262144, + .offset = 0x0c000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 2, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 32768, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430F67681A", + .bits = 20, + .psa = CHIPINFO_PSA_ENHANCED, + .clock_control = 0x02, + .mclk_control = 0x0000041f, + .clock_map = { + {0}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x822d, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x38, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2, + .v3_write = &write_xv2, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_1337, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 524288, + .offset = 0x0c000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 16384, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430F67691A", + .bits = 20, + .psa = CHIPINFO_PSA_ENHANCED, + .clock_control = 0x02, + .mclk_control = 0x0000041f, + .clock_map = { + {0}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x822e, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x38, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2, + .v3_write = &write_xv2, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_1337, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 524288, + .offset = 0x0c000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 32768, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430F67751A", + .bits = 20, + .psa = CHIPINFO_PSA_ENHANCED, + .clock_control = 0x02, + .mclk_control = 0x0000041f, + .clock_map = { + {0}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x822f, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x38, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2, + .v3_write = &write_xv2, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_1337, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 131072, + .offset = 0x0c000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 16384, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430F67761A", + .bits = 20, + .psa = CHIPINFO_PSA_ENHANCED, + .clock_control = 0x02, + .mclk_control = 0x0000041f, + .clock_map = { + {0}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8230, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x38, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2, + .v3_write = &write_xv2, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_1337, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 262144, + .offset = 0x0c000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 2, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 16384, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430F67771A", + .bits = 20, + .psa = CHIPINFO_PSA_ENHANCED, + .clock_control = 0x02, + .mclk_control = 0x0000041f, + .clock_map = { + {0}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8231, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x38, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2, + .v3_write = &write_xv2, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_1337, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 262144, + .offset = 0x0c000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 2, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 32768, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430F67781A", + .bits = 20, + .psa = CHIPINFO_PSA_ENHANCED, + .clock_control = 0x02, + .mclk_control = 0x0000041f, + .clock_map = { + {0}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8232, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x38, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2, + .v3_write = &write_xv2, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_1337, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 524288, + .offset = 0x0c000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 16384, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430F67791A", + .bits = 20, + .psa = CHIPINFO_PSA_ENHANCED, + .clock_control = 0x02, + .mclk_control = 0x0000041f, + .clock_map = { + {0}, + {"eUSCIA3", 0x2f}, + {"eUSCIA2", 0x2e}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"eUSCIB1", 0x31}, + {"Comparator B", 0xa8}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8233, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x38, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2, + .v3_write = &write_xv2, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_1337, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 524288, + .offset = 0x0c000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 32768, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FG6626", + .bits = 20, + .psa = CHIPINFO_PSA_ENHANCED, + .clock_control = 0x02, + .mclk_control = 0x0000041f, + .clock_map = { + {0}, + {"LCDB", 0xb0}, + {"DAC12", 0xc0}, + {"Comparator B", 0xa8}, + {0}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {0}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8234, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x38, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2, + .v3_write = &write_xv2, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_1337, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 131072, + .offset = 0x04400, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 8192, + .offset = 0x02400, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FG6625", + .bits = 20, + .psa = CHIPINFO_PSA_ENHANCED, + .clock_control = 0x02, + .mclk_control = 0x0000041f, + .clock_map = { + {0}, + {"LCDB", 0xb0}, + {"DAC12", 0xc0}, + {"Comparator B", 0xa8}, + {0}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {0}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8235, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x38, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2, + .v3_write = &write_xv2, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_1337, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 65536, + .offset = 0x04400, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 2, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 8192, + .offset = 0x02400, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "UsbRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FG6426", + .bits = 20, + .psa = CHIPINFO_PSA_ENHANCED, + .clock_control = 0x02, + .mclk_control = 0x0000041f, + .clock_map = { + {0}, + {"LCDB", 0xb0}, + {"DAC12", 0xc0}, + {"Comparator B", 0xa8}, + {0}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {0}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8236, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x38, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2, + .v3_write = &write_xv2, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_1337, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 131072, + .offset = 0x04400, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 10240, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FG6425", + .bits = 20, + .psa = CHIPINFO_PSA_ENHANCED, + .clock_control = 0x02, + .mclk_control = 0x0000041f, + .clock_map = { + {0}, + {"LCDB", 0xb0}, + {"DAC12", 0xc0}, + {"Comparator B", 0xa8}, + {0}, + {"RTC", 0x8a}, + {"USCI3", 0x2b}, + {"USCI2", 0x2a}, + {"USCI1", 0x29}, + {"USCI0", 0x28}, + {0}, + {"Timer0_B7", 0x9d}, + {"Timer2_A3", 0x8f}, + {"Timer1_A3", 0x8e}, + {"Timer0_A5", 0x91}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8237, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x38, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2, + .v3_write = &write_xv2, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_1337, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 65536, + .offset = 0x04400, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 2, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 10240, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430F67621", + .bits = 20, + .psa = CHIPINFO_PSA_ENHANCED, + .clock_control = 0x02, + .mclk_control = 0x0000041f, + .clock_map = { + {0}, + {0}, + {0}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {0}, + {0}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8238, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x38, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2, + .v3_write = &write_xv2, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_1337, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 65536, + .offset = 0x04000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 2, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430F67641", + .bits = 20, + .psa = CHIPINFO_PSA_ENHANCED, + .clock_control = 0x02, + .mclk_control = 0x0000041f, + .clock_map = { + {0}, + {0}, + {0}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {0}, + {0}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8239, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x38, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2, + .v3_write = &write_xv2, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_1337, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 131072, + .offset = 0x04000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 8192, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR2633", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x0000041f, + .clock_map = { + {"PORT", 0x50}, + {"Captivate", 0xb7}, + {0}, + {0}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {0}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {0}, + {"Timer2_A2", 0x8b}, + {"Timer3_A2", 0x8c}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x823c, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + [0x4e] = 0x3f, + }, + .v3_erase = &erase_xv2_fr41xx, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x00018, + .disable_lpm5 = 0x00018, + .reg_mask_3v = 0x04020, + .enable_lpm5_3v = 0x04020, + .disable_lpm5_3v = 0x04020, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 15360, + .offset = 0x0c400, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Lib", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 12288, + .offset = 0x04000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x02000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR2533", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x0000041f, + .clock_map = { + {"PORT", 0x50}, + {"Captivate", 0xb7}, + {0}, + {0}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {0}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {0}, + {"Timer2_A2", 0x8b}, + {"Timer3_A2", 0x8c}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x823d, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + [0x4e] = 0x3f, + }, + .v3_erase = &erase_xv2_fr41xx, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x00018, + .disable_lpm5 = 0x00018, + .reg_mask_3v = 0x04020, + .enable_lpm5_3v = 0x04020, + .disable_lpm5_3v = 0x04020, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 15360, + .offset = 0x0c400, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Lib", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 12288, + .offset = 0x04000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x02000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR2632", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x0000041f, + .clock_map = { + {"PORT", 0x50}, + {"Captivate", 0xb7}, + {0}, + {0}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {0}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {0}, + {"Timer2_A2", 0x8b}, + {"Timer3_A2", 0x8c}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x823e, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + [0x4e] = 0x3f, + }, + .v3_erase = &erase_xv2_fr41xx, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x00018, + .disable_lpm5 = 0x00018, + .reg_mask_3v = 0x04020, + .enable_lpm5_3v = 0x04020, + .disable_lpm5_3v = 0x04020, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 8192, + .offset = 0x0e000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Lib", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 12288, + .offset = 0x04000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x02000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR2532", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x0000041f, + .clock_map = { + {"PORT", 0x50}, + {"Captivate", 0xb7}, + {0}, + {0}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {0}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {0}, + {"Timer2_A2", 0x8b}, + {"Timer3_A2", 0x8c}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x823f, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + [0x4e] = 0x3f, + }, + .v3_erase = &erase_xv2_fr41xx, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x00018, + .disable_lpm5 = 0x00018, + .reg_mask_3v = 0x04020, + .enable_lpm5_3v = 0x04020, + .disable_lpm5_3v = 0x04020, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 8192, + .offset = 0x0e000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Lib", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 12288, + .offset = 0x04000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x02000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR2433", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x0000041f, + .clock_map = { + {"PORT", 0x50}, + {"Captivate", 0xb7}, + {0}, + {0}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {0}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {0}, + {"Timer2_A2", 0x8b}, + {"Timer3_A2", 0x8c}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8240, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + [0x4e] = 0x3f, + }, + .v3_erase = &erase_xv2_fr41xx, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x00018, + .disable_lpm5 = 0x00018, + .reg_mask_3v = 0x04020, + .enable_lpm5_3v = 0x04020, + .disable_lpm5_3v = 0x04020, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 15360, + .offset = 0x0c400, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Lib", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 12288, + .offset = 0x04000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x02000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR6970", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x0000043f, + .clock_map = { + {"PORT", 0x50}, + {"LCDC", 0xb0}, + {0}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {"eUSCIB1", 0x31}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A5", 0x91}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8249, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 32768, + .offset = 0x08000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4064, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 6, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR6972", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x0000043f, + .clock_map = { + {"PORT", 0x50}, + {"LCDC", 0xb0}, + {0}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {"eUSCIB1", 0x31}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A5", 0x91}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x824b, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 64512, + .offset = 0x04400, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4064, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 6, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR6870", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x0000043f, + .clock_map = { + {"PORT", 0x50}, + {"LCDC", 0xb0}, + {0}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {"eUSCIB1", 0x31}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A5", 0x91}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x824c, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 32768, + .offset = 0x08000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4064, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 6, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR6872", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x0000043f, + .clock_map = { + {"PORT", 0x50}, + {"LCDC", 0xb0}, + {0}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {"eUSCIB1", 0x31}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A5", 0x91}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x824e, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 64512, + .offset = 0x04400, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4064, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 6, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR6920", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x0000043f, + .clock_map = { + {"PORT", 0x50}, + {"LCDC", 0xb0}, + {0}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {"eUSCIB1", 0x31}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A5", 0x91}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x824f, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 32768, + .offset = 0x08000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4064, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 6, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR6920", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x0000043f, + .clock_map = { + {"PORT", 0x50}, + {"LCDC", 0xb0}, + {0}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {"eUSCIB1", 0x31}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A5", 0x91}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8250, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 32768, + .offset = 0x08000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4064, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 6, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR6922", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x0000043f, + .clock_map = { + {"PORT", 0x50}, + {"LCDC", 0xb0}, + {0}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {"eUSCIB1", 0x31}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A5", 0x91}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8253, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 64512, + .offset = 0x04400, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4064, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 6, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR6922", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x0000043f, + .clock_map = { + {"PORT", 0x50}, + {"LCDC", 0xb0}, + {0}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {"eUSCIB1", 0x31}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A5", 0x91}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8254, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 64512, + .offset = 0x04400, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4064, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 6, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR6820", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x0000043f, + .clock_map = { + {"PORT", 0x50}, + {"LCDC", 0xb0}, + {0}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {"eUSCIB1", 0x31}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A5", 0x91}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8255, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 32768, + .offset = 0x08000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4064, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 6, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR6820", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x0000043f, + .clock_map = { + {"PORT", 0x50}, + {"LCDC", 0xb0}, + {0}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {"eUSCIB1", 0x31}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A5", 0x91}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8256, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 32768, + .offset = 0x08000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4064, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 6, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR6822", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x0000043f, + .clock_map = { + {"PORT", 0x50}, + {"LCDC", 0xb0}, + {0}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {"eUSCIB1", 0x31}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A5", 0x91}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8259, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 64512, + .offset = 0x04400, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4064, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 6, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR6822", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x0000043f, + .clock_map = { + {"PORT", 0x50}, + {"LCDC", 0xb0}, + {0}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {"eUSCIB1", 0x31}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A5", 0x91}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x825a, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 64512, + .offset = 0x04400, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4064, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 6, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR5970", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x0000043f, + .clock_map = { + {"PORT", 0x50}, + {0}, + {0}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {"eUSCIB1", 0x31}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A5", 0x91}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x825b, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 32768, + .offset = 0x08000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4064, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 6, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR5972", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x0000043f, + .clock_map = { + {"PORT", 0x50}, + {0}, + {0}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {"eUSCIB1", 0x31}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A5", 0x91}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x825d, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 64512, + .offset = 0x04400, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4064, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 6, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR5870", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x0000043f, + .clock_map = { + {"PORT", 0x50}, + {0}, + {0}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {"eUSCIB1", 0x31}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A5", 0x91}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x825e, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 32768, + .offset = 0x08000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4064, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 6, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR5872", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x0000043f, + .clock_map = { + {"PORT", 0x50}, + {0}, + {0}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {"eUSCIB1", 0x31}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A5", 0x91}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8260, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 64512, + .offset = 0x04400, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4064, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 6, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR5922", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x0000043f, + .clock_map = { + {"PORT", 0x50}, + {0}, + {0}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {"eUSCIB1", 0x31}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A5", 0x91}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8261, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 64512, + .offset = 0x04400, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4064, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 6, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR5922", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x0000043f, + .clock_map = { + {"PORT", 0x50}, + {0}, + {0}, + {"Comparator E", 0xa8}, + {"ADC12B", 0xd8}, + {"RTC", 0x8a}, + {"eUSCIB1", 0x31}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A5", 0x91}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8262, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 64512, + .offset = 0x04400, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4064, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 6, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR2033", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x00000407, + .clock_map = { + {"PORT", 0x50}, + {0}, + {0}, + {0}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {0}, + {"eUSCIB0", 0x30}, + {0}, + {"eUSCIA0", 0x2c}, + {0}, + {0}, + {0}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8275, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + [0x4e] = 0x3f, + }, + .v3_erase = &erase_xv2_fr41xx, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x00018, + .disable_lpm5 = 0x00018, + .reg_mask_3v = 0x04020, + .enable_lpm5_3v = 0x04020, + .disable_lpm5_3v = 0x04020, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 15360, + .offset = 0x0c400, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x02000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430F6720A", + .bits = 20, + .psa = CHIPINFO_PSA_ENHANCED, + .clock_control = 0x02, + .mclk_control = 0x0000041f, + .clock_map = { + {0}, + {0}, + {0}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {0}, + {0}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8276, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x38, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2, + .v3_write = &write_xv2, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_1337, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 16384, + .offset = 0x0c000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430F6721A", + .bits = 20, + .psa = CHIPINFO_PSA_ENHANCED, + .clock_control = 0x02, + .mclk_control = 0x0000041f, + .clock_map = { + {0}, + {0}, + {0}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {0}, + {0}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8277, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x38, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2, + .v3_write = &write_xv2, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_1337, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 32768, + .offset = 0x08000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR2032", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x00000407, + .clock_map = { + {"PORT", 0x50}, + {0}, + {0}, + {0}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {0}, + {"eUSCIB0", 0x30}, + {0}, + {"eUSCIA0", 0x2c}, + {0}, + {0}, + {0}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8278, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + [0x4e] = 0x3f, + }, + .v3_erase = &erase_xv2_fr41xx, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x00018, + .disable_lpm5 = 0x00018, + .reg_mask_3v = 0x04020, + .enable_lpm5_3v = 0x04020, + .disable_lpm5_3v = 0x04020, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 8192, + .offset = 0x0e000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x02000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430F6723A", + .bits = 20, + .psa = CHIPINFO_PSA_ENHANCED, + .clock_control = 0x02, + .mclk_control = 0x0000041f, + .clock_map = { + {0}, + {0}, + {0}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {0}, + {0}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8279, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x38, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2, + .v3_write = &write_xv2, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_1337, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 65536, + .offset = 0x04000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 2, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430F6724A", + .bits = 20, + .psa = CHIPINFO_PSA_ENHANCED, + .clock_control = 0x02, + .mclk_control = 0x0000041f, + .clock_map = { + {0}, + {0}, + {0}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {0}, + {0}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x827a, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x38, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2, + .v3_write = &write_xv2, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_1337, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 98304, + .offset = 0x04000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 3, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430F6725A", + .bits = 20, + .psa = CHIPINFO_PSA_ENHANCED, + .clock_control = 0x02, + .mclk_control = 0x0000041f, + .clock_map = { + {0}, + {0}, + {0}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {0}, + {0}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x827b, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x38, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2, + .v3_write = &write_xv2, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_1337, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 131072, + .offset = 0x04000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430F6726A", + .bits = 20, + .psa = CHIPINFO_PSA_ENHANCED, + .clock_control = 0x02, + .mclk_control = 0x0000041f, + .clock_map = { + {0}, + {0}, + {0}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {0}, + {0}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x827c, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x38, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2, + .v3_write = &write_xv2, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_1337, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 131072, + .offset = 0x04000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 8192, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430F6730A", + .bits = 20, + .psa = CHIPINFO_PSA_ENHANCED, + .clock_control = 0x02, + .mclk_control = 0x0000041f, + .clock_map = { + {0}, + {0}, + {0}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {0}, + {0}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8280, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x38, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2, + .v3_write = &write_xv2, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_1337, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 16384, + .offset = 0x0c000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430F6731A", + .bits = 20, + .psa = CHIPINFO_PSA_ENHANCED, + .clock_control = 0x02, + .mclk_control = 0x0000041f, + .clock_map = { + {0}, + {0}, + {0}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {0}, + {0}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8281, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x38, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2, + .v3_write = &write_xv2, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_1337, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 32768, + .offset = 0x08000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430F6733A", + .bits = 20, + .psa = CHIPINFO_PSA_ENHANCED, + .clock_control = 0x02, + .mclk_control = 0x0000041f, + .clock_map = { + {0}, + {0}, + {0}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {0}, + {0}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8283, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x38, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2, + .v3_write = &write_xv2, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_1337, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 65536, + .offset = 0x04000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 2, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430F6734A", + .bits = 20, + .psa = CHIPINFO_PSA_ENHANCED, + .clock_control = 0x02, + .mclk_control = 0x0000041f, + .clock_map = { + {0}, + {0}, + {0}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {0}, + {0}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8284, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x38, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2, + .v3_write = &write_xv2, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_1337, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 98304, + .offset = 0x04000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 3, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430F6735A", + .bits = 20, + .psa = CHIPINFO_PSA_ENHANCED, + .clock_control = 0x02, + .mclk_control = 0x0000041f, + .clock_map = { + {0}, + {0}, + {0}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {0}, + {0}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8285, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x38, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2, + .v3_write = &write_xv2, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_1337, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 131072, + .offset = 0x04000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430F6736A", + .bits = 20, + .psa = CHIPINFO_PSA_ENHANCED, + .clock_control = 0x02, + .mclk_control = 0x0000041f, + .clock_map = { + {0}, + {0}, + {0}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {0}, + {0}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8286, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x38, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2, + .v3_write = &write_xv2, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_1337, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 131072, + .offset = 0x04000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 8192, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430F67621A", + .bits = 20, + .psa = CHIPINFO_PSA_ENHANCED, + .clock_control = 0x02, + .mclk_control = 0x0000041f, + .clock_map = { + {0}, + {0}, + {0}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {0}, + {0}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8287, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x38, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2, + .v3_write = &write_xv2, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_1337, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 65536, + .offset = 0x04000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 2, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430F67641A", + .bits = 20, + .psa = CHIPINFO_PSA_ENHANCED, + .clock_control = 0x02, + .mclk_control = 0x0000041f, + .clock_map = { + {0}, + {0}, + {0}, + {"SD24B", 0xd5}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIA1", 0x2d}, + {"eUSCIA0", 0x2c}, + {0}, + {0}, + {"Timer0_A3", 0x8e}, + {"Timer1_A2", 0x8b}, + {"Timer2_A2", 0x8c}, + {"Timer3_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8288, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x38, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + }, + .v3_erase = &erase_xv2, + .v3_write = &write_xv2, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_1337, + .power = { + .reg_mask = 0x00000, + .enable_lpm5 = 0x00000, + .disable_lpm5 = 0x00000, + .reg_mask_3v = 0x00000, + .enable_lpm5_3v = 0x00000, + .disable_lpm5_3v = 0x00000, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 131072, + .offset = 0x04000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 8192, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 128, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_FLASH, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 512, + .bank_size = 0 /* no info */, + .banks = 4, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR5994", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x1000107f, + .clock_map = { + {"PORT", 0x50}, + {"ADC12B", 0xd8}, + {"Comparator E", 0xa8}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIB1", 0x31}, + {"eUSCIA1", 0x2d}, + {"eUSCIA2", 0x2e}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A2", 0x8c}, + {"Timer4_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {"eUSCIA3", 0x2f}, + {"eUSCIB2", 0x32}, + {"eUSCIB3", 0x33}, + {"AES128", 0x60}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x82a1, + .ver_sub_id = 0x0000, + .revision = 0x10, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 262144, + .offset = 0x04000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "LeaRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x02c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit2", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 1280, + .offset = 0x00b00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "LeaPeripheral", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 128, + .offset = 0x00a80, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 2656, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 6, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR59941", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x1000107f, + .clock_map = { + {"PORT", 0x50}, + {"ADC12B", 0xd8}, + {"Comparator E", 0xa8}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIB1", 0x31}, + {"eUSCIA1", 0x2d}, + {"eUSCIA2", 0x2e}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A2", 0x8c}, + {"Timer4_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {"eUSCIA3", 0x2f}, + {"eUSCIB2", 0x32}, + {"eUSCIB3", 0x33}, + {"AES128", 0x60}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x82a2, + .ver_sub_id = 0x0000, + .revision = 0x10, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 262144, + .offset = 0x04000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "LeaRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x02c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit2", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 1280, + .offset = 0x00b00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "LeaPeripheral", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 128, + .offset = 0x00a80, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 2656, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 6, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR5992", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x1000107f, + .clock_map = { + {"PORT", 0x50}, + {"ADC12B", 0xd8}, + {"Comparator E", 0xa8}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIB1", 0x31}, + {"eUSCIA1", 0x2d}, + {"eUSCIA2", 0x2e}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A2", 0x8c}, + {"Timer4_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {"eUSCIA3", 0x2f}, + {"eUSCIB2", 0x32}, + {"eUSCIB3", 0x33}, + {"AES128", 0x60}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x82a3, + .ver_sub_id = 0x0000, + .revision = 0x10, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 131072, + .offset = 0x04000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "LeaRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x02c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit2", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 1280, + .offset = 0x00b00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "LeaPeripheral", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 128, + .offset = 0x00a80, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 2656, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 6, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR5964", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x1000107f, + .clock_map = { + {"PORT", 0x50}, + {"ADC12B", 0xd8}, + {"Comparator E", 0xa8}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIB1", 0x31}, + {"eUSCIA1", 0x2d}, + {"eUSCIA2", 0x2e}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A2", 0x8c}, + {"Timer4_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {"eUSCIA3", 0x2f}, + {"eUSCIB2", 0x32}, + {"eUSCIB3", 0x33}, + {"AES128", 0x60}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x82a4, + .ver_sub_id = 0x0000, + .revision = 0x10, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 262144, + .offset = 0x04000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 8192, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4064, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 6, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR5962", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x1000107f, + .clock_map = { + {"PORT", 0x50}, + {"ADC12B", 0xd8}, + {"Comparator E", 0xa8}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIB1", 0x31}, + {"eUSCIA1", 0x2d}, + {"eUSCIA2", 0x2e}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A2", 0x8c}, + {"Timer4_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {"eUSCIA3", 0x2f}, + {"eUSCIB2", 0x32}, + {"eUSCIB3", 0x33}, + {"AES128", 0x60}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x82a6, + .ver_sub_id = 0x0000, + .revision = 0x10, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 131072, + .offset = 0x04000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 8192, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4064, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 6, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR6047", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x1000107f, + .clock_map = { + {"PORT", 0x50}, + {"ADC12B", 0xd8}, + {"Comparator E", 0xa8}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIB1", 0x31}, + {"eUSCIA1", 0x2d}, + {"eUSCIA2", 0x2e}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A2", 0x8c}, + {"Timer4_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {"eUSCIA3", 0x2f}, + {0}, + {0}, + {"AES256", 0x60}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x82e9, + .ver_sub_id = 0x0000, + .revision = 0x10, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 262144, + .offset = 0x04000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "LeaRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x02c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit3", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x00f00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "UssPeripheral", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x00e00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit2", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 768, + .offset = 0x00b00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "LeaPeripheral", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 128, + .offset = 0x00a80, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 2656, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Eem", .type = CHIPINFO_MEMTYPE_REGISTER, .bits = 0, .mapped = 0, .size = 128, .offset = 0x00000, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR6047", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x1000107f, + .clock_map = { + {"PORT", 0x50}, + {"ADC12B", 0xd8}, + {"Comparator E", 0xa8}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIB1", 0x31}, + {"eUSCIA1", 0x2d}, + {"eUSCIA2", 0x2e}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A2", 0x8c}, + {"Timer4_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {"eUSCIA3", 0x2f}, + {0}, + {0}, + {"AES256", 0x60}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x82ea, + .ver_sub_id = 0x0000, + .revision = 0x10, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 262144, + .offset = 0x04000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "LeaRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x02c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit3", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x00f00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "UssPeripheral", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x00e00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit2", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 768, + .offset = 0x00b00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "LeaPeripheral", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 128, + .offset = 0x00a80, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 2656, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Eem", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 0, + .mapped = 0, + .size = 128, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR6047", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x1000107f, + .clock_map = { + {"PORT", 0x50}, + {"ADC12B", 0xd8}, + {"Comparator E", 0xa8}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIB1", 0x31}, + {"eUSCIA1", 0x2d}, + {"eUSCIA2", 0x2e}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A2", 0x8c}, + {"Timer4_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {"eUSCIA3", 0x2f}, + {0}, + {0}, + {"AES256", 0x60}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x82ea, + .ver_sub_id = 0x0000, + .revision = 0x20, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 262144, + .offset = 0x04000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "LeaRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x02c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit3", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x00f00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "UssPeripheral", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x00e00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit2", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 768, + .offset = 0x00b00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "LeaPeripheral", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 128, + .offset = 0x00a80, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 2656, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Eem", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 0, + .mapped = 0, + .size = 128, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR6045", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x1000107f, + .clock_map = { + {"PORT", 0x50}, + {"ADC12B", 0xd8}, + {"Comparator E", 0xa8}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIB1", 0x31}, + {"eUSCIA1", 0x2d}, + {"eUSCIA2", 0x2e}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A2", 0x8c}, + {"Timer4_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {"eUSCIA3", 0x2f}, + {0}, + {0}, + {"AES256", 0x60}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x82eb, + .ver_sub_id = 0x0000, + .revision = 0x10, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 131072, + .offset = 0x04000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "LeaRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x02c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit3", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x00f00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "UssPeripheral", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x00e00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit2", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 768, + .offset = 0x00b00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "LeaPeripheral", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 128, + .offset = 0x00a80, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 2656, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Eem", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 0, + .mapped = 0, + .size = 128, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR6045", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x1000107f, + .clock_map = { + {"PORT", 0x50}, + {"ADC12B", 0xd8}, + {"Comparator E", 0xa8}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIB1", 0x31}, + {"eUSCIA1", 0x2d}, + {"eUSCIA2", 0x2e}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A2", 0x8c}, + {"Timer4_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {"eUSCIA3", 0x2f}, + {0}, + {0}, + {"AES256", 0x60}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x82eb, + .ver_sub_id = 0x0000, + .revision = 0x20, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 131072, + .offset = 0x04000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "LeaRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x02c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit3", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x00f00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "UssPeripheral", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x00e00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit2", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 768, + .offset = 0x00b00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "LeaPeripheral", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 128, + .offset = 0x00a80, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 2656, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Eem", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 0, + .mapped = 0, + .size = 128, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR6037", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x1000107f, + .clock_map = { + {"PORT", 0x50}, + {"ADC12B", 0xd8}, + {"Comparator E", 0xa8}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIB1", 0x31}, + {"eUSCIA1", 0x2d}, + {"eUSCIA2", 0x2e}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A2", 0x8c}, + {"Timer4_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {"eUSCIA3", 0x2f}, + {0}, + {0}, + {"AES256", 0x60}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x82ec, + .ver_sub_id = 0x0000, + .revision = 0x10, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 262144, + .offset = 0x04000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "LeaRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x02c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit2", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 1280, + .offset = 0x00b00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "LeaPeripheral", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 128, + .offset = 0x00a80, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 2656, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Eem", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 0, + .mapped = 0, + .size = 128, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR6037", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x1000107f, + .clock_map = { + {"PORT", 0x50}, + {"ADC12B", 0xd8}, + {"Comparator E", 0xa8}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIB1", 0x31}, + {"eUSCIA1", 0x2d}, + {"eUSCIA2", 0x2e}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A2", 0x8c}, + {"Timer4_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {"eUSCIA3", 0x2f}, + {0}, + {0}, + {"AES256", 0x60}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x82ec, + .ver_sub_id = 0x0000, + .revision = 0x20, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 262144, + .offset = 0x04000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "LeaRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x02c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit2", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 1280, + .offset = 0x00b00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "LeaPeripheral", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 128, + .offset = 0x00a80, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 2656, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Eem", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 0, + .mapped = 0, + .size = 128, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR6035", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x1000107f, + .clock_map = { + {"PORT", 0x50}, + {"ADC12B", 0xd8}, + {"Comparator E", 0xa8}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIB1", 0x31}, + {"eUSCIA1", 0x2d}, + {"eUSCIA2", 0x2e}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A2", 0x8c}, + {"Timer4_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {"eUSCIA3", 0x2f}, + {0}, + {0}, + {"AES256", 0x60}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x82ed, + .ver_sub_id = 0x0000, + .revision = 0x10, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 131072, + .offset = 0x04000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "LeaRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x02c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit2", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 1280, + .offset = 0x00b00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "LeaPeripheral", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 128, + .offset = 0x00a80, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 2656, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Eem", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 0, + .mapped = 0, + .size = 128, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR6035", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x1000107f, + .clock_map = { + {"PORT", 0x50}, + {"ADC12B", 0xd8}, + {"Comparator E", 0xa8}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIB1", 0x31}, + {"eUSCIA1", 0x2d}, + {"eUSCIA2", 0x2e}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A2", 0x8c}, + {"Timer4_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {"eUSCIA3", 0x2f}, + {0}, + {0}, + {"AES256", 0x60}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x82ed, + .ver_sub_id = 0x0000, + .revision = 0x20, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 131072, + .offset = 0x04000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "LeaRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x02c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit2", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 1280, + .offset = 0x00b00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "LeaPeripheral", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 128, + .offset = 0x00a80, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 2656, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Eem", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 0, + .mapped = 0, + .size = 128, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR60471", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x1000107f, + .clock_map = { + {"PORT", 0x50}, + {"ADC12B", 0xd8}, + {"Comparator E", 0xa8}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIB1", 0x31}, + {"eUSCIA1", 0x2d}, + {"eUSCIA2", 0x2e}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A2", 0x8c}, + {"Timer4_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {"eUSCIA3", 0x2f}, + {0}, + {0}, + {"AES256", 0x60}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x82ee, + .ver_sub_id = 0x0000, + .revision = 0x10, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 262144, + .offset = 0x04000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "LeaRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x02c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit3", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x00f00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "UssPeripheral", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x00e00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit2", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 768, + .offset = 0x00b00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "LeaPeripheral", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 128, + .offset = 0x00a80, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 2656, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Eem", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 0, + .mapped = 0, + .size = 128, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR60471", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x1000107f, + .clock_map = { + {"PORT", 0x50}, + {"ADC12B", 0xd8}, + {"Comparator E", 0xa8}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIB1", 0x31}, + {"eUSCIA1", 0x2d}, + {"eUSCIA2", 0x2e}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A2", 0x8c}, + {"Timer4_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {"eUSCIA3", 0x2f}, + {0}, + {0}, + {"AES256", 0x60}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x82ee, + .ver_sub_id = 0x0000, + .revision = 0x20, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 262144, + .offset = 0x04000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "LeaRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x02c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit3", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x00f00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "UssPeripheral", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x00e00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit2", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 768, + .offset = 0x00b00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "LeaPeripheral", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 128, + .offset = 0x00a80, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 2656, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Eem", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 0, + .mapped = 0, + .size = 128, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR60371", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x1000107f, + .clock_map = { + {"PORT", 0x50}, + {"ADC12B", 0xd8}, + {"Comparator E", 0xa8}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIB1", 0x31}, + {"eUSCIA1", 0x2d}, + {"eUSCIA2", 0x2e}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A2", 0x8c}, + {"Timer4_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {"eUSCIA3", 0x2f}, + {0}, + {0}, + {"AES256", 0x60}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x82ef, + .ver_sub_id = 0x0000, + .revision = 0x10, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 262144, + .offset = 0x04000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "LeaRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x02c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit2", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 1280, + .offset = 0x00b00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "LeaPeripheral", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 128, + .offset = 0x00a80, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 2656, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Eem", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 0, + .mapped = 0, + .size = 128, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR60371", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x1000107f, + .clock_map = { + {"PORT", 0x50}, + {"ADC12B", 0xd8}, + {"Comparator E", 0xa8}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIB1", 0x31}, + {"eUSCIA1", 0x2d}, + {"eUSCIA2", 0x2e}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A2", 0x8c}, + {"Timer4_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {"eUSCIA3", 0x2f}, + {0}, + {0}, + {"AES256", 0x60}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x82ef, + .ver_sub_id = 0x0000, + .revision = 0x20, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 262144, + .offset = 0x04000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "LeaRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x02c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit2", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 1280, + .offset = 0x00b00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "LeaPeripheral", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 128, + .offset = 0x00a80, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 2656, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Eem", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 0, + .mapped = 0, + .size = 128, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR2311", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x00000407, + .clock_map = { + {"PORT", 0x50}, + {0}, + {0}, + {0}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {0}, + {"eUSCIB0", 0x30}, + {0}, + {"eUSCIA0", 0x2c}, + {0}, + {0}, + {"Comparator E", 0xa8}, + {"Timer0_B3", 0x97}, + {"Timer1_B3", 0x98}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x82f0, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + [0x4e] = 0x3f, + }, + .v3_erase = &erase_xv2_fr41xx, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x00018, + .disable_lpm5 = 0x00018, + .reg_mask_3v = 0x04020, + .enable_lpm5_3v = 0x04020, + .disable_lpm5_3v = 0x04020, + }, + .memory = { + { + .name = "Bsl2", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0xffc00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 3840, + .offset = 0x0f100, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x02000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 128, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR2310", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x00000407, + .clock_map = { + {"PORT", 0x50}, + {0}, + {0}, + {0}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {0}, + {"eUSCIB0", 0x30}, + {0}, + {"eUSCIA0", 0x2c}, + {0}, + {0}, + {"Comparator E", 0xa8}, + {"Timer0_B3", 0x97}, + {"Timer1_B3", 0x98}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x82f1, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + [0x4e] = 0x3f, + }, + .v3_erase = &erase_xv2_fr41xx, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x00018, + .disable_lpm5 = 0x00018, + .reg_mask_3v = 0x04020, + .enable_lpm5_3v = 0x04020, + .disable_lpm5_3v = 0x04020, + }, + .memory = { + { + .name = "Bsl2", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0xffc00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x0f800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x02000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 128, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR2111", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x00000405, + .clock_map = { + {"PORT", 0x50}, + {0}, + {0}, + {0}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {0}, + {0}, + {0}, + {"eUSCIA0", 0x2c}, + {0}, + {0}, + {"Comparator E", 0xa8}, + {"Timer0_B3", 0x97}, + {0}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x82fa, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + [0x4e] = 0x3f, + }, + .v3_erase = &erase_xv2_fr41xx, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x00018, + .disable_lpm5 = 0x00018, + .reg_mask_3v = 0x04020, + .enable_lpm5_3v = 0x04020, + .disable_lpm5_3v = 0x04020, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 3840, + .offset = 0x0f100, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x02000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 128, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR2110", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x00000405, + .clock_map = { + {"PORT", 0x50}, + {0}, + {0}, + {0}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {0}, + {0}, + {0}, + {"eUSCIA0", 0x2c}, + {0}, + {0}, + {"Comparator E", 0xa8}, + {"Timer0_B3", 0x97}, + {0}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x82fb, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + [0x4e] = 0x3f, + }, + .v3_erase = &erase_xv2_fr41xx, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x00018, + .disable_lpm5 = 0x00018, + .reg_mask_3v = 0x04020, + .enable_lpm5_3v = 0x04020, + .disable_lpm5_3v = 0x04020, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x0f800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x02000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 128, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR50431", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x1000107f, + .clock_map = { + {"PORT", 0x50}, + {"ADC12B", 0xd8}, + {"Comparator E", 0xa8}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIB1", 0x31}, + {"eUSCIA1", 0x2d}, + {"eUSCIA2", 0x2e}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A2", 0x8c}, + {"Timer4_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {"eUSCIA3", 0x2f}, + {0}, + {0}, + {"AES256", 0x60}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x830f, + .ver_sub_id = 0x0000, + .revision = 0x10, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 65536, + .offset = 0x06000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "LeaRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 8192, + .offset = 0x04000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 768, + .offset = 0x01900, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit3", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x00f00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "UssPeripheral", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x00e00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit2", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 768, + .offset = 0x00b00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "LeaPeripheral", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 128, + .offset = 0x00a80, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 2656, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Eem", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 0, + .mapped = 0, + .size = 128, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR2522", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x00000407, + .clock_map = { + {"PORT", 0x50}, + {"Captivate", 0xb7}, + {0}, + {0}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {0}, + {"eUSCIB0", 0x30}, + {"eUSCIA0", 0x2c}, + {0}, + {0}, + {0}, + {0}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8310, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + [0x4e] = 0x3f, + }, + .v3_erase = &erase_xv2_fr41xx, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x00018, + .disable_lpm5 = 0x00018, + .reg_mask_3v = 0x04020, + .enable_lpm5_3v = 0x04020, + .disable_lpm5_3v = 0x04020, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 7424, + .offset = 0x0e300, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Lib", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 12288, + .offset = 0x04000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x02000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR2422", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x00000407, + .clock_map = { + {"PORT", 0x50}, + {"Captivate", 0xb7}, + {0}, + {0}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {0}, + {"eUSCIB0", 0x30}, + {"eUSCIA0", 0x2c}, + {0}, + {0}, + {0}, + {0}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8311, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + [0x4e] = 0x3f, + }, + .v3_erase = &erase_xv2_fr41xx, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x00018, + .disable_lpm5 = 0x00018, + .reg_mask_3v = 0x04020, + .enable_lpm5_3v = 0x04020, + .disable_lpm5_3v = 0x04020, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 7424, + .offset = 0x0e300, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Lib", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 12288, + .offset = 0x04000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x02000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR6043", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x1000107f, + .clock_map = { + {"PORT", 0x50}, + {"ADC12B", 0xd8}, + {"Comparator E", 0xa8}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIB1", 0x31}, + {"eUSCIA1", 0x2d}, + {"eUSCIA2", 0x2e}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A2", 0x8c}, + {"Timer4_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {"eUSCIA3", 0x2f}, + {0}, + {0}, + {"AES256", 0x60}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8312, + .ver_sub_id = 0x0000, + .revision = 0x10, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 65536, + .offset = 0x06000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "LeaRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 8192, + .offset = 0x04000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 768, + .offset = 0x01900, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit3", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x00f00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "UssPeripheral", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x00e00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit2", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 768, + .offset = 0x00b00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "LeaPeripheral", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 128, + .offset = 0x00a80, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 2656, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Eem", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 0, + .mapped = 0, + .size = 128, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR6041", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x1000107f, + .clock_map = { + {"PORT", 0x50}, + {"ADC12B", 0xd8}, + {"Comparator E", 0xa8}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIB1", 0x31}, + {"eUSCIA1", 0x2d}, + {"eUSCIA2", 0x2e}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A2", 0x8c}, + {"Timer4_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {"eUSCIA3", 0x2f}, + {0}, + {0}, + {"AES256", 0x60}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8314, + .ver_sub_id = 0x0000, + .revision = 0x10, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 32768, + .offset = 0x08000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "LeaRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 8192, + .offset = 0x04000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 768, + .offset = 0x01900, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit3", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x00f00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "UssPeripheral", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x00e00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit2", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 768, + .offset = 0x00b00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "LeaPeripheral", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 128, + .offset = 0x00a80, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 2656, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Eem", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 0, + .mapped = 0, + .size = 128, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR5043", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x1000107f, + .clock_map = { + {"PORT", 0x50}, + {"ADC12B", 0xd8}, + {"Comparator E", 0xa8}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIB1", 0x31}, + {"eUSCIA1", 0x2d}, + {"eUSCIA2", 0x2e}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A2", 0x8c}, + {"Timer4_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {"eUSCIA3", 0x2f}, + {0}, + {0}, + {"AES256", 0x60}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8317, + .ver_sub_id = 0x0000, + .revision = 0x10, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 65536, + .offset = 0x06000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "LeaRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 8192, + .offset = 0x04000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 768, + .offset = 0x01900, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit3", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x00f00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "UssPeripheral", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x00e00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit2", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 768, + .offset = 0x00b00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "LeaPeripheral", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 128, + .offset = 0x00a80, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 2656, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Eem", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 0, + .mapped = 0, + .size = 128, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR5041", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x1000107f, + .clock_map = { + {"PORT", 0x50}, + {"ADC12B", 0xd8}, + {"Comparator E", 0xa8}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIB1", 0x31}, + {"eUSCIA1", 0x2d}, + {"eUSCIA2", 0x2e}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A2", 0x8c}, + {"Timer4_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {"eUSCIA3", 0x2f}, + {0}, + {0}, + {"AES256", 0x60}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8318, + .ver_sub_id = 0x0000, + .revision = 0x10, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 32768, + .offset = 0x08000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "LeaRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 8192, + .offset = 0x04000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 768, + .offset = 0x01900, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit3", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x00f00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "UssPeripheral", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x00e00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit2", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 768, + .offset = 0x00b00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "LeaPeripheral", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 128, + .offset = 0x00a80, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 2656, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Eem", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 0, + .mapped = 0, + .size = 128, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR60431", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x1000107f, + .clock_map = { + {"PORT", 0x50}, + {"ADC12B", 0xd8}, + {"Comparator E", 0xa8}, + {"RTC", 0x8a}, + {"eUSCIB0", 0x30}, + {"eUSCIB1", 0x31}, + {"eUSCIA1", 0x2d}, + {"eUSCIA2", 0x2e}, + {"eUSCIA0", 0x2c}, + {"Timer0_B7", 0x9d}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Timer2_A2", 0x8b}, + {"Timer3_A2", 0x8c}, + {"Timer4_A2", 0x8d}, + {"Watchdog Timer", 0x0a}, + {"eUSCIA3", 0x2f}, + {0}, + {0}, + {"AES256", 0x60}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x831a, + .ver_sub_id = 0x0000, + .revision = 0x10, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0xff, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x0a] = 0x4a, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x50, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + }, + .v3_erase = &erase_xv2_fram, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x10018, + .disable_lpm5 = 0x10000, + .reg_mask_3v = 0x0c0a0, + .enable_lpm5_3v = 0x0c020, + .disable_lpm5_3v = 0x040a0, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 65536, + .offset = 0x06000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "LeaRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 8192, + .offset = 0x04000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 768, + .offset = 0x01900, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit3", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x00f00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "UssPeripheral", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x00e00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit2", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 768, + .offset = 0x00b00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "LeaPeripheral", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 128, + .offset = 0x00a80, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit1", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 2656, + .offset = 0x00020, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "TinyRam", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 26, + .offset = 0x00006, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Eem", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 0, + .mapped = 0, + .size = 128, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR2512", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x00000407, + .clock_map = { + {"PORT", 0x50}, + {"Captivate", 0xb7}, + {0}, + {0}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {0}, + {"eUSCIB0", 0x30}, + {"eUSCIA0", 0x2c}, + {0}, + {0}, + {0}, + {0}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x831c, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + [0x4e] = 0x3f, + }, + .v3_erase = &erase_xv2_fr41xx, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x00018, + .disable_lpm5 = 0x00018, + .reg_mask_3v = 0x04020, + .enable_lpm5_3v = 0x04020, + .disable_lpm5_3v = 0x04020, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 7424, + .offset = 0x0e300, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Lib", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 12288, + .offset = 0x04000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x02000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Info", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 256, + .offset = 0x01800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2048, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR2100", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x00000405, + .clock_map = { + {"PORT", 0x50}, + {0}, + {0}, + {0}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {0}, + {0}, + {0}, + {"eUSCIA0", 0x2c}, + {0}, + {0}, + {"Comparator E", 0xa8}, + {"Timer0_B3", 0x97}, + {0}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8320, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + [0x4e] = 0x3f, + }, + .v3_erase = &erase_xv2_fr41xx, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x00018, + .disable_lpm5 = 0x00018, + .reg_mask_3v = 0x04020, + .enable_lpm5_3v = 0x04020, + .disable_lpm5_3v = 0x04020, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x0fc00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x02000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 128, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + {0} + }, + }, + + { + .name = "MSP430FR2000", + .bits = 20, + .psa = CHIPINFO_PSA_REGULAR, + .clock_control = 0x02, + .mclk_control = 0x00000405, + .clock_map = { + {"PORT", 0x50}, + {0}, + {0}, + {0}, + {"ADC10", 0xd6}, + {"RTC", 0x8a}, + {0}, + {0}, + {0}, + {"eUSCIA0", 0x2c}, + {0}, + {0}, + {"Comparator E", 0xa8}, + {"Timer0_B3", 0x97}, + {0}, + {"Watchdog Timer", 0x0a}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + {0}, + }, + .id = { + .ver_id = 0x8321, + .ver_sub_id = 0x0000, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .id_mask = { + .ver_id = 0xffff, + .ver_sub_id = 0xffff, + .revision = 0x00, + .fab = 0x00, + .self = 0x0000, + .config = 0x00, + .fuses = 0x00, + .activation_key = 0x00000000, + }, + .eem = { /* no info */ }, + .voltage = { + .vcc_min = 1800, + .vcc_max = 3600, + .vcc_flash_min = 1800, + .vcc_secure_min = 2500, + .vpp_secure_min = 6000, + .vpp_secure_max = 7000, + .has_test_vpp = 1, + }, + .v3_functions = { + [0x09] = 0x39, + [0x12] = 0x3a, + [0x13] = 0x3b, + [0x14] = 0x3c, + [0x15] = 0x3d, + [0x16] = 0x3d, + [0x17] = 0x3e, + [0x18] = 0x3f, + [0x19] = 0x3f, + [0x1a] = 0x40, + [0x1c] = 0x41, + [0x1d] = 0x42, + [0x1e] = 0x43, + [0x1f] = 0x44, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, + [0x4e] = 0x3f, + }, + .v3_erase = &erase_xv2_fr41xx, + .v3_write = &write_xv2_fram, + .clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC, + .features = 0 + | CHIPINFO_FEATURE_LCFE + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_FRAM, + .power = { + .reg_mask = 0x10018, + .enable_lpm5 = 0x00018, + .disable_lpm5 = 0x00018, + .reg_mask_3v = 0x04020, + .enable_lpm5_3v = 0x04020, + .disable_lpm5_3v = 0x04020, + }, + .memory = { + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x0fe00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 512, + .offset = 0x02000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 128, + .offset = 0x01a00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Bsl", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 1024, + .offset = 0x01000, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -78369,7 +92111,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x0417, + .mclk_control = 0x00000007, .clock_map = { {0}, {0}, @@ -78381,12 +92123,12 @@ const struct chipinfo chipinfo_db[] = { { {0}, {0}, {0}, - {"CCS", 0x02}, - {"APOOL", 0x2d}, + {"CCS", 0x1e}, + {"APOOL", 0xb5}, {0}, - {"Timer0_A3", 0x08}, - {"Timer1_A3", 0x09}, - {"Watchdog Timer", 0x01}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -78424,27 +92166,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0xffffffff, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x04, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 900, .vcc_max = 1800, @@ -78455,29 +92177,29 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, - .features = 0, + .features = 0 + | CHIPINFO_FEATURE_NO_BSL, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, @@ -78488,80 +92210,58 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 1888, - .offset = 0x0f880, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 128, - .offset = 0x02380, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 128, - .offset = 0x0f800, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "peripheral16bit", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 16, - .mapped = 1, - .size = 4096, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "VectorTable", + .name = "IrVec", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32, .offset = 0x0ffe0, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 1888, + .offset = 0x0f880, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 128, + .offset = 0x0f800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 128, + .offset = 0x02380, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -78573,7 +92273,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x0417, + .mclk_control = 0x00000007, .clock_map = { {0}, {0}, @@ -78585,12 +92285,12 @@ const struct chipinfo chipinfo_db[] = { { {0}, {0}, {0}, - {"CCS", 0x02}, - {"APOOL", 0x2d}, + {"CCS", 0x1e}, + {"APOOL", 0xb5}, {0}, - {"Timer0_A3", 0x08}, - {"Timer1_A3", 0x09}, - {"Watchdog Timer", 0x01}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -78628,27 +92328,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0xffffffff, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x04, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 900, .vcc_max = 1800, @@ -78659,30 +92339,30 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, .features = 0 - | CHIPINFO_FEATURE_QUICK_MEM_READ, + | CHIPINFO_FEATURE_QUICK_MEM_READ + | CHIPINFO_FEATURE_NO_BSL, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, @@ -78693,80 +92373,58 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 1920, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 128, - .offset = 0x02380, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 2016, - .offset = 0x0f800, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "peripheral16bit", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 16, - .mapped = 1, - .size = 4096, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "VectorTable", + .name = "IrVec", .type = CHIPINFO_MEMTYPE_RAM, .bits = 16, .mapped = 1, .size = 32, .offset = 0x0ffe0, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2016, + .offset = 0x0f800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 128, + .offset = 0x02380, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 1920, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, .banks = 1, }, {0} @@ -78778,7 +92436,7 @@ const struct chipinfo chipinfo_db[] = { { .bits = 20, .psa = CHIPINFO_PSA_REGULAR, .clock_control = 0x02, - .mclk_control = 0x0417, + .mclk_control = 0x00000007, .clock_map = { {0}, {0}, @@ -78790,12 +92448,12 @@ const struct chipinfo chipinfo_db[] = { { {0}, {0}, {0}, - {"CCS", 0x02}, - {"APOOL", 0x2d}, + {"CCS", 0x1e}, + {"APOOL", 0xb5}, {0}, - {"Timer0_A3", 0x08}, - {"Timer1_A3", 0x09}, - {"Watchdog Timer", 0x01}, + {"Timer0_A3", 0x8e}, + {"Timer1_A3", 0x8f}, + {"Watchdog Timer", 0x0a}, {0}, {0}, {0}, @@ -78833,27 +92491,7 @@ const struct chipinfo chipinfo_db[] = { { .fuses = 0x00, .activation_key = 0xffffffff, }, - .eem = { - .state_storage = 0x00, - .cycle_counter = 0x01, - .cycle_counter_ops = 0x00, - .trig_emulation_level = 0x04, - .trig_mem = 0x02, - .trig_reg = 0x00, - .trig_combinations = 0x02, - .trig_options = 0x01, - .trig_dma = 0x01, - .trig_read_write = 0x01, - .trig_reg_ops = 0x00, - .trig_comp_level = 0x02, - .trig_mem_cond_level = 0x00, - .trig_mem_umask_level = 0x00, - .seq_states = 0x00, - .seq_start = 0x00, - .seq_end = 0x00, - .seq_reset = 0x00, - .seq_blocked = 0x00, - }, + .eem = { /* no info */ }, .voltage = { .vcc_min = 900, .vcc_max = 1800, @@ -78864,29 +92502,29 @@ const struct chipinfo chipinfo_db[] = { { .has_test_vpp = 0, }, .v3_functions = { - [0x09] = 0x37, - [0x11] = 0x39, + [0x09] = 0x38, [0x12] = 0x3a, [0x13] = 0x3b, [0x14] = 0x3c, - [0x15] = 0x3c, + [0x15] = 0x3d, [0x16] = 0x3d, [0x17] = 0x3e, - [0x18] = 0x3e, + [0x18] = 0x3f, [0x19] = 0x3f, - [0x1b] = 0x40, + [0x1a] = 0x40, [0x1c] = 0x41, [0x1d] = 0x42, [0x1e] = 0x43, [0x1f] = 0x44, - [0x25] = 0x36, - [0x49] = 0x4a, + [0x20] = 0x45, + [0x26] = 0x37, + [0x4a] = 0x4b, }, .v3_erase = &erase_xv2, .v3_write = &write_xv2, - .v3_unlock = &bsl_unlock_xv2, .clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS, - .features = 0, + .features = 0 + | CHIPINFO_FEATURE_NO_BSL, .power = { .reg_mask = 0x00000, .enable_lpm5 = 0x00000, @@ -78897,80 +92535,58 @@ const struct chipinfo chipinfo_db[] = { { }, .memory = { { - .name = "main", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 96, - .offset = 0x01c00, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "system", - .type = CHIPINFO_MEMTYPE_RAM, - .bits = 16, - .mapped = 1, - .size = 128, - .offset = 0x02380, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "bootcode", - .type = CHIPINFO_MEMTYPE_ROM, - .bits = 16, - .mapped = 1, - .size = 2016, - .offset = 0x0f800, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "peripheral16bit", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 16, - .mapped = 1, - .size = 4096, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "CPU", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 16, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "EEM", - .type = CHIPINFO_MEMTYPE_REGISTER, - .bits = 0, - .mapped = 0, - .size = 128, - .offset = 0x00000, - .seg_size = 1, - .bank_size = 0, - .banks = 1, - }, - { - .name = "VectorTable", + .name = "IrVec", .type = CHIPINFO_MEMTYPE_ROM, .bits = 16, .mapped = 1, .size = 32, .offset = 0x0ffe0, .seg_size = 1, - .bank_size = 0, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "BootCode", + .type = CHIPINFO_MEMTYPE_ROM, + .bits = 16, + .mapped = 1, + .size = 2016, + .offset = 0x0f800, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Ram", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 128, + .offset = 0x02380, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Main", + .type = CHIPINFO_MEMTYPE_RAM, + .bits = 16, + .mapped = 1, + .size = 96, + .offset = 0x01c00, + .seg_size = 1, + .bank_size = 0 /* no info */, + .banks = 1, + }, + { + .name = "Peripheral16bit", + .type = CHIPINFO_MEMTYPE_REGISTER, + .bits = 16, + .mapped = 1, + .size = 4096, + .offset = 0x00000, + .seg_size = 1, + .bank_size = 0 /* no info */, .banks = 1, }, {0} diff --git a/util/chipinfo.h b/util/chipinfo.h index 139113a..d7ed6d4 100644 --- a/util/chipinfo.h +++ b/util/chipinfo.h @@ -138,7 +138,7 @@ struct chipinfo { unsigned int bits; chipinfo_psa_t psa; uint8_t clock_control; - uint16_t mclk_control; + uint32_t mclk_control; chipinfo_clock_sys_t clock_sys; chipinfo_features_t features;