From 76fb6a0ba6ea1f06bddcf562f0ce0baa61349028 Mon Sep 17 00:00:00 2001
From: sys64738 <sys64738@hellsite.site>
Date: Fri, 11 Mar 2022 22:24:46 +0100
Subject: [PATCH] pio fifo dma delay test

---
 src/test/delay.pio   | 95 ++++++++++++++++++++++++++++++++++++++++++++
 src/test/delaytest.c | 40 ++++++++++++++++++-
 2 files changed, 133 insertions(+), 2 deletions(-)

diff --git a/src/test/delay.pio b/src/test/delay.pio
index 41d541b..10a3ef4 100644
--- a/src/test/delay.pio
+++ b/src/test/delay.pio
@@ -21,8 +21,34 @@ _start:
 	nop [31]
 	set pins, 0
 
+.program delayf1
+.side_set 1
+
+_start:
+	nop [15]   side 0
+	nop [15]   side 0
+	nop [15]   side 0
+	nop [15]   side 0
+	nop [15]   side 0
+	nop [15]   side 0
+	nop [15]   side 0
+	nop [15]   side 0
+	set x, 7 [15] side 0
+	in x, 32 [15] side 0
+	push       side 0
+	nop [15]   side 1
+
+.program delayf2
+.side_set 1
+
+_start:
+	nop        side 0
+	pull       side 0
+	nop [15]   side 1
+
 % c-sdk {
 #include <hardware/clocks.h>
+#include <hardware/dma.h>
 
 static inline void delayt1_program_init(PIO pio, uint sm, uint offset,
 		uint pin, bool en) {
@@ -93,5 +119,74 @@ static inline void delayt3_put(PIO pio) {
 	pio->irq_force = 1<<0;
 }
 
+static inline void delayf1_program_init(PIO pio, uint sm, uint offset,
+		uint pin, bool en) {
+	pio_gpio_init(pio, pin);
+
+	pio_sm_set_consecutive_pindirs(pio, sm, pin, 1, true);
+
+	pio_sm_config c = delayf1_program_get_default_config(offset);
+	sm_config_set_out_pins(&c, pin, 1);
+	sm_config_set_set_pins(&c, pin, 1);
+	sm_config_set_sideset_pins(&c, pin);
+	//sm_config_set_in_shift(&c, false, true, 32);
+	sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_RX);
+
+	sm_config_set_clkdiv(&c, 1);
+
+	pio_sm_init(pio, sm, offset, &c);
+	pio_sm_set_enabled(pio, sm, en);
+}
+
+static inline void delayf2_program_init(PIO pio, uint sm, uint offset,
+		uint pin, bool en) {
+	pio_gpio_init(pio, pin);
+
+	pio_sm_set_consecutive_pindirs(pio, sm, pin, 1, true);
+
+	pio_sm_config c = delayf2_program_get_default_config(offset);
+	sm_config_set_out_pins(&c, pin, 1);
+	sm_config_set_set_pins(&c, pin, 1);
+	sm_config_set_sideset_pins(&c, pin);
+	sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_TX);
+
+	sm_config_set_clkdiv(&c, 1);
+
+	pio_sm_init(pio, sm, offset, &c);
+	pio_sm_set_enabled(pio, sm, en);
+}
+
+static inline void delayf_init_fifodma(PIO pio, uint smf1, uint smf2,
+		uint dmach, uint dmach2) {
+	static uint32_t countno = 1;
+
+	dma_channel_config c2 = dma_channel_get_default_config(dmach2);
+	channel_config_set_transfer_data_size(&c2, DMA_SIZE_32);
+	channel_config_set_read_increment(&c2, false);
+	channel_config_set_write_increment(&c2, false);
+	dma_channel_configure(dmach2, &c2,
+		&dma_hw->ch[dmach].al1_transfer_count_trig, // dma dst
+		&countno, // dma src
+		countno, // xfer count
+		false // don't trigger
+	);
+
+	dma_channel_config c = dma_channel_get_default_config(dmach);
+	channel_config_set_transfer_data_size(&c, DMA_SIZE_32);
+	channel_config_set_read_increment(&c, false);
+	channel_config_set_write_increment(&c, false);
+	channel_config_set_dreq(&c,
+			((pio == pio1_hw) ? DREQ_PIO1_RX0 : DREQ_PIO0_RX0) + smf1);
+	channel_config_set_chain_to(&c, dmach2);
+	dma_channel_configure(dmach, &c,
+		&pio->txf[smf2], // dma dst
+		&pio->rxf[smf1], // dma src
+		countno, // xfer count
+		true // trigger
+	);
+
+
+}
+
 %}
 
diff --git a/src/test/delaytest.c b/src/test/delaytest.c
index 894fcc4..4099c3e 100644
--- a/src/test/delaytest.c
+++ b/src/test/delaytest.c
@@ -2,6 +2,7 @@
 #include <stddef.h>
 #include <stdint.h>
 #include <stdbool.h>
+#include <stdio.h>
 
 #include <RP2040.h>
 #include <system_RP2040.h>
@@ -36,6 +37,8 @@ enum test {
 	test_core0_fifo_irq_wfi,
 	test_core0_wfe,
 
+	test_pio_fifo_dma,
+
 	test__num
 };
 
@@ -327,6 +330,36 @@ static void t_core0_fifo_irq_wfi(void) {
 		sio_hw->gpio_clr = 1<<PIN_TRIG_OUT;
 	}
 }
+
+
+__attribute__((__section__(".scratch_y.t_pio_fifo_dma")))
+static void t_pio_fifo_dma(void) {
+	uint off1 = pio_add_program(pio0, &delayf1_program);
+	uint off2 = pio_add_program(pio0, &delayf2_program);
+	uint dmach = dma_claim_unused_channel(true);
+	uint dmctl = dma_claim_unused_channel(true);
+
+	delayf1_program_init(pio0, 0, off1, PIN_HIGH    , false);
+	delayf2_program_init(pio0, 1, off2, PIN_TRIG_OUT, true );
+
+	delayf_init_fifodma(pio0, 0, 1, dmach, dmctl);
+
+	pio_sm_set_enabled(pio0, 0, true);
+	//gpio_put(PIN_HIGH, false);
+
+	for (int i = 0; ; ++i) {
+		/*uint32_t v=0;
+		while (!pio_sm_is_rx_fifo_empty(pio0, 0)) {
+			v = pio0->rxf[0];
+			pio0->txf[1] = v;
+		}
+		if (v==7)printf("rx[%d] %lu\r\n", i, v);*/
+		__WFI();
+	}
+}
+
+
+
 static test_fn tests[] = {
 	// delays: (units are ns, 40ns=1cyc@25MHz, so 200ns=5cyc)
 
@@ -432,6 +465,9 @@ static test_fn tests[] = {
 	// ==> 4 cycles irq->next insn after wfi
 	[test_core0_fifo_irq_wfi] = t_core0_fifo_irq_wfi,
 
+	// 240 cyc always
+	[test_pio_fifo_dma] = t_pio_fifo_dma,
+
 	[test__num] = NULL,
 };
 
@@ -460,7 +496,7 @@ void delaytest(void) {
 
 	SCB->SCR &= ~SCB_SCR_SEVONPEND_Msk;
 
-	const enum test t = test_pio_if_irq_handle;
+	const enum test t = test_pio_fifo_dma;
 
 	if (t <= test_core0_mem || t >= test_core0_wfe)
 		__disable_irq();
@@ -495,6 +531,6 @@ void delaytest(void) {
 			busy_wait_us_32(100);
 			irq_set_enabled(irq, true);*/
 		}
-	} else while (true) ;
+	} else while (true) __WFI();
 }