diff --git a/src/test/delay.pio b/src/test/delay.pio index 807caa3..41d541b 100644 --- a/src/test/delay.pio +++ b/src/test/delay.pio @@ -16,7 +16,7 @@ _start: .program delayt3 _start: - wait irq 0 + wait 1 irq 0 set pins, 1 [31] nop [31] set pins, 0 @@ -89,7 +89,8 @@ static inline void delayt3_program_init(PIO pio, uint sm, uint offset, } static inline void delayt3_put(PIO pio) { - hw_set_bits(&pio->irq_force, (1<<0)); + //hw_set_bits(&pio->irq_force, (1<<0)); + pio->irq_force = 1<<0; } %} diff --git a/src/test/delaytest.c b/src/test/delaytest.c index 4637adb..f73252f 100644 --- a/src/test/delaytest.c +++ b/src/test/delaytest.c @@ -195,7 +195,7 @@ static void t_pio_fifo(void) { delayt2_program_init(pio0, 0, off, PIN_TRIG_OUT, true); - const int gpio = PIN_TRIG_IN; + /*const int gpio = PIN_TRIG_IN; const int irq = IO_IRQ_BANK0; const int event = GPIO_IRQ_EDGE_RISE; @@ -204,17 +204,22 @@ static void t_pio_fifo(void) { irq_set_priority(irq, PICO_HIGHEST_IRQ_PRIORITY); hw_set_bits(&iobank0_hw->proc1_irq_ctrl.inte[gpio>>3], event << 4*(gpio&7)); __disable_irq(); - irq_set_enabled(irq, true); + irq_set_enabled(irq, true);*/ + gpio_put(PIN_TRIG_IN, false); + gpio_set_dir(PIN_TRIG_IN, GPIO_OUT); while (true) { - __WFI(); + sio_hw->gpio_set = 1<gpio_clr = 1<gpio_set = 1<intr[gpio>>3] = event << 4*(gpio&7); // acknowledge irq busy_wait_us_32(100); - irq_set_enabled(irq, true); - //sio_hw->gpio_clr = 1<proc1_irq_ctrl.inte[gpio>>3], event << 4*(gpio&7)); __disable_irq(); - irq_set_enabled(irq, true); + irq_set_enabled(irq, true);*/ + gpio_put(PIN_TRIG_IN, false); + gpio_set_dir(PIN_TRIG_IN, GPIO_OUT); while (true) { - __WFI(); + sio_hw->gpio_set = 1<gpio_clr = 1<gpio_set = 1<intr[gpio>>3] = event << 4*(gpio&7); // acknowledge irq busy_wait_us_32(100); - irq_set_enabled(irq, true); - //sio_hw->gpio_clr = 1< 1 cycle delay between fifo put & insn after pull exec + [test_pio_fifo] = t_pio_fifo, + // gpio hi then delayt3 put: (str | movs ldr str) 200 + // delay3 put then gpio hi: (str | str) 0 + // ==> 1 cycle delay between irq set & insn after wait exec [test_pio_irq ] = t_pio_irq, // these depend on core0 using a GPIO trigger using WFI, so this is a bit // more complicated. N_obsv = N_gpio_irq_wfi + N_core0 // => x_core0 = x_obsv - x_gpio_irq_wfi // => σ_core0 = sqrt(σ²_obsv - σ²_gpio_irq_wfi) + // + // actually no redo this, also with deterministic timings - // 740 660 680 640 580 640 740 660 700 640 - // 660 580 720 680 740 620 620 660 640 660 + //(740 660 680 640 580 640 740 660 700 640 + // 660 580 720 680 740 620 620 660 640 660) + // memwr then gpio hi: (movs str | str) + // 160 320 160 320 180 340 160 320 160 320 + // gpio hi then memwr: (str | movs str) + // 320 440 320 440 320 440 320 440 320 440 + // => loop is ldr; cmp; beq.n -> 5cyc (ahb) variation + // => movs str before TRIG_OUT hi (2cyc) + // ==> 3..8 cycles write->out of loop [test_core0_mem] = t_core0_mem, - // 520 540 540 540 560 560 540 520 560 540 - // 540 560 520 540 540 520 560 540 560 540 + //(520 540 540 540 560 560 540 520 560 540 + // 540 560 520 540 540 520 560 540 560 540) + // gpio hi then sev: (str | sev) 280 + // sev then gpio hi: (sev | str) 160 + // => 6 cycles sev->GPIO (wfe movs str) + // ==> 4 cycles sev->next insn after wfe [test_core0_wfe] = t_core0_wfe, - // 740 640 700 620 600 720 660 660 600 720 - // 560 660 600 680 660 580 740 560 700 700 + //(740 640 700 620 600 720 660 660 600 720 + // 560 660 600 680 660 580 740 560 700 700) + // gpio hi then fifo write: (str | movs str) + // 360 280 360 280 360 280 360 280 360 280 + // fifo write then gpio hi: (str | str) + // 360 280 360 280 360 280 360 280 360 280 + // => loop is ldr; test; beq.n -> 4cyc (sio) variation + // => movs str before TRIG_OUT hi (2cyc) + // ==> 3..7 cycles fifo->out of loop [test_core0_fifo_busyloop] = t_core0_fifo_busyloop, - // 1460 1480 1500 1480 1520 1500 1540 1520 1500 1500 - // 1540 1520 1520 1520 1520 1500 1540 1500 1500 1520 + //(1460 1480 1500 1480 1520 1500 1540 1520 1500 1500 + // 1540 1520 1520 1520 1520 1500 1540 1500 1500 1520) + // gpio hi then fifo write: (str | movs str) 1200 + // fifo write then gpio hi: (str | str) 1040 + // => 28 cycles irq->GPIO (push r4-r6,lr movs movs lsls lsls movs : 5+n cyc) + // ==> 18 cycles delay? (=> push timings?) [test_core0_fifo_irq_handle] = t_core0_fifo_irq_handle, - // 780 760 800 800 780 800 780 780 780 800 - // 800 760 800 800 800 820 780 780 800 780 + //(780 760 800 800 780 800 780 780 780 800 + // 800 760 800 800 800 820 780 780 800 780) + // gpio hi then fifo write: (str | movs str) 480 + // fifo write then gpio hi: (str | str) 320 + // => 7 cycles irq->GPIO (wfi movs movs str) + // ==> 4 cycles irq->next insn after wfi [test_core0_fifo_irq_wfi] = t_core0_fifo_irq_wfi, [test__num] = NULL, @@ -407,14 +454,14 @@ void delaytest(void) { SCB->SCR &= ~SCB_SCR_SEVONPEND_Msk; - const enum test t = test_pio_fifo; + const enum test t = test_core0_fifo_busyloop; if (t <= test_core0_mem || t >= test_core0_wfe) __disable_irq(); multicore_launch_core1(tests[t]); if (t >= test_core0_mem && t <= test_core0_wfe) { - const int gpio = PIN_TRIG_IN; + /*const int gpio = PIN_TRIG_IN; const int irq = IO_IRQ_BANK0; const int event = GPIO_IRQ_EDGE_RISE; @@ -423,15 +470,24 @@ void delaytest(void) { irq_set_priority(irq, PICO_HIGHEST_IRQ_PRIORITY); hw_set_bits(&iobank0_hw->proc0_irq_ctrl.inte[gpio>>3], event << 4*(gpio&7)); __disable_irq(); - irq_set_enabled(irq, true); + irq_set_enabled(irq, true);*/ + gpio_put(PIN_TRIG_IN, false); + gpio_set_dir(PIN_TRIG_IN, GPIO_OUT); while (true) { - __WFI(); + //asm volatile("nop"); sio_hw->fifo_wr = 1;//__SEV();//shvar = 1;// - irq_set_enabled(irq, false); + //asm volatile("nop"); + sio_hw->gpio_set = 1<gpio_clr = 1<intr[gpio>>3] = event << 4*(gpio&7); // acknowledge irq busy_wait_us_32(100); - irq_set_enabled(irq, true); + irq_set_enabled(irq, true);*/ } } else while (true) ;