stuff
This commit is contained in:
commit
008bbb95ab
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*.pdf
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*.html
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*.zip
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*.tar.gz
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# mdm isa reversing
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It looks quite a lot like the "sensor controller" ISA but the details differ
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(more registers, different encoding, no pc-relative branches, fewer insns?).
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## disassembler
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See `analyze-asm.py`. Needs a few tweaks to be usable as a standalone
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disassembler but it works.
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## documentation
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```
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instruction set (as of now):
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registers are 16-bit wide. notation is always "op src, dst".
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memory addressing is in 16-bit word units, never byte indexed.
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RAM/ROM and I/O buses are separate like in the 8080 or Z80.
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basically a babby's first 16bit machine one might find designed
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specifically for a uni course.
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alu reg, reg alu=or/and/mov/add/sub/cmp
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alu imm, reg imm is 5bit!
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btst imm, reg bit test in reg. imm is a bit index
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bclr imm, reg bit clear in reg
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shift reg, reg shift=sl0(lsl)/sr0(lsr)/srx(asr)
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shift imm, reg imm is 4bit
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lmd (reg), reg load from ROM/RAM space
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lmd imm, reg imm is 4bit? 7bit?
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lli imm, reg load long immediate(?), imm is 10bit
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b<cc> abs branch if conditioncode (eq/ne/mi/pl), abs is absolute addr
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jmp abs
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jmp (reg)
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jsr abs
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loop abs loop instruction. r0 = loop counter, branch if r0 != 0
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rts return
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wait wait for interrupt???
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input abs, reg read from I/O space (absolute address)
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output reg, abs write to I/O space
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outclr abs set I/O reg to 0?
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outset abs set I/O reg to 0xffff??
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outbclr imm, abs clear bit <imm> of I/O reg <abs>
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outbset imm, abs set bit of I/O reg
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reg encoding: 0XXXX = rX (X=0..15)
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10000 = pc (alu srcop only)
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others = ?? (alu srcop only)
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instruction set encoding maybe:
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instructions are always 16 bits wide
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000a aams ssss dddd ALU op; a=op, m=mode (src 0=reg/1=imm), s=src, d=dst
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000 or
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001 and
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010 xor? hypothetical
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011 tst? hypothetical
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100 mov
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101 add
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110 sub
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111 cmp
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0010 a??? ssss dddd bit op; a=op, ?=?, s=src(bitind imm), d=dst
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0010 btst
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1010 bclr
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^ reg/imm? depending on placement, unify with aluop or shiftop
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is there a bset somewhere?
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0011 aaam ssss dddd shift; a=op, m=reg/imm, s=src(bitind), d=dst
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000 sl0
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100 sr0
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110 srx
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others?
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0100 ccdd dddd dddd b<cc> d=dstabs
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00 eq
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01 ne
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10 mi
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11 pl
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^ maybe another cc bit?
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0110 aadd dddd dddd jmpop; d=abs
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00 jmp
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01 jsr
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10 loop
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11 misc reg-indirect insns (see below)
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0110 1100 0000 dddd jmp (d=reg)
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^^^^ other ops?
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? 0110 1101 ssss dddd ?? input (s=srcreg), d=dst hypothetical
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0110 1110 ssss dddd output s=src, (d=dstreg)
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0110 1111 ssss dddd lmd (s=srcreg), d=dst no store?
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0111 0000 0000 0000 rts
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0111 0001 0000 0000 wait
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^^^^ ^^^^ lots of space here for other ops!
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0111 0010 dddd dddd outclr d=dstabs
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0111 0011 dddd dddd outset d=dstabs
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0111 1sss ssss dddd lmd s=srcabs, d=dst no store?
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^^^ unsure of these (000 afaics)
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1000 ssss ssss dddd input s=srcabs, d=dst
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1001 dddd dddd ssss output s=srcreg, d=dstabs
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1010 dddd dddd ssss outbclr s=srcbitindimm, d=dstabs
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1011 dddd dddd ssss outbset s=srcbitindimm, d=dstabs
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11ss ssss ssss dddd lli s=src(imm), d=dst
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pseudo-ops:
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nop = or r0, r0
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```
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@ -0,0 +1,189 @@
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#!/usr/bin/env python3
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import sys
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from typing import *
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class InsnRec(NamedTuple):
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addr: int
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opcode: int
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insn: str
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args: str
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# special insns:
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# * DBG_PRINT0: lli+jsr
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# * DBG_FUNC: output+input+btst+bne+outbset+rts
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def get_ops(file):
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def aftersplit(st, sep, ind):
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a = st.split(sep, maxsplit=ind)
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if len(a) == 1: return a # sep not in st
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return a[ind:]
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with open(file, 'r') as f:
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for l in f.readlines():
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if len(l) == 0: continue
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nocomment = l.split(';', maxsplit=1)[0].strip()
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if len(nocomment) == 0: continue
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nolbl = ' '.join(x.strip() for x in aftersplit(nocomment, ':', 1))
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if len(nolbl) == 0: continue
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#print(nolbl)
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#op = nolbl.split(maxsplit=1)[0]#.lower()
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#print(op)
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spl = nolbl.split(maxsplit=1)
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#print(spl)
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yield spl
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def parse_hex(file):
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with open(file, 'r') as f:
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for l in f.readlines():
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if len(l) == 0: continue
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nocomment = l.split('#', maxsplit=1)[0].strip()
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if len(nocomment) == 0: continue
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for x in nocomment.split():
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yield int(x, 16)
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def join_asm(ops, hdt):
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hoff = 0
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for op in ops:
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if op[0] == '.ORG':
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continue # skip
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elif op[0] == 'DBG_PRINT0':
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yield InsnRec(hoff, hdt[hoff+0], "lli", op[1])
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yield InsnRec(hoff, hdt[hoff+1], "jsr", "_DBG_PRINT")
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hoff += 2
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elif op[0] == 'DBG_FUNC':
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yield InsnRec(hoff, hdt[hoff+0], "output", "r0, MCETRCCMD")
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yield InsnRec(hoff, hdt[hoff+1], "input", "MCETRCBUSY, r0")
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yield InsnRec(hoff, hdt[hoff+2], "btst", "0, r0")
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yield InsnRec(hoff, hdt[hoff+3], "bne", "_DBG_PRINT_WAIT")
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yield InsnRec(hoff, hdt[hoff+4], "outbset", "MCETRCSEND_SEND, MCETRCSEND")
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yield InsnRec(hoff, hdt[hoff+5], "rts", "")
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hoff += 6
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else:
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yield InsnRec(hoff, hdt[hoff], op[0], "" if len(op)==1 else op[1])
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hoff += 1
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assert hoff == len(hdt)
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def get_baseops(recs):
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d = dict()
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for r in recs:
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if r.insn == '.DATA': continue
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tup = d.get(r.insn, (0, 0xffff))
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d[r.insn] = (tup[0] | r.opcode, tup[1] & r.opcode)
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return d
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def decode(insn):
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REGS = [*["r%d"%x for x in range(16)], "pc", *["unk%d"%x for x in range(17,32)]]
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ALUOPS = ["or", "and", "xor?", "tst?", "mov", "add", "sub", "cmp"]
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assert insn == (insn & 0xffff), "insn %04x must be 16bit!"%insn
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op = insn >> 12
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# often used
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dreg = insn & 0xf
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dstabs = insn & 0x3ff
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if op == 0 or op == 1: # ALU op
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aluop = (insn >> 10) & 7
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src = (insn >> 4) & 0x1f
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mode = insn & (1 << 9)
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if mode == 0: # reg src
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return "%s %s, %s" % (ALUOPS[aluop], REGS[src], REGS[dreg])
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else: # imm src
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return "%s %d, %s" % (ALUOPS[aluop], src, REGS[dreg])
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elif op == 2: # bit op
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bitop = (insn >> 8) & 0xf
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src = (insn >> 4) & 0xf
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opstr = {0b0010: 'btst', 0b1010: 'bclr'}.get(bitop, "bitop_%x"%bitop)
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return "%s %d, %s" % (opstr, src, REGS[dreg])
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elif op == 3: # shift op
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shiftop = (insn >> 9) & 7
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src = (insn >> 4) & 0xf
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mode = insn & (1 << 8)
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opstr = {0: "sl0", 4: "sr0", 6: "srx"}.get(shiftop, "shiftop_%d"%shiftop)
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if mode == 0: # reg src
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return "%s %s, %s" % (opstr, REGS[src], REGS[dreg])
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else: # imm src
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return "%s %d, %s" % (opstr, src, REGS[dreg])
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elif op == 4 or op == 5: # b<cc> NEWCC?
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cc = (insn >> 10) & 7
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ccstr = ["eq","ne","mi","pl", *["CC%d"%x for x in range(4,8)]][cc]
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return "b%s 0x%04x" % (ccstr, dstabs)
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elif op == 6: # jmpop + reg-indirect
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if (insn & 0x0c00) == 0x0c00: # reg-indirect
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typ = (insn >> 8) & 3
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src = (insn >> 4) & 0xf
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if typ == 0: # jmp (reg)
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if src != 0:
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return "jmp_WUT %d, (%s)" % (src, REGS[dreg])
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else:
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return "jmp (%s)" % REGS[dreg]
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elif typ == 1: # input
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return "input (%s), %s" % (REGS[src], REGS[dreg])
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elif typ == 2: # output
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return "output %s, (%s)" % (REGS[src], REGS[dreg])
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elif typ == 3: # lmd
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return "lmd (%s), %s" % (REGS[src], REGS[dreg])
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else: assert False
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else: # jmpop
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typ = (insn >> 10) & 3
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typstr = {0: "jmp", 1: "jsr", 2: "loop"}[typ]
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return "%s 0x%04x" % (typstr, dstabs)
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elif op == 7: # misc
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if (insn & 0x0800) != 0: # lmd
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src = (insn >> 4) & 0x7f
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unsure = (src & 0x70) != 0
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return "lmd%s 0x%x, %s" % (("?" if unsure else ""), src, REGS[dreg])
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else: # outclr/outset/rts/wait
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subop = (insn >> 8) & 7
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dstabs &= 0xff
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if subop in (0,1):
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opstr = ["rts", "wait"][subop]
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return opstr if dstabs == 0 else ("%s? 0x%02x"%(opstr,dstabs))
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elif subop in (2,3):
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opstr = ["outclr", "outset"][subop-2]
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return "%s 0x%02x" % (opstr, dstabs)
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else:
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return "misc_abs %d, 0x%02x" % (subop, dstabs)
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elif op >= 8 and op < 0xc: # I/O
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src = (insn >> 4) & 0xff
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opstr = ["input", "output", "outbclr", "outbset"][op-8]
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if op == 8: # input
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return "%s 0x%02x, %s" % (opstr, src, REGS[dreg])
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else:
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return "%s %s, 0x%02x" % (opstr, (REGS[dreg] if op == 9 else str(dreg)), src)
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elif op >= 0xc and op <= 0xf: # lli
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src = (insn & 0x3ff0) >> 4
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return "lli 0x%x, %s" % (src, REGS[dreg])
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else:
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assert False, "Unknown opcode of insn %04x"%insn
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if __name__ == '__main__':
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assert len(sys.argv) > 2, ("Usage: %s <asm file> <hex file>" % sys.argv[0])
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ops = get_ops(sys.argv[1])
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#for x in ops: print(x[0])
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hdt = list(parse_hex(sys.argv[2]))
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#for x in hdt: print(hex(x))
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recs = join_asm(ops, hdt)
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#for x in recs: print("%04x:\t%04x\t%s\t%s"%x)
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#for k, v in get_baseops(recs).items():
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# print("%s\t(%04x, %04x)"%(k,*v))
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declen = 20
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for x in recs:
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dec = "" if x.insn == ".DATA" else decode(x.opcode)
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dec += (" "*max(declen-len(dec),0))
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print("%04x:\t%04x\t%s\t%s %s" % (x.addr, x.opcode, dec, x.insn, x.args))
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@ -0,0 +1,36 @@
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add (16bf, 1400)
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and (067f, 0400)
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cmp (1eff, 1c00)
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mov (13ff, 1000)
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nop (0000, 0000)
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or (0076, 0000)
|
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sub (1aff, 1800)
|
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|
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btst (22f3, 2200)
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bclr (2a73, 2a70)
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sl0 (31f7, 3100)
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sr0 (39f7, 3800)
|
||||
srx (3db6, 3d00)
|
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|
||||
lli (ffff, c000)
|
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|
||||
beq (43ff, 4000)
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bne (47ff, 4400)
|
||||
bmi (49e2, 49e2)
|
||||
bpl (4ff3, 4c80)
|
||||
|
||||
jmp (6fff, 6000)
|
||||
jsr (67ff, 6400)
|
||||
loop (6bff, 6800)
|
||||
|
||||
lmd (7fff, 6800)
|
||||
|
||||
rts (7000, 7000)
|
||||
wait (7100, 7100)
|
||||
|
||||
input (8fff, 8000)
|
||||
output (ffff, 0000)
|
||||
outclr (72ff, 7200)
|
||||
outset (7397, 7300)
|
||||
outbclr (a7ff, a000)
|
||||
outbset (bfff, b000)
|
||||
|
|
@ -0,0 +1,726 @@
|
|||
0000 .DATA 0x0000
|
||||
0000 .DATA 0x0000
|
||||
0000 .DATA 0x0000
|
||||
0000 .DATA 0x0000
|
||||
0000 .DATA 0x0000
|
||||
0000 .DATA 0x0000
|
||||
0000 .DATA 0x0000
|
||||
0000 .DATA 0x0000
|
||||
0000 .DATA 0x0000
|
||||
0000 .DATA 0x0000
|
||||
0000 .DATA 0x0000
|
||||
0000 .DATA 0x0000
|
||||
0000 .DATA 0x0000
|
||||
0000 .DATA 0x0000
|
||||
0001 .DATA 0x0001
|
||||
0003 .DATA 0x0003
|
||||
0007 .DATA 0x0007
|
||||
000f .DATA 0x000F
|
||||
0017 .DATA 0x0017
|
||||
003f .DATA 0x003F
|
||||
0043 .DATA 0x0043
|
||||
0050 .DATA 0x0050
|
||||
0054 .DATA 0x0054
|
||||
0080 .DATA 0x0080
|
||||
0082 .DATA 0x0082
|
||||
017f .DATA 0x017F
|
||||
0300 .DATA 0x0300
|
||||
0387 .DATA 0x0387
|
||||
0510 .DATA 0x0510
|
||||
0006 .DATA 0x06
|
||||
06f0 .DATA 0x06F0
|
||||
07ff .DATA 0x07FF
|
||||
0800 .DATA 0x0800
|
||||
091e .DATA 0x091E
|
||||
0c30 .DATA 0x0C30
|
||||
0fff .DATA 0x0FFF
|
||||
2fcf .DATA 0x2FCF
|
||||
3d1f .DATA 0x3D1F
|
||||
3f9d .DATA 0x3F9D
|
||||
4074 .DATA 0x4074
|
||||
5014 .DATA 0x5014
|
||||
8000 .DATA 0x8000
|
||||
8080 .DATA 0x8080
|
||||
aa00 .DATA 0xAA00
|
||||
c02f .DATA 0xC02F
|
||||
f800 .DATA 0xF800
|
||||
ff00 .DATA 0xFF00
|
||||
1611 add 1, r1
|
||||
1611 add 1, r1
|
||||
1612 add 1, r2
|
||||
1612 add 1, r2
|
||||
1613 add 1, r3
|
||||
1618 add 1, r8
|
||||
1618 add 1, r8
|
||||
161c add 1, r12
|
||||
1610 add 1,r0
|
||||
1630 add 3, r0
|
||||
1630 add 3,r0
|
||||
1401 add r0, r1
|
||||
1402 add r0, r2
|
||||
1404 add r0, r4
|
||||
14bc add r11, r12
|
||||
14bc add r11, r12
|
||||
1426 add r2, r6
|
||||
1426 add r2, r6
|
||||
1426 add r2, r6
|
||||
0620 and 2, r0
|
||||
0622 and 2, r2
|
||||
0633 and 3, r3
|
||||
063e and 3, r14
|
||||
0670 and 7, r0
|
||||
0410 and r1, r0
|
||||
0410 and r1,r0
|
||||
0410 and r1,r0
|
||||
0420 and r2, r0
|
||||
2a70 bclr 7, r0
|
||||
2a73 bclr 7, r3
|
||||
41a4 beq CAPT_FREQUENCY
|
||||
426a beq GEN_FSK_AVG_LEN_CORRECT
|
||||
427c beq GEN_FSK_DSBU_AVG_LEN_16_SYMBOLS_CHECK
|
||||
4289 beq GEN_FSK_DSBU_AVG_LEN_8_SYMBOLS
|
||||
41b8 beq IIR_K4
|
||||
41bf beq IIR_K8
|
||||
4166 beq LOOP_SAMPLES_FIFO_BLIND
|
||||
4173 beq LOOP_SAMPLES_FIFO_BLIND_DEMFRAC4WR
|
||||
417e beq LOOP_SAMPLES_FIFO_BLIND_DEMFRAC5WR
|
||||
4224 beq LOOP_SAMPLES_FIFO_SYNC
|
||||
4231 beq LOOP_SAMPLES_FIFO_SYNC_DEMFRAC4WR
|
||||
423c beq LOOP_SAMPLES_FIFO_SYNC_DEMFRAC5WR
|
||||
4199 beq LOOP_SAMPLES_TRANSPARENT_FIFO
|
||||
40bf beq MTX_Iqdump_Common_Preamble_16bitSyncWord
|
||||
40c9 beq MTX_Iqdump_Common_Preamble_RFESEND
|
||||
40ee beq MTX_Iqdump_Common_Preamble_Send_One_SW
|
||||
412e beq MTX_MFSK_SymbolLoop
|
||||
41c6 beq NO_IIR_FILTER
|
||||
40a0 beq ZERO_DONE
|
||||
49e2 bmi Neg_Sat
|
||||
45a4 bne CAPT_FREQUENCY
|
||||
45f3 bne DUMP_SAMPLES
|
||||
4618 bne DUMP_SAMPLES_FIFO
|
||||
457e bne LOOP_SAMPLES_FIFO_BLIND_DEMFRAC5WR
|
||||
463c bne LOOP_SAMPLES_FIFO_SYNC_DEMFRAC5WR
|
||||
44e2 bne MTX_Iqdump_Common_Preamble_Loop
|
||||
4526 bne MTX_MFSK_ToneLoop
|
||||
464c bne RFE_Started
|
||||
4572 bne TEST_PATTERN_ADD_BLIND
|
||||
4630 bne TEST_PATTERN_ADD_SYNC
|
||||
46d1 bne _DBG_PRINT_WAIT
|
||||
4eb3 bpl MRX_GenFSK_CommonEnd
|
||||
4eb3 bpl MRX_GenFSK_CommonEnd
|
||||
4eb3 bpl MRX_GenFSK_CommonEnd
|
||||
4cc1 bpl MTX_Iqdump_Common_Preamble_ShortSyncWord
|
||||
4de0 bpl Pos_Sat
|
||||
2200 btst 0, r0
|
||||
2200 btst 0, r0
|
||||
2201 btst 0, r1
|
||||
2201 btst 0, r1
|
||||
2201 btst 0, r1
|
||||
2201 btst 0, r1
|
||||
2210 btst 1, r0
|
||||
2210 btst 1, r0
|
||||
22f0 btst 15, r0
|
||||
2230 btst 3, r0
|
||||
2263 btst 6, r3
|
||||
2273 btst 7, r3
|
||||
2200 btst MCEEVENT2_C1BE_A_POS_PEAK, r0
|
||||
2200 btst MCEEVENT2_C1BE_A_POS_PEAK, r0
|
||||
1e04 cmp 0, r4
|
||||
1e04 cmp 0, r4
|
||||
1e04 cmp 0, r4
|
||||
1e09 cmp 0, r9
|
||||
1e09 cmp 0, r9
|
||||
1e0e cmp 0, r14
|
||||
1e20 cmp 2, r0
|
||||
1e22 cmp 2, r2
|
||||
1e2e cmp 2, r14
|
||||
1e3e cmp 3, r14
|
||||
1c01 cmp r0, r1
|
||||
1c03 cmp r0, r3
|
||||
1c10 cmp r1, r0
|
||||
1ca8 cmp r10, r8
|
||||
1ca8 cmp r10, r8
|
||||
1cd0 cmp r13, r0
|
||||
1ce0 cmp r14, r0
|
||||
1c4c cmp r4, r12
|
||||
1c4c cmp r4, r12
|
||||
1c4c cmp r4, r12
|
||||
8990 input BRMACC0, r0
|
||||
8980 input COUNT1RES, r0
|
||||
8980 input COUNT1RES, r0
|
||||
8982 input COUNT1RES, r2
|
||||
8982 input COUNT1RES, r2
|
||||
8984 input COUNT1RES, r4
|
||||
8984 input COUNT1RES, r4
|
||||
8440 input DEMC1BE0, r0
|
||||
8af0 input DEMFIFE2,r0
|
||||
8bf0 input DEMFRAC4, r0
|
||||
8bf0 input DEMFRAC4, r0
|
||||
8c00 input DEMFRAC5, r0
|
||||
8c00 input DEMFRAC5, r0
|
||||
8b54 input DEMLQIE0, r4
|
||||
8ab2 input DEMPDIF0, r2
|
||||
80b0 input MCEEVENT2, r0
|
||||
80b0 input MCEEVENT2, r0
|
||||
89f0 input MCETRCBUSY, r0
|
||||
8162 input MDMAPI, r2
|
||||
8170 input MDMCMDPAR0, r0
|
||||
8170 input MDMCMDPAR0, r0
|
||||
8170 input MDMCMDPAR0, r0
|
||||
8173 input MDMCMDPAR0, r3
|
||||
8184 input MDMCMDPAR1, r4
|
||||
8184 input MDMCMDPAR1, r4
|
||||
8184 input MDMCMDPAR1, r4
|
||||
8190 input MDMCMDPAR2, r0
|
||||
81d1 input MDMFIFORD, r1
|
||||
8210 input MDMFIFOSTA, r0
|
||||
8212 input MDMFIFOSTA, r2
|
||||
8c90 input MDMSPAR1, r0
|
||||
8ca1 input MDMSPAR2, r1
|
||||
8ca1 input MDMSPAR2, r1
|
||||
8ca1 input MDMSPAR2, r1
|
||||
8ca1 input MDMSPAR2, r1
|
||||
81b0 input MDMSTATUS, r0
|
||||
81b1 input MDMSTATUS, r1
|
||||
84a0 input MDMSYNC0, r0
|
||||
84a0 input MDMSYNC0, r0
|
||||
84a2 input MDMSYNC0, r2
|
||||
84b0 input MDMSYNC1, r0
|
||||
84b0 input MDMSYNC1, r0
|
||||
84b0 input MDMSYNC1, r0
|
||||
84b4 input MDMSYNC1, r4
|
||||
84c0 input MDMSYNC2, r0
|
||||
84c0 input MDMSYNC2, r0
|
||||
84d0 input MDMSYNC3, r0
|
||||
84d0 input MDMSYNC3, r0
|
||||
84d0 input MDMSYNC3, r0
|
||||
8630 input MODCTRL, r0
|
||||
8240 input RFERCEV, r0
|
||||
8230 input RFESEND, r0
|
||||
89ce input VITACCCTRL, r14
|
||||
6c01 jmp (r1)
|
||||
607d jmp CMD_OK_END
|
||||
607d jmp CMD_OK_END
|
||||
607d jmp CMD_OK_END
|
||||
607d jmp CMD_OK_END
|
||||
607d jmp CMD_OK_END
|
||||
6044 jmp CMD_PROC
|
||||
6295 jmp GEN_FSK_CALC_DEMSWIMBAL
|
||||
627e jmp GEN_FSK_DSBU_AVG_LEN_16_SYMBOLS
|
||||
61c7 jmp HARD_DECISION
|
||||
61c7 jmp HARD_DECISION
|
||||
61c7 jmp HARD_DECISION
|
||||
61fa jmp LOOP_SAMPLES
|
||||
6148 jmp LOOP_SAMPLES_BLIND
|
||||
6166 jmp LOOP_SAMPLES_FIFO_BLIND
|
||||
6224 jmp LOOP_SAMPLES_FIFO_SYNC
|
||||
6199 jmp LOOP_SAMPLES_TRANSPARENT_FIFO
|
||||
6088 jmp MCFG_Entry
|
||||
6088 jmp MCFG_Entry
|
||||
6088 jmp MCFG_Entry
|
||||
6088 jmp MCFG_Entry
|
||||
6088 jmp MCFG_Entry
|
||||
6088 jmp MCFG_Entry
|
||||
6087 jmp MNOP_Entry
|
||||
6087 jmp MNOP_Entry
|
||||
6087 jmp MNOP_Entry
|
||||
6087 jmp MNOP_Entry
|
||||
6087 jmp MNOP_Entry
|
||||
6087 jmp MNOP_Entry
|
||||
6087 jmp MNOP_Entry
|
||||
6087 jmp MNOP_Entry
|
||||
6087 jmp MNOP_Entry
|
||||
6087 jmp MNOP_Entry
|
||||
6087 jmp MNOP_Entry
|
||||
6087 jmp MNOP_Entry
|
||||
6087 jmp MNOP_Entry
|
||||
6087 jmp MNOP_Entry
|
||||
6087 jmp MNOP_Entry
|
||||
6087 jmp MNOP_Entry
|
||||
6087 jmp MNOP_Entry
|
||||
6087 jmp MNOP_Entry
|
||||
6087 jmp MNOP_Entry
|
||||
6087 jmp MNOP_Entry
|
||||
6087 jmp MNOP_Entry
|
||||
6087 jmp MNOP_Entry
|
||||
6087 jmp MNOP_Entry
|
||||
6087 jmp MNOP_Entry
|
||||
6087 jmp MNOP_Entry
|
||||
614e jmp MRX_Entry_FIFO_BLIND
|
||||
614e jmp MRX_Entry_FIFO_BLIND
|
||||
6200 jmp MRX_Entry_FIFO_SYNC
|
||||
613e jmp MRX_Entry_REG_BLIND
|
||||
61e4 jmp MRX_Entry_REG_SYNC
|
||||
6186 jmp MRX_Entry_TRANSPARENT_FIFO
|
||||
6244 jmp MRX_SETUP
|
||||
6104 jmp MTX_Entry
|
||||
6104 jmp MTX_Entry
|
||||
6104 jmp MTX_Entry
|
||||
6104 jmp MTX_Entry
|
||||
6104 jmp MTX_Entry
|
||||
60c9 jmp MTX_Iqdump_Common_Preamble_RFESEND
|
||||
60c9 jmp MTX_Iqdump_Common_Preamble_RFESEND
|
||||
6112 jmp MTX_MFSK
|
||||
6030 jmp START_PROCESS
|
||||
61ee jmp SYNC_SEARCH
|
||||
6213 jmp SYNC_SEARCH_FIFO
|
||||
65d0 jsr MDMFIFOWR_AND_WAIT10
|
||||
65d0 jsr MDMFIFOWR_AND_WAIT10
|
||||
65d0 jsr MDMFIFOWR_AND_WAIT10
|
||||
65d0 jsr MDMFIFOWR_AND_WAIT10
|
||||
66ca jsr MODCTRL_CLR
|
||||
66ca jsr MODCTRL_CLR
|
||||
6644 jsr MRX_SETUP
|
||||
6644 jsr MRX_SETUP
|
||||
6644 jsr MRX_SETUP
|
||||
6644 jsr MRX_SETUP
|
||||
6644 jsr MRX_SETUP
|
||||
64a5 jsr MTX_Iqdump_Common_Preamble
|
||||
64f5 jsr MTX_Iqdump_Termination
|
||||
64f5 jsr MTX_Iqdump_Termination
|
||||
65d9 jsr SignExt_and_Saturate
|
||||
65d9 jsr SignExt_and_Saturate
|
||||
65d9 jsr SignExt_and_Saturate
|
||||
65d9 jsr SignExt_and_Saturate
|
||||
66d0 jsr _DBG_PRINT
|
||||
66d0 jsr _DBG_PRINT
|
||||
66d0 jsr _DBG_PRINT
|
||||
66d0 jsr _DBG_PRINT
|
||||
66d0 jsr _DBG_PRINT
|
||||
66d0 jsr _DBG_PRINT
|
||||
66d0 jsr _DBG_PRINT
|
||||
66d0 jsr _DBG_PRINT
|
||||
66d0 jsr _DBG_PRINT
|
||||
66d0 jsr _DBG_PRINT
|
||||
66d0 jsr _DBG_PRINT
|
||||
66d0 jsr _DBG_PRINT
|
||||
66d0 jsr _DBG_PRINT
|
||||
66d0 jsr _DBG_PRINT
|
||||
66d0 jsr _DBG_PRINT
|
||||
c080 lli "########################### Blind REGISTER MODE -> IQ Dump starting at once ########################"
|
||||
c090 lli "########################### Blind RFC FIFO Mode -> IQ Dump starting at once (DataRate <= 12,5 kbps) ########################"
|
||||
c0a0 lli "########################### Transparent FIFO Mode -> PDIFF streaming starting at once ########################"
|
||||
c0b0 lli "########################### Transparent FIFO Mode Stop AGC ########################"
|
||||
c0c0 lli "########################### IQ Dump REGISTER MODE, RX started, Wait for Sync ########################"
|
||||
c0d0 lli "########################### Sync Found REGISTER MODE -> IQ Dump starting ########################"
|
||||
c0e0 lli "########################### IQ Dump through RFC FIFO, RX started, Wait for Sync (DataRate <= 12.5 kbps) ########################"
|
||||
c0f0 lli "########################### Sync Found RFC FIFO MODE-> IQ samples through FIFO starting ########################"
|
||||
c100 lli "########################### RX Started ########################"
|
||||
c110 lli "All bits received, MCE Ending"
|
||||
c040 lli "IQDump___ NoFEC, TX Started"
|
||||
c050 lli "IQDump___ Multi-level FSK TX Mode"
|
||||
c030 lli "MCFG - IQ Dump Configuration"
|
||||
c060 lli "Starting MFSK Symbol Loop"
|
||||
c070 lli "Stopping MFSK Symbol Loop"
|
||||
c000 lli 0x0, r0
|
||||
c000 lli 0x0, r0
|
||||
c030 lli 0x03, r0
|
||||
c030 lli 0x03,r0
|
||||
c040 lli 0x04, r0
|
||||
c100 lli 0x10, r0
|
||||
ffc0 lli 0x3FC, r0
|
||||
c801 lli 0x80, r1
|
||||
cd90 lli 0xD9, r0
|
||||
c0b0 lli 11, r0
|
||||
c0f3 lli 15, r3
|
||||
c0f5 lli 15, r5
|
||||
c100 lli 16, r0
|
||||
c100 lli 16, r0
|
||||
c020 lli 2, r0
|
||||
c18b lli 24, r11
|
||||
c18b lli 24, r11
|
||||
c035 lli 3, r5
|
||||
c035 lli 3, r5
|
||||
c035 lli 3, r5
|
||||
c035 lli 3, r5
|
||||
c1f2 lli 31, r2
|
||||
c200 lli 32, r0
|
||||
c050 lli 5, r0
|
||||
c050 lli 5, r0
|
||||
c4f2 lli DEMFB2P0, r2
|
||||
c0c1 lli MDMCONF_IQDUMP, r1
|
||||
c2b2 lli MDMCONF_IQDUMP_FIRST_REG, r2
|
||||
c4e0 lli MDMCONF_IQDUMP_LAST_REG, r0
|
||||
c750 lli VITCTRL, r0
|
||||
6f13 lmd (r1), r3
|
||||
78a0 lmd CORR_DEFG_THR, r0
|
||||
7842 lmd DEMC1BE0_MASKA_BITS, r2
|
||||
7810 lmd DEMENABLE0_RX_IQDUMP, r0
|
||||
7820 lmd DEMENABLE1_RX_IQDUMP, r0
|
||||
7851 lmd IQDUMP_MASK_BITS_15_8, r1
|
||||
7851 lmd IQDUMP_MASK_BITS_15_8, r1
|
||||
787d lmd IQDUMP_MAX_POS_VAL, r13
|
||||
787d lmd IQDUMP_MAX_POS_VAL, r13
|
||||
788e lmd IQDUMP_MIN_NEG_VAL, r14
|
||||
788e lmd IQDUMP_MIN_NEG_VAL, r14
|
||||
786a lmd IQDUMP_TEST_MAX_VAL, r10
|
||||
786a lmd IQDUMP_TEST_MAX_VAL, r10
|
||||
789d lmd TRANSPARENT_CAPT, r13
|
||||
78b0 lmd TX_TONE_COUNT, r0
|
||||
7830 lmd VITACCCTRL_REG_DEFAULT,r0
|
||||
69d2 loop LOOP_MDMFIFOWR
|
||||
6960 loop LOOP_SAMPLES_FIFO_BLIND_WAIT
|
||||
6a20 loop LOOP_SAMPLES_FIFO_SYNC_WAIT
|
||||
6992 loop LOOP_SAMPLES_TRANSPARENT_FIFO_WAIT
|
||||
688e loop MCFG_Iqdump_Loop
|
||||
68bc loop MTX_Iqdump_Common_Preamble_SyncWord_ShiftLoop1
|
||||
68c7 loop MTX_Iqdump_Common_Preamble_SyncWord_ShiftLoop2
|
||||
689d loop ZERO_LOOP
|
||||
1200 mov 0, r0
|
||||
1202 mov 0, r2
|
||||
1203 mov 0, r3
|
||||
1204 mov 0, r4
|
||||
1205 mov 0, r5
|
||||
1208 mov 0, r8
|
||||
1208 mov 0, r8
|
||||
120c mov 0, r12
|
||||
120c mov 0, r12
|
||||
120c mov 0, r12
|
||||
13f0 mov 0x1F, r0
|
||||
13f3 mov 0x1F, r3
|
||||
13f3 mov 0x1F, r3
|
||||
1218 mov 1, r8
|
||||
1218 mov 1, r8
|
||||
1220 mov 2, r0
|
||||
1210 mov CMD_OK, r0
|
||||
1101 mov pc, r1
|
||||
1000 mov r0, r0
|
||||
1000 mov r0, r0
|
||||
1000 mov r0, r0
|
||||
1001 mov r0, r1
|
||||
1001 mov r0, r1
|
||||
1003 mov r0, r3
|
||||
1013 mov r1, r3
|
||||
1015 mov r1, r5
|
||||
10a9 mov r10, r9
|
||||
10a9 mov r10, r9
|
||||
10a9 mov r10, r9
|
||||
10a9 mov r10, r9
|
||||
10d0 mov r13, r0
|
||||
10e0 mov r14, r0
|
||||
1020 mov r2, r0
|
||||
1021 mov r2, r1
|
||||
1026 mov r2, r6
|
||||
1030 mov r3, r0
|
||||
1056 mov r5, r6
|
||||
1056 mov r5, r6
|
||||
1056 mov r5, r6
|
||||
1065 mov r6, r5
|
||||
1065 mov r6, r5
|
||||
1065 mov r6, r5
|
||||
1080 mov r8, r0
|
||||
1080 mov r8, r0
|
||||
1090 mov r9, r0
|
||||
1090 mov r9, r0
|
||||
0000 nop
|
||||
0000 nop
|
||||
0000 nop
|
||||
0004 or r0,r4
|
||||
0010 or r1, r0
|
||||
0012 or r1, r2
|
||||
0020 or r2, r0
|
||||
0020 or r2, r0
|
||||
0042 or r4, r2
|
||||
a230 outbclr 0, RFESEND
|
||||
a235 outbclr 5, RFESEND
|
||||
a35d outbclr DEMMISC2_MLSERUN,DEMMISC2
|
||||
a4e5 outbclr DEMSWQU0_RUN, DEMSWQU0
|
||||
a0d2 outbclr MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0
|
||||
a0d2 outbclr MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0
|
||||
a0d2 outbclr MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0
|
||||
a0d2 outbclr MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0
|
||||
a0d2 outbclr MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0
|
||||
a0d2 outbclr MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0
|
||||
a0d3 outbclr MCEEVENT0_FIFO_ERR_UNDERFLOW, MCEEVENTMSK0
|
||||
a0d0 outbclr MCEEVENT0_MDMAPI_WR, MCEEVENTMSK0
|
||||
a0d5 outbclr MCEEVENT0_RFECMD_IRQ, MCEEVENTMSK0
|
||||
a0d1 outbclr MCEEVENT0_TIMER_IRQ, MCEEVENTMSK0
|
||||
a0d1 outbclr MCEEVENT0_TIMER_IRQ, MCEEVENTMSK0
|
||||
a0e1 outbclr MCEEVENT1_CLKEN_BAUD, MCEEVENTMSK1
|
||||
a0e8 outbclr MCEEVENT1_RAT_EVENT0, MCEEVENTMSK1
|
||||
a0e8 outbclr MCEEVENT1_RAT_EVENT0, MCEEVENTMSK1
|
||||
a0f0 outbclr MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTMSK2
|
||||
a0f0 outbclr MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTMSK2
|
||||
a0f0 outbclr MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTMSK2
|
||||
a0f0 outbclr MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTMSK2
|
||||
a0f0 outbclr MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTMSK2
|
||||
a0f0 outbclr MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTMSK2
|
||||
a0f0 outbclr MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTMSK2
|
||||
a0f3 outbclr MCEEVENT2_C1BE_B_POS_PEAK, MCEEVENTMSK2
|
||||
a0f3 outbclr MCEEVENT2_C1BE_B_POS_PEAK, MCEEVENTMSK2
|
||||
a0f3 outbclr MCEEVENT2_C1BE_B_POS_PEAK, MCEEVENTMSK2
|
||||
a0f3 outbclr MCEEVENT2_C1BE_B_POS_PEAK, MCEEVENTMSK2
|
||||
a0f3 outbclr MCEEVENT2_C1BE_B_POS_PEAK, MCEEVENTMSK2
|
||||
a008 outbclr MDMENABLE_FB2PLL, MDMENABLE
|
||||
a003 outbclr MDMENABLE_MODULATOR, MDMENABLE
|
||||
a002 outbclr MDMENABLE_TIMEBASE, MDMENABLE
|
||||
a630 outbclr MODCTRL_PREAMBLEINSERT, MODCTRL
|
||||
a634 outbclr MODCTRL_SOFTTXENABLE, MODCTRL
|
||||
b070 outbset 0, MCESTROBES0
|
||||
b230 outbset 0,RFESEND
|
||||
b230 outbset 0,RFESEND
|
||||
b231 outbset 1, RFESEND
|
||||
b231 outbset 1, RFESEND
|
||||
b231 outbset 1, RFESEND
|
||||
b235 outbset 5, RFESEND
|
||||
b0d2 outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0
|
||||
b0d2 outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0
|
||||
b0d2 outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0
|
||||
b0d2 outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0
|
||||
b0d2 outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0
|
||||
b112 outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTCLR0
|
||||
b112 outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTCLR0
|
||||
b112 outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTCLR0
|
||||
b112 outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTCLR0
|
||||
b112 outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTCLR0
|
||||
b112 outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTCLR0
|
||||
b112 outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTCLR0
|
||||
b112 outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTCLR0
|
||||
b112 outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTCLR0
|
||||
b112 outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTCLR0
|
||||
b118 outbset MCEEVENT0_CPEFWEVENT0, MCEEVENTCLR0
|
||||
b0d3 outbset MCEEVENT0_FIFO_ERR_UNDERFLOW, MCEEVENTMSK0
|
||||
b113 outbset MCEEVENT0_FIFO_ERR_UNDERFLOW, MCEEVENTCLR0
|
||||
b0d0 outbset MCEEVENT0_MDMAPI_WR, MCEEVENTMSK0
|
||||
b110 outbset MCEEVENT0_MDMAPI_WR, MCEEVENTCLR0
|
||||
b0d5 outbset MCEEVENT0_RFECMD_IRQ, MCEEVENTMSK0
|
||||
b115 outbset MCEEVENT0_RFECMD_IRQ, MCEEVENTCLR0
|
||||
b0d1 outbset MCEEVENT0_TIMER_IRQ, MCEEVENTMSK0
|
||||
b0d1 outbset MCEEVENT0_TIMER_IRQ, MCEEVENTMSK0
|
||||
b111 outbset MCEEVENT0_TIMER_IRQ, MCEEVENTCLR0
|
||||
b111 outbset MCEEVENT0_TIMER_IRQ, MCEEVENTCLR0
|
||||
b111 outbset MCEEVENT0_TIMER_IRQ, MCEEVENTCLR0
|
||||
b111 outbset MCEEVENT0_TIMER_IRQ, MCEEVENTCLR0
|
||||
b0e1 outbset MCEEVENT1_CLKEN_BAUD, MCEEVENTMSK1
|
||||
b121 outbset MCEEVENT1_CLKEN_BAUD, MCEEVENTCLR1
|
||||
b121 outbset MCEEVENT1_CLKEN_BAUD, MCEEVENTCLR1
|
||||
b121 outbset MCEEVENT1_CLKEN_BAUD, MCEEVENTCLR1
|
||||
b0e0 outbset MCEEVENT1_PREAMBLE_DONE, MCEEVENTMSK1
|
||||
b0e0 outbset MCEEVENT1_PREAMBLE_DONE, MCEEVENTMSK1
|
||||
b120 outbset MCEEVENT1_PREAMBLE_DONE, MCEEVENTCLR1
|
||||
b120 outbset MCEEVENT1_PREAMBLE_DONE, MCEEVENTCLR1
|
||||
b120 outbset MCEEVENT1_PREAMBLE_DONE, MCEEVENTCLR1
|
||||
b120 outbset MCEEVENT1_PREAMBLE_DONE, MCEEVENTCLR1
|
||||
b0e8 outbset MCEEVENT1_RAT_EVENT0, MCEEVENTMSK1
|
||||
b0e8 outbset MCEEVENT1_RAT_EVENT0, MCEEVENTMSK1
|
||||
b128 outbset MCEEVENT1_RAT_EVENT0, MCEEVENTCLR1
|
||||
b128 outbset MCEEVENT1_RAT_EVENT0, MCEEVENTCLR1
|
||||
b0f0 outbset MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTMSK2
|
||||
b0f0 outbset MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTMSK2
|
||||
b130 outbset MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTCLR2
|
||||
b130 outbset MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTCLR2
|
||||
b130 outbset MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTCLR2
|
||||
b130 outbset MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTCLR2
|
||||
b074 outbset MCESTROBES0_EVENT0, MCESTROBES0
|
||||
b074 outbset MCESTROBES0_EVENT0, MCESTROBES0
|
||||
b074 outbset MCESTROBES0_EVENT0, MCESTROBES0
|
||||
b074 outbset MCESTROBES0_EVENT0, MCESTROBES0
|
||||
b074 outbset MCESTROBES0_EVENT0, MCESTROBES0
|
||||
b9e0 outbset MCETRCSEND_SEND, MCETRCSEND
|
||||
b006 outbset MDMENABLE_ADCDIG, MDMENABLE
|
||||
b004 outbset MDMENABLE_DEMODULATOR, MDMENABLE
|
||||
b008 outbset MDMENABLE_FB2PLL, MDMENABLE
|
||||
b003 outbset MDMENABLE_MODULATOR, MDMENABLE
|
||||
b003 outbset MDMENABLE_MODULATOR, MDMENABLE
|
||||
b002 outbset MDMENABLE_TIMEBASE, MDMENABLE
|
||||
b002 outbset MDMENABLE_TIMEBASE, MDMENABLE
|
||||
b002 outbset MDMENABLE_TIMEBASE, MDMENABLE
|
||||
b016 outbset MDMINIT_ADCDIG, MDMINIT
|
||||
b014 outbset MDMINIT_DEMODULATOR, MDMINIT
|
||||
b013 outbset MDMINIT_MODULATOR, MDMINIT
|
||||
b013 outbset MDMINIT_MODULATOR, MDMINIT
|
||||
b012 outbset MDMINIT_TIMEBASE, MDMINIT
|
||||
b012 outbset MDMINIT_TIMEBASE, MDMINIT
|
||||
b012 outbset MDMINIT_TIMEBASE, MDMINIT
|
||||
b63c outbset MODCTRL_CDC_COL_RESTART, MODCTRL
|
||||
b633 outbset MODCTRL_FECENABLE, MODCTRL
|
||||
b630 outbset MODCTRL_PREAMBLEINSERT, MODCTRL
|
||||
b634 outbset MODCTRL_SOFTTXENABLE, MODCTRL
|
||||
ba3c outbset RDCAPT0_DEMLQIE0, RDCAPT0
|
||||
ba38 outbset RDCAPT0_DEMPDIF0, RDCAPT0
|
||||
ba38 outbset RDCAPT0_DEMPDIF0, RDCAPT0
|
||||
b910 outbset TIMCTRL_ENABLETIMER, TIMCTRL
|
||||
7203 outclr DEMENABLE0
|
||||
7204 outclr DEMENABLE1
|
||||
720d outclr MCEEVENTMSK0
|
||||
720e outclr MCEEVENTMSK1
|
||||
720f outclr MCEEVENTMSK2
|
||||
7210 outclr MCEEVENTMSK3
|
||||
7206 outclr MDMENABLE_ADCDIG, MDMENABLE
|
||||
7204 outclr MDMENABLE_DEMODULATOR, MDMENABLE
|
||||
7202 outclr MDMENABLE_TIMEBASE, MDMENABLE
|
||||
721e outclr MDMFIFOWRCTRL
|
||||
721b outclr MDMSTATUS
|
||||
7263 outclr MODCTRL
|
||||
722c outclr MODPRECTRL
|
||||
7223 outclr RFESEND
|
||||
7223 outclr RFESEND
|
||||
7291 outclr TIMCTRL
|
||||
7291 outclr TIMCTRL
|
||||
7291 outclr TIMCTRL
|
||||
7291 outclr TIMCTRL
|
||||
9010 output r0, MDMINIT
|
||||
9030 output r0, DEMENABLE0
|
||||
9040 output r0, DEMENABLE1
|
||||
9050 output r0, DEMINIT0
|
||||
9060 output r0, DEMINIT1
|
||||
9170 output r0, MDMCMDPAR0
|
||||
91b0 output r0, MDMSTATUS
|
||||
91e0 output r0, MDMFIFOWRCTRL
|
||||
91e0 output r0, MDMFIFOWRCTRL
|
||||
91f0 output r0, MDMFIFORDCTRL
|
||||
91f0 output r0, MDMFIFORDCTRL
|
||||
92c0 output r0, MODPRECTRL
|
||||
92f0 output r0, MODSOFTTX
|
||||
9380 output r0, DEMDSBU
|
||||
9440 output r0, DEMC1BE0
|
||||
9480 output r0, DEMC1BE11
|
||||
9490 output r0, DEMC1BE12
|
||||
9590 output r0, DEMC1BEREF0
|
||||
95a0 output r0, DEMC1BEREF1
|
||||
95b0 output r0, DEMC1BEREF2
|
||||
95c0 output r0, DEMC1BEREF3
|
||||
9630 output r0, MODCTRL
|
||||
9640 output r0, MODPREAMBLE
|
||||
9910 output r0, TIMCTRL
|
||||
9930 output r0, TIMPERIOD
|
||||
9930 output r0, TIMPERIOD
|
||||
9970 output r0, COUNT1IN
|
||||
9970 output r0, COUNT1IN
|
||||
9970 output r0, COUNT1IN
|
||||
9970 output r0, COUNT1IN
|
||||
9970 output r0, COUNT1IN
|
||||
9970 output r0, COUNT1IN
|
||||
9990 output r0, BRMACC0
|
||||
9a00 output r0, MCETRCCMD
|
||||
99c0 output r0,VITACCCTRL
|
||||
91c1 output r1, MDMFIFOWR
|
||||
92f1 output r1, MODSOFTTX
|
||||
9a3d output r13, RDCAPT0
|
||||
9642 output r2, MODPREAMBLE
|
||||
9722 output r2, DEMSWIMBAL
|
||||
6e23 output r3, (r2)
|
||||
6e23 output r3, (r2)
|
||||
92c3 output r3, MODPRECTRL
|
||||
94e3 output r3, DEMSWQU0
|
||||
91b4 output r4, MDMSTATUS
|
||||
9644 output r4, MODPREAMBLE
|
||||
92c5 output r5, MODPRECTRL
|
||||
9b75 output r5, RDCAPT1
|
||||
9b75 output r5, RDCAPT1
|
||||
9b75 output r5, RDCAPT1
|
||||
9b75 output r5, RDCAPT1
|
||||
91c6 output r6, MDMFIFOWR
|
||||
7303 outset DEMENABLE0
|
||||
7304 outset DEMENABLE1
|
||||
7305 outset DEMINIT0
|
||||
7305 outset DEMINIT0
|
||||
7306 outset DEMINIT1
|
||||
7306 outset DEMINIT1
|
||||
7311 outset MCEEVENTCLR0
|
||||
7311 outset MCEEVENTCLR0
|
||||
7311 outset MCEEVENTCLR0
|
||||
7311 outset MCEEVENTCLR0
|
||||
7311 outset MCEEVENTCLR0
|
||||
7311 outset MCEEVENTCLR0
|
||||
7311 outset MCEEVENTCLR0
|
||||
7311 outset MCEEVENTCLR0
|
||||
7312 outset MCEEVENTCLR1
|
||||
7312 outset MCEEVENTCLR1
|
||||
7312 outset MCEEVENTCLR1
|
||||
7312 outset MCEEVENTCLR1
|
||||
7312 outset MCEEVENTCLR1
|
||||
7312 outset MCEEVENTCLR1
|
||||
7312 outset MCEEVENTCLR1
|
||||
7312 outset MCEEVENTCLR1
|
||||
7313 outset MCEEVENTCLR2
|
||||
7391 outset TIMCTRL
|
||||
7391 outset TIMCTRL
|
||||
7000 rts
|
||||
7000 rts
|
||||
7000 rts
|
||||
7000 rts
|
||||
7000 rts
|
||||
7000 rts
|
||||
7000 rts
|
||||
7000 rts
|
||||
7000 rts
|
||||
3126 sl0 2, r6
|
||||
3130 sl0 3, r0
|
||||
3136 sl0 3, r6
|
||||
3151 sl0 5, r1
|
||||
3151 sl0 5, r1
|
||||
3152 sl0 5, r2
|
||||
3154 sl0 5, r4
|
||||
3150 sl0 5,r0
|
||||
3180 sl0 8, r0
|
||||
3180 sl0 8, r0
|
||||
3182 sl0 8, r2
|
||||
3182 sl0 8, r2
|
||||
3184 sl0 8, r4
|
||||
3184 sl0 8, r4
|
||||
3162 sl0 DEMC1BE0_MASKA, r2
|
||||
3911 sr0 1, r1
|
||||
3912 sr0 1, r2
|
||||
3914 sr0 1, r4
|
||||
3924 sr0 2, r4
|
||||
3930 sr0 3,r0
|
||||
3952 sr0 5, r2
|
||||
3963 sr0 6, r3
|
||||
3976 sr0 7, r6
|
||||
3980 sr0 8, r0
|
||||
3982 sr0 8, r2
|
||||
3983 sr0 8, r3
|
||||
3832 sr0 r3, r2
|
||||
3834 sr0 r3, r4
|
||||
3d16 srx 1, r6
|
||||
3d26 srx 2, r6
|
||||
3d30 srx 3, r0
|
||||
3d36 srx 3, r6
|
||||
3d80 srx 8, r0
|
||||
3d82 srx 8, r2
|
||||
1a10 sub 1, r0
|
||||
1a10 sub 1, r0
|
||||
1a13 sub 1, r3
|
||||
1a15 sub 1, r5
|
||||
1a19 sub 1, r9
|
||||
1a19 sub 1, r9
|
||||
1a42 sub 4, r2
|
||||
1a44 sub 4, r4
|
||||
1a80 sub 8, r0
|
||||
1a80 sub 8, r0
|
||||
1a82 sub 8, r2
|
||||
1a84 sub 8, r4
|
||||
1802 sub r0, r2
|
||||
1803 sub r0, r3
|
||||
1820 sub r2,r0
|
||||
1820 sub r2,r0
|
||||
1830 sub r3, r0
|
||||
1832 sub r3, r2
|
||||
1850 sub r5, r0
|
||||
1856 sub r5,r6
|
||||
1856 sub r5,r6
|
||||
7100 wait
|
||||
7100 wait
|
||||
7100 wait
|
||||
7100 wait
|
||||
7100 wait
|
||||
7100 wait
|
||||
7100 wait
|
||||
7100 wait
|
||||
7100 wait
|
||||
7100 wait
|
||||
7100 wait
|
||||
7100 wait
|
||||
7100 wait
|
||||
7100 wait
|
||||
7100 wait
|
||||
7100 wait
|
||||
7100 wait
|
||||
7100 wait
|
||||
7100 wait
|
||||
7100 wait
|
||||
7100 wait
|
||||
7100 wait
|
||||
7100 wait
|
||||
7100 wait
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,405 @@
|
|||
# grouped by words, words are in msnyb..lsnyb notation
|
||||
|
||||
# jmp START_PROCESS
|
||||
6030
|
||||
|
||||
# START OF LMD_DATA_SPACE
|
||||
2fcf
|
||||
3f9d 0001
|
||||
003f ff00
|
||||
0fff 07ff
|
||||
f800 0300
|
||||
8080 0006
|
||||
# END OF LMD_DATA_SPACE
|
||||
# START OF MDMCONF_IQDUMP
|
||||
0003 0017
|
||||
3d1f 0000
|
||||
0000 0800
|
||||
000f 0000
|
||||
0387 0000
|
||||
4074 0043
|
||||
8000 0082
|
||||
0080 06f0
|
||||
0000 091e
|
||||
0510 0054
|
||||
0007 0000
|
||||
5014 0050
|
||||
0000 c02f
|
||||
0c30 017f
|
||||
0000 0000
|
||||
0000 0000
|
||||
0000 0000
|
||||
aa00 0000
|
||||
# END OF MDMCONF_IQDUMP
|
||||
|
||||
# start of code
|
||||
|
||||
# START_PROCESS
|
||||
7223 66ca
|
||||
a35d a4e5
|
||||
7303 7305
|
||||
7203 7304
|
||||
7306 7204
|
||||
7391 7291
|
||||
b008 ffc0
|
||||
9010 a008
|
||||
720d 720e
|
||||
720f 7210
|
||||
# CMD_PROC (FALLTHRU)
|
||||
b0d0 7100
|
||||
b110 a0d0
|
||||
721b 8162
|
||||
1020 3952
|
||||
0670 0020
|
||||
1630 1101
|
||||
1401 6c01
|
||||
6087 6088
|
||||
6104 613e
|
||||
6087 6087
|
||||
6087 6087
|
||||
6087 6088
|
||||
6104 61e4
|
||||
6087 6087
|
||||
6087 6087
|
||||
6087 6088
|
||||
6104 614e
|
||||
6087 6087
|
||||
6087 6087
|
||||
6087 6088
|
||||
6104 6200
|
||||
6087 6087
|
||||
6087 6087
|
||||
6087 6088
|
||||
6104 6186
|
||||
6087 6087
|
||||
6087 6087
|
||||
6088 6112
|
||||
614e
|
||||
# CMD_PROC end
|
||||
|
||||
# CMD_OK_END
|
||||
1210
|
||||
# CPE_NOTIFY
|
||||
7223 7311
|
||||
7312 7313
|
||||
81b1 0010
|
||||
91b0 b070
|
||||
6044
|
||||
# MNOP_ENTRY
|
||||
607d
|
||||
# MCFG_ENTRY
|
||||
c030 66d0
|
||||
c0c1 c2b2
|
||||
c4e0 1820
|
||||
6f13 6e23
|
||||
1611 1612
|
||||
688e 7830
|
||||
99c0 78a0
|
||||
9480 9490
|
||||
c4f2 c750
|
||||
1820 40a0
|
||||
1203 6e23
|
||||
1612 689d
|
||||
78b0 9990
|
||||
7263 b63c
|
||||
607d
|
||||
# MTX_Iqdump_Common_Preamble
|
||||
8190
|
||||
9640 8170
|
||||
3980 2a70
|
||||
1001 1611
|
||||
84a2 84b4
|
||||
c0f3 c0f5
|
||||
c200 1c01
|
||||
40c9 c100
|
||||
1c10 40bf
|
||||
4cc1 1013
|
||||
1803 1830
|
||||
1a13 1a10
|
||||
3912 68bc
|
||||
60c9 13f3
|
||||
60c9 13f3
|
||||
1015 c100
|
||||
1850 1a15
|
||||
1a10 3914
|
||||
68c7 b0e8
|
||||
7100 b128
|
||||
a0e8 b230
|
||||
b910 8990
|
||||
9930 b111
|
||||
b0d1 7100
|
||||
b002 b012
|
||||
b111 a0d1
|
||||
7291 b630
|
||||
b003 b013
|
||||
722c b0e0
|
||||
7100 b120
|
||||
8170 92c0
|
||||
7100 b120
|
||||
8170 22f0
|
||||
44e2 13f0
|
||||
1c03 40ee
|
||||
92c3 9642
|
||||
7100 b120
|
||||
92c5 9644
|
||||
7100 b120
|
||||
b0e0 a630
|
||||
7000
|
||||
# MTX_Iqdump_Termination
|
||||
a0e1
|
||||
c030 9910
|
||||
c040 9930
|
||||
b111 b0d1
|
||||
7100 b111
|
||||
a0d1 7291
|
||||
a003 a002
|
||||
a230 7000
|
||||
# MTX_Entry
|
||||
7311 7312
|
||||
c040 66d0
|
||||
c100 91f0
|
||||
64a5 b633
|
||||
b113 b0d3
|
||||
7100 a0d3
|
||||
64f5 607d
|
||||
# MTX_MFSK
|
||||
7311 7312
|
||||
c050 66d0
|
||||
c030 91f0
|
||||
b634 b0e8
|
||||
7100 b128
|
||||
a0e8 b230
|
||||
b002 b012
|
||||
b003 b013
|
||||
1200 92f0
|
||||
b121 b0e1
|
||||
7100 b121
|
||||
8210 0620
|
||||
1e20 4526
|
||||
c060 66d0
|
||||
7100 b121
|
||||
81d1 92f1
|
||||
0000 0000
|
||||
0000 8212
|
||||
0622 1e22
|
||||
412e c070
|
||||
66d0 a634
|
||||
64f5 607d
|
||||
# MRX_Entry_REG_BLIND
|
||||
a0d2 a0f0
|
||||
a0f3 7311
|
||||
7312 6644
|
||||
c080 66d0
|
||||
b0d2 c035
|
||||
7100 9b75
|
||||
ba38 b074
|
||||
b112 6148
|
||||
# MRX_Entry_FIFO_BLIND
|
||||
a0d2 a0f0
|
||||
a0f3 7311
|
||||
7312 6644
|
||||
c18b c000
|
||||
91e0 120c
|
||||
1218 786a
|
||||
787d 788e
|
||||
10a9 b074
|
||||
b0d2 c050
|
||||
b112 7100
|
||||
6960 c090
|
||||
66d0 c035
|
||||
b112 7100
|
||||
9b75 8bf0
|
||||
65d9 8ca1
|
||||
2201 4173
|
||||
1080 1ca8
|
||||
4572 1208
|
||||
1618 65d0
|
||||
8c00 65d9
|
||||
8ca1 2201
|
||||
417e 1090
|
||||
1a19 1e09
|
||||
457e 10a9
|
||||
65d0 8184
|
||||
1e04 4166
|
||||
14bc 1c4c
|
||||
4eb3 6166
|
||||
# MRX_Entry_TRANSPARENT_FIFO
|
||||
a0d2 a0f0
|
||||
a0f3 7311
|
||||
7312 6644
|
||||
721e 120c
|
||||
1205 b074
|
||||
b0d2 c050
|
||||
b112 7100
|
||||
6992 c0a0
|
||||
66d0 789d
|
||||
89ce b112
|
||||
7100 8c90
|
||||
2200 41a4
|
||||
8230 2210
|
||||
45a4 b231
|
||||
c0b0 66d0
|
||||
9a3d 8ab2
|
||||
3182 3d82
|
||||
8af0 3180
|
||||
3d80 1802
|
||||
063e 1e0e
|
||||
41c6 1e2e
|
||||
41b8 1e3e
|
||||
41bf 1056
|
||||
1426 3d16
|
||||
1065 61c7
|
||||
1056 3126
|
||||
1856 1426
|
||||
3d26 1065
|
||||
61c7 1056
|
||||
3136 1856
|
||||
1426 3d36
|
||||
1065 61c7
|
||||
1026 3976
|
||||
91c6 8184
|
||||
1e04 4199
|
||||
161c 1c4c
|
||||
4eb3 6199
|
||||
# MDMFIFOWR_AND_WAIT10
|
||||
1001 c0b0
|
||||
91c1 3911
|
||||
1000 1000
|
||||
1000 69d2
|
||||
7000
|
||||
# SignExt_and_saturate
|
||||
3130
|
||||
3d30 1cd0
|
||||
4de0 1ce0
|
||||
49e2 7000
|
||||
10d0 7000
|
||||
10e0 7000
|
||||
# MRX_Entry_REG_SYNC
|
||||
c0c0 66d0
|
||||
a0d2 a0f0
|
||||
a0f3 7311
|
||||
7312 6644
|
||||
b130 b0f0
|
||||
7100 80b0
|
||||
2200 45f3
|
||||
61ee b231
|
||||
c0d0 66d0
|
||||
b130 a0f0
|
||||
b0d2 c035
|
||||
7100 9b75
|
||||
ba38 b074
|
||||
b112 61fa
|
||||
# MRX_Entry_FIFO_SYNC
|
||||
c0e0 66d0
|
||||
a0d2 a0f0
|
||||
a0f3 7311
|
||||
7312 6644
|
||||
c18b c000
|
||||
91e0 120c
|
||||
1218 786a
|
||||
787d 788e
|
||||
10a9 b130
|
||||
b0f0 7100
|
||||
80b0 2200
|
||||
4618 6213
|
||||
b074 b231
|
||||
c0f0 66d0
|
||||
b130 a0f0
|
||||
b0d2 c020
|
||||
b112 7100
|
||||
6a20 c035
|
||||
b112 7100
|
||||
9b75 8bf0
|
||||
65d9 8ca1
|
||||
2201 4231
|
||||
1080 1ca8
|
||||
4630 1208
|
||||
1618 65d0
|
||||
8c00 65d9
|
||||
8ca1 2201
|
||||
423c 1090
|
||||
1a19 1e09
|
||||
463c 10a9
|
||||
65d0 8184
|
||||
1e04 4224
|
||||
14bc 1c4c
|
||||
4eb3 6224
|
||||
# MRX_SETUP
|
||||
8240 2230
|
||||
464c b0d5
|
||||
7100 b115
|
||||
a0d5 6244
|
||||
# RFE_Started
|
||||
c100 66d0
|
||||
b118 b006
|
||||
b016 b004
|
||||
b014 b002
|
||||
b012 8440
|
||||
7842 0420
|
||||
8173 3983
|
||||
2a73 94e3
|
||||
c1f2 1832
|
||||
3162 1021
|
||||
3151 0012
|
||||
0020 9440
|
||||
1030 1610
|
||||
3930 2210
|
||||
426a 1220
|
||||
3150 1003
|
||||
3180 1630
|
||||
9380 1202
|
||||
1204 2273
|
||||
427c 84a0
|
||||
9970 8982
|
||||
1a82 84c0
|
||||
9970 8984
|
||||
1a84 627e
|
||||
2263 4289
|
||||
84b0 9970
|
||||
8980 1a80
|
||||
1402 84d0
|
||||
9970 8980
|
||||
1a80 1404
|
||||
6295 84b0
|
||||
7851 0410
|
||||
9970 8982
|
||||
1a42 84d0
|
||||
7851 0410
|
||||
9970 8984
|
||||
1a44 3152
|
||||
3154 3963
|
||||
0633 1613
|
||||
3832 3834
|
||||
3182 3982
|
||||
3184 0042
|
||||
9722 84a0
|
||||
9590 84b0
|
||||
95a0 84c0
|
||||
95b0 84d0
|
||||
95c0 7810
|
||||
9030 9050
|
||||
7820 9040
|
||||
9060 b235
|
||||
cd90 9170
|
||||
7000
|
||||
# MRX_GenFSK_CommonEnd
|
||||
a235
|
||||
b112 7100
|
||||
a0d2 b112
|
||||
ba3c 81b0
|
||||
8b54 3924
|
||||
3184 0004
|
||||
91b4 c110
|
||||
66d0 7391
|
||||
7291 66ca
|
||||
7206 7202
|
||||
7204 7305
|
||||
7306 607d
|
||||
# MODCTRL_CLR
|
||||
8630 c801
|
||||
3151 0410
|
||||
9630 7000
|
||||
# DBG_FUNC
|
||||
9a00 89f0
|
||||
2200 46d1
|
||||
b9e0 7000
|
||||
Loading…
Reference in New Issue