BLAHAJ
/
ccmdm-re
10
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
ccmdm-re/defs.h

1796 lines
88 KiB
C
Raw Permalink Blame History

; vim: set ft=asm:
.DEFINE CMD_OK 1
.DEFINE CMD_ERR 2
.DEFINE MDMCONF_IQDUMP_FIRST_REG 43 ; ADCDIGCONF
.DEFINE MDMCONF_IQDUMP_LAST_REG 78 ; DEMSWQU0
;;; Length of configuration (number of .DATA words)
.DEFINE MDMCONF_IQDUMP_LENGTH 36
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;; mce_commonlib.asm
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; --------------------------------------------------------------
; MCEEVENT0 event register bit positions
;
.DEFINE MCEEVENT0_MDMAPI_WR 0 ; New command from CPE received in MDMAPI register
.DEFINE MCEEVENT0_TIMER_IRQ 1 ; Timer period expired in local timer
.DEFINE MCEEVENT0_CLKEN_4BAUD 2 ; Clock enable event at 4 times baud rate
.DEFINE MCEEVENT0_FIFO_ERR_UNDERFLOW 3 ; FIFO underflow error event
.DEFINE MCEEVENT0_FIFO_ERR_OVERFLOW 4 ; FIFO overflow error event
.DEFINE MCEEVENT0_RFECMD_IRQ 5 ; New command from RFE received in MCERCEV register
.DEFINE MCEEVENT0_COUNTER_IRQ 6 ; Counter value reached in local timer
.DEFINE MCEEVENT0_MDMFIFO_WR 7 ; A write to the MDMFIFO register from CPE
.DEFINE MCEEVENT0_CPEFWEVENT0 8 ; Firmware defined event from CPE
.DEFINE MCEEVENT0_CPEFWEVENT1 9 ; Firmware defined event from CPE
.DEFINE MCEEVENT0_BDEC_EN 10 ; BDEC output enable
.DEFINE MCEEVENT0_FRAC_EN 11 ; FRAC output enable
.DEFINE MCEEVENT0_DL_TX_DONE 12 ; SMI serdes data word transmit done
.DEFINE MCEEVENT0_CL_TX_DONE 13 ; SMI serdes command word transmit done
.DEFINE MCEEVENT0_DL_RX_IRQ 14 ; SMI serdes data word receive interrupt
.DEFINE MCEEVENT0_CL_RX_IRQ 15 ; SMI serdes command word receive interrupt
; --------------------------------------------------------------
; MCEEVENT1 event register bit positions
;
.DEFINE MCEEVENT1_PREAMBLE_DONE 0 ; Preamble done interrupt from modulator
.DEFINE MCEEVENT1_CLKEN_BAUD 1 ; Baud indication
.DEFINE MCEEVENT1_FIFOWR_READY 2 ; It is legal to write to MDMFIFOWR register
.DEFINE MCEEVENT1_FIFORD_VALID 3 ; It is leval to read from MDMFIFORD register
.DEFINE MCEEVENT1_VITACC 4 ; Unused event
.DEFINE MCEEVENT1_MDMCMDPAR0_WR 5 ; A write to MDMCMDPAR0 register from CPE
.DEFINE MCEEVENT1_MDMCMDPAR1_WR 6 ; A write to MDMCMDPAR1 register from CPE
.DEFINE MCEEVENT1_CLKEN_BAUD_F 7 ; Flushed Baud Indication
.DEFINE MCEEVENT1_RAT_EVENT0 8 ; Radio timer event 0
.DEFINE MCEEVENT1_RAT_EVENT1 9 ; Radio timer event 1
.DEFINE MCEEVENT1_RAT_EVENT2 10 ; Radio timer event 2
.DEFINE MCEEVENT1_RAT_EVENT3 11 ; Radio timer event 3
.DEFINE MCEEVENT1_RAT_EVENT4 12 ; Radio timer event 4
.DEFINE MCEEVENT1_RAT_EVENT5 13 ; Radio timer event 5
.DEFINE MCEEVENT1_RAT_EVENT6 14 ; Radio timer event 6
.DEFINE MCEEVENT1_RAT_EVENT7 15 ; Radio timer event 7
; --------------------------------------------------------------
; MCEEVENT2 event register bit positions
;
.DEFINE MCEEVENT2_C1BE_A_POS_PEAK 0 ; Correlator peak detect: corr A > thr A (occurs one sample after peak)
.DEFINE MCEEVENT2_C1BE_A_NEG_PEAK 1 ; Correlator peak detect: corr A < -thr A (occurs one sample after peak)
.DEFINE MCEEVENT2_C1BE_A_ANY_PEAK 2 ; Correlator peak detect: abs(corr A) > thr A (occurs one sample after peak)
.DEFINE MCEEVENT2_C1BE_B_POS_PEAK 3 ; Correlator peak detect: corr B > thr B (occurs one sample after peak)
.DEFINE MCEEVENT2_C1BE_B_NEG_PEAK 4 ; Correlator peak detect: corr B < -thr B (occurs one sample after peak)
.DEFINE MCEEVENT2_C1BE_B_ANY_PEAK 5 ; Correlator peak detect: abs(corr B) > thr B (occurs one sample after peak)
.DEFINE MCEEVENT2_C1BE_C_POS_PEAK 6 ; Correlator peak detect: corr C > thr C (occurs one sample after peak)
.DEFINE MCEEVENT2_C1BE_C_NEG_PEAK 7 ; Correlator peak detect: corr C < -thr C (occurs one sample after peak)
.DEFINE MCEEVENT2_C1BE_C_ANY_PEAK 8 ; Correlator peak detect: abs(corr C) > thr C (occurs one sample after peak)
.DEFINE MCEEVENT2_C1BE_CMB_POS_PEAK 9 ; Correlator peak detect: corr CMB > thr CMB (occurs one sample after peak)
.DEFINE MCEEVENT2_C1BE_CMB_NEG_PEAK 10 ; Correlator peak detect: corr CMB < -thr CMB (occurs one sample after peak)
.DEFINE MCEEVENT2_C1BE_CMB_ANY_PEAK 11 ; Correlator peak detect: abs(corr CMB) > thr CMB (occurs one sample after peak)
.DEFINE MCEEVENT2_C1BE_B_LOADED 12 ; Correlator B loaded (by auto-copy function)
.DEFINE MCEEVENT2_SWQU_SYNCED_IRQ 13 ; Sync word qualifier detected sync word
.DEFINE MCEEVENT2_MDMGPI0 14 ; Event from RFCore GPI 0
.DEFINE MCEEVENT2_MDMGPI1 15 ; Event from RFCore GPI 1
; --------------------------------------------------------------
; MCEEVENT3 event register bit positions
;
.DEFINE MCEEVENT3_C1BE_D_POS_PEAK 0 ; Correlator peak detect: corr A > thr A (occurs one sample after peak)
.DEFINE MCEEVENT3_C1BE_D_NEG_PEAK 1 ; Correlator peak detect: corr A < -thr A (occurs one sample after peak)
.DEFINE MCEEVENT3_C1BE_D_ANY_PEAK 2 ; Correlator peak detect: abs(corr A) > thr A (occurs one sample after peak)
.DEFINE MCEEVENT3_C1BE_E_POS_PEAK 3 ; Correlator peak detect: corr B > thr B (occurs one sample after peak)
.DEFINE MCEEVENT3_C1BE_E_NEG_PEAK 4 ; Correlator peak detect: corr B < -thr B (occurs one sample after peak)
.DEFINE MCEEVENT3_C1BE_E_ANY_PEAK 5 ; Correlator peak detect: abs(corr B) > thr B (occurs one sample after peak)
.DEFINE MCEEVENT3_C1BE_F_POS_PEAK 6 ; Correlator peak detect: corr C > thr C (occurs one sample after peak)
.DEFINE MCEEVENT3_C1BE_F_NEG_PEAK 7 ; Correlator peak detect: corr C < -thr C (occurs one sample after peak)
.DEFINE MCEEVENT3_C1BE_F_ANY_PEAK 8 ; Correlator peak detect: abs(corr C) > thr C (occurs one sample after peak)
.DEFINE MCEEVENT3_C1BE_CMB_DE_POS_PEAK 9 ; Correlator peak detect: corr CMB > thr CMB (occurs one sample after peak)
.DEFINE MCEEVENT3_C1BE_CMB_DE_NEG_PEAK 10 ; Correlator peak detect: corr CMB < -thr CMB (occurs one sample after peak)
.DEFINE MCEEVENT3_C1BE_CMB_DE_ANY_PEAK 11 ; Correlator peak detect: abs(corr CMB) > thr CMB (occurs one sample after peak)
.DEFINE MCEEVENT3_C1BE_G_POS_PEAK 12 ; Correlator peak detect: corr G > thr G
.DEFINE MCEEVENT3_C1BE_G_NEG_PEAK 13 ; Correlator peak detect: corr G < -thr G
.DEFINE MCEEVENT3_C1BE_G_ANY_PEAK 14 ; Correlator peak detect: abs(corr G) > thr G
.DEFINE MCEEVENT3_SWQU_FALSE_SYNC_IRQ 15 ; Sync owrd qualifier false sync
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;; mdm_regs.asm
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; --------------------------------------------------------------
; MDMENABLE
;
MDMENABLE .assign 0
MDMENABLE_PDIF2 .assign 11 ;
MDMENABLE_PHASECORR .assign 10 ;
MDMENABLE_HILBDISC .assign 9 ;
MDMENABLE_FB2PLL .assign 8 ;
MDMENABLE_VITACC .assign 7 ;
MDMENABLE_ADCDIG .assign 6 ;
MDMENABLE_SMI .assign 5 ;
MDMENABLE_DEMODULATOR .assign 4 ;
MDMENABLE_MODULATOR .assign 3 ;
MDMENABLE_TIMEBASE .assign 2 ;
MDMENABLE_TXRXFIFO .assign 1 ;
MDMENABLE_mce .assign 0 ;
; --------------------------------------------------------------
; MDMINIT
;
MDMINIT .assign 1
MDMINIT_PDIF2 .assign 11 ;
MDMINIT_PHASECORR .assign 10 ;
MDMINIT_HILBDISC .assign 9 ;
MDMINIT_FB2PLL .assign 8 ;
MDMINIT_VITACC .assign 7 ;
MDMINIT_ADCDIG .assign 6 ;
MDMINIT_SMI .assign 5 ;
MDMINIT_DEMODULATOR .assign 4 ;
MDMINIT_MODULATOR .assign 3 ;
MDMINIT_TIMEBASE .assign 2 ;
MDMINIT_TXRXFIFO .assign 1 ;
MDMINIT_mce .assign 0 ;
; --------------------------------------------------------------
; MDMPDREQ
;
MDMPDREQ .assign 2
MDMPDREQ_mcePDREQ .assign 0 ;
; --------------------------------------------------------------
; DEMENABLE0
;
DEMENABLE0 .assign 3
DEMENABLE0_FE23 .assign 15 ;
DEMENABLE0_FE13 .assign 14 ;
DEMENABLE0_FELP .assign 13 ;
DEMENABLE0_THRD .assign 12 ;
DEMENABLE0_FRAC .assign 11 ;
DEMENABLE0_FIDC .assign 10 ;
DEMENABLE0_CHFI .assign 9 ;
DEMENABLE0_BDEC .assign 8 ;
DEMENABLE0_IQMC .assign 7 ;
DEMENABLE0_MGE2 .assign 6 ;
DEMENABLE0_MGE1 .assign 5 ;
DEMENABLE0_RSVD .assign 4 ;
DEMENABLE0_CODC .assign 3 ;
DEMENABLE0_CMI4 .assign 2 ;
DEMENABLE0_CMIX .assign 1 ;
DEMENABLE0_HILB .assign 0 ;
; --------------------------------------------------------------
; DEMENABLE1
;
DEMENABLE1 .assign 4
DEMENABLE1_VITE .assign 15 ;
DEMENABLE1_MLSE .assign 14 ;
DEMENABLE1_SOFD .assign 13 ;
DEMENABLE1_SWQU .assign 12 ;
DEMENABLE1_MAFC .assign 11 ;
DEMENABLE1_MAFI .assign 10 ;
DEMENABLE1_FIFE .assign 9 ;
DEMENABLE1_PDIF .assign 8 ;
DEMENABLE1_CA2P .assign 7 ;
DEMENABLE1_FECP .assign 6 ;
DEMENABLE1_FEC5 .assign 5 ;
DEMENABLE1_C1BE .assign 4 ;
DEMENABLE1_LQIE .assign 3 ;
DEMENABLE1_F4BA .assign 2 ;
DEMENABLE1_STIM .assign 1 ;
DEMENABLE1_DSBU .assign 0 ;
; --------------------------------------------------------------
; DEMINIT0
;
DEMINIT0 .assign 5
DEMINIT0_FE23 .assign 15 ;
DEMINIT0_FE13 .assign 14 ;
DEMINIT0_FELP .assign 13 ;
DEMINIT0_THRD .assign 12 ;
DEMINIT0_FRAC .assign 11 ;
DEMINIT0_FIDC .assign 10 ;
DEMINIT0_CHFI .assign 9 ;
DEMINIT0_BDEC .assign 8 ;
DEMINIT0_IQMC .assign 7 ;
DEMINIT0_MGE2 .assign 6 ;
DEMINIT0_MGE1 .assign 5 ;
DEMINIT0_RSVD .assign 4 ;
DEMINIT0_CODC .assign 3 ;
DEMINIT0_CMI4 .assign 2 ;
DEMINIT0_CMIX .assign 1 ;
DEMINIT0_HILB .assign 0 ;
; --------------------------------------------------------------
; DEMINIT1
;
DEMINIT1 .assign 6
DEMINIT1_VITE .assign 15 ;
DEMINIT1_MLSE .assign 14 ;
DEMINIT1_SOFD .assign 13 ;
DEMINIT1_SWQU .assign 12 ;
DEMINIT1_MAFC .assign 11 ;
DEMINIT1_MAFI .assign 10 ;
DEMINIT1_FIFE .assign 9 ;
DEMINIT1_PDIF .assign 8 ;
DEMINIT1_CA2P .assign 7 ;
DEMINIT1_FECP .assign 6 ;
DEMINIT1_FEC5 .assign 5 ;
DEMINIT1_C1BE .assign 4 ;
DEMINIT1_LQIE .assign 3 ;
DEMINIT1_F4BA .assign 2 ;
DEMINIT1_STIM .assign 1 ;
DEMINIT1_DSBU .assign 0 ;
; --------------------------------------------------------------
; MCESTROBES0
;
MCESTROBES0 .assign 7
MCESTROBES0_EVENT5 .assign 12 ;
MCESTROBES0_EVENT4 .assign 11 ;
MCESTROBES0_ROMDUMP .assign 10 ;
MCESTROBES0_VITACCSTART .assign 9 ;
MCESTROBES0_MLSETERM .assign 8 ;
MCESTROBES0_EVENT3 .assign 7 ;
MCESTROBES0_EVENT2 .assign 6 ;
MCESTROBES0_EVENT1 .assign 5 ;
MCESTROBES0_EVENT0 .assign 4 ;
MCESTROBES0_MCETIMBALIGN .assign 3 ;
MCESTROBES0_DSBURESTART .assign 2 ;
MCESTROBES0_RSVD .assign 1 ;
MCESTROBES0_CMDDONE .assign 0 ;
; --------------------------------------------------------------
; MCESTROBES1
;
MCESTROBES1 .assign 8
MCESTROBES1_C1BECOPYCMD2 .assign 15 ;
MCESTROBES1_C1BEPEAKGCMD .assign 14 ;
MCESTROBES1_C1BEPEAKDECMD .assign 13 ;
MCESTROBES1_C1BEPEAKFCMD .assign 12 ;
MCESTROBES1_C1BEPEAKECMD .assign 11 ;
MCESTROBES1_C1BEPEAKDCMD .assign 10 ;
MCESTROBES1_C1BEPEAKABCMD .assign 9 ;
MCESTROBES1_C1BEPEAKCCMD .assign 8 ;
MCESTROBES1_C1BEPEAKBCMD .assign 7 ;
MCESTROBES1_C1BEPEAKACMD .assign 6 ;
MCESTROBES1_C1BEADVANCECMD .assign 5 ;
MCESTROBES1_C1BESTALLCMD .assign 4 ;
MCESTROBES1_C1BEROTCMD .assign 2 ;
MCESTROBES1_C1BECOPYCMD .assign 1 ;
MCESTROBES1_RESERVED .assign 0 ;
; --------------------------------------------------------------
; MCEEVENT0
;
MCEEVENT0 .assign 9
MCEEVENT0_CL_RX_IRQ .assign 15 ;
MCEEVENT0_DL_RX_IRQ .assign 14 ;
MCEEVENT0_CL_TX_DONE .assign 13 ;
MCEEVENT0_DL_TX_DONE .assign 12 ;
MCEEVENT0_FRAC_EN .assign 11 ;
MCEEVENT0_BDEC_EN .assign 10 ;
MCEEVENT0_CPEFWEVENT1 .assign 9 ;
MCEEVENT0_CPEFWEVENT0 .assign 8 ;
MCEEVENT0_MDMFIFO_WR .assign 7 ;
MCEEVENT0_COUNTER_IRQ .assign 6 ;
MCEEVENT0_RFECMD_IRQ .assign 5 ;
MCEEVENT0_FIFO_ERR_OVERFLOW .assign 4 ;
MCEEVENT0_FIFO_ERR_UNDERFLOW .assign 3 ;
MCEEVENT0_CLKEN_4BAUD .assign 2 ;
MCEEVENT0_TIMER_IRQ .assign 1 ;
MCEEVENT0_MDMAPI_WR .assign 0 ;
; --------------------------------------------------------------
; MCEEVENT1
;
MCEEVENT1 .assign 10
MCEEVENT1_RAT_EVENT7 .assign 15 ;
MCEEVENT1_RAT_EVENT6 .assign 14 ;
MCEEVENT1_RAT_EVENT5 .assign 13 ;
MCEEVENT1_RAT_EVENT4 .assign 12 ;
MCEEVENT1_RAT_EVENT3 .assign 11 ;
MCEEVENT1_RAT_EVENT2 .assign 10 ;
MCEEVENT1_RAT_EVENT1 .assign 9 ;
MCEEVENT1_RAT_EVENT0 .assign 8 ;
MCEEVENT1_CLKEN_BAUD_F .assign 7 ;
MCEEVENT1_MDMCMDPAR1_WR .assign 6 ;
MCEEVENT1_MDMCMDPAR0_WR .assign 5 ;
MCEEVENT1_VITACC .assign 4 ;
MCEEVENT1_FIFORD_VALID .assign 3 ;
MCEEVENT1_FIFOWR_READY .assign 2 ;
MCEEVENT1_CLKEN_BAUD .assign 1 ;
MCEEVENT1_PREAMBLE_DONE .assign 0 ;
; --------------------------------------------------------------
; MCEEVENT2
;
MCEEVENT2 .assign 11
MCEEVENT2_MDMGPI1 .assign 15 ;
MCEEVENT2_MDMGPI0 .assign 14 ;
MCEEVENT2_SWQU_SYNCED_IRQ .assign 13 ;
MCEEVENT2_C1BE_B_LOADED .assign 12 ;
MCEEVENT2_C1BE_CMB_ANY_PEAK .assign 11 ;
MCEEVENT2_C1BE_CMB_NEG_PEAK .assign 10 ;
MCEEVENT2_C1BE_CMB_POS_PEAK .assign 9 ;
MCEEVENT2_C1BE_C_ANY_PEAK .assign 8 ;
MCEEVENT2_C1BE_C_NEG_PEAK .assign 7 ;
MCEEVENT2_C1BE_C_POS_PEAK .assign 6 ;
MCEEVENT2_C1BE_B_ANY_PEAK .assign 5 ;
MCEEVENT2_C1BE_B_NEG_PEAK .assign 4 ;
MCEEVENT2_C1BE_B_POS_PEAK .assign 3 ;
MCEEVENT2_C1BE_A_ANY_PEAK .assign 2 ;
MCEEVENT2_C1BE_A_NEG_PEAK .assign 1 ;
MCEEVENT2_C1BE_A_POS_PEAK .assign 0 ;
; --------------------------------------------------------------
; MCEEVENT3
;
MCEEVENT3 .assign 12
MCEEVENT3_SWQU_FALSE_SYNC_IRQ .assign 15 ;
MCEEVENT3_C1BE_G_ANY_PEAK .assign 14 ;
MCEEVENT3_C1BE_G_NEG_PEAK .assign 13 ;
MCEEVENT3_C1BE_G_POS_PEAK .assign 12 ;
MCEEVENT3_C1BE_CMB_DE_ANY_PEAK .assign 11 ;
MCEEVENT3_C1BE_CMB_DE_NEG_PEAK .assign 10 ;
MCEEVENT3_C1BE_CMB_DE_POS_PEAK .assign 9 ;
MCEEVENT3_C1BE_F_ANY_PEAK .assign 8 ;
MCEEVENT3_C1BE_F_NEG_PEAK .assign 7 ;
MCEEVENT3_C1BE_F_POS_PEAK .assign 6 ;
MCEEVENT3_C1BE_E_ANY_PEAK .assign 5 ;
MCEEVENT3_C1BE_E_NEG_PEAK .assign 4 ;
MCEEVENT3_C1BE_E_POS_PEAK .assign 3 ;
MCEEVENT3_C1BE_D_ANY_PEAK .assign 2 ;
MCEEVENT3_C1BE_D_NEG_PEAK .assign 1 ;
MCEEVENT3_C1BE_D_POS_PEAK .assign 0 ;
; --------------------------------------------------------------
; MCEEVENTMSK0
;
MCEEVENTMSK0 .assign 13
MCEEVENTMSK0_CL_RX_IRQ .assign 15 ;
MCEEVENTMSK0_DL_RX_IRQ .assign 14 ;
MCEEVENTMSK0_CL_TX_DONE .assign 13 ;
MCEEVENTMSK0_DL_TX_DONE .assign 12 ;
MCEEVENTMSK0_FRAC_EN .assign 11 ;
MCEEVENTMSK0_BDEC_EN .assign 10 ;
MCEEVENTMSK0_CPEFWEVENT1 .assign 9 ;
MCEEVENTMSK0_CPEFWEVENT0 .assign 8 ;
MCEEVENTMSK0_MDMFIFO_WR .assign 7 ;
MCEEVENTMSK0_COUNTER_IRQ .assign 6 ;
MCEEVENTMSK0_RFECMD_IRQ .assign 5 ;
MCEEVENTMSK0_FIFO_ERR_OVERFLOW .assign 4 ;
MCEEVENTMSK0_FIFO_ERR_UNDERFLOW .assign 3 ;
MCEEVENTMSK0_CLKEN_4BAUD .assign 2 ;
MCEEVENTMSK0_TIMER_IRQ .assign 1 ;
MCEEVENTMSK0_MDMAPI_WR .assign 0 ;
; --------------------------------------------------------------
; MCEEVENTMSK1
;
MCEEVENTMSK1 .assign 14
MCEEVENTMSK1_RAT_EVENT7 .assign 15 ;
MCEEVENTMSK1_RAT_EVENT6 .assign 14 ;
MCEEVENTMSK1_RAT_EVENT5 .assign 13 ;
MCEEVENTMSK1_RAT_EVENT4 .assign 12 ;
MCEEVENTMSK1_RAT_EVENT3 .assign 11 ;
MCEEVENTMSK1_RAT_EVENT2 .assign 10 ;
MCEEVENTMSK1_RAT_EVENT1 .assign 9 ;
MCEEVENTMSK1_RAT_EVENT0 .assign 8 ;
MCEEVENTMSK1_CLKEN_BAUD_F .assign 7 ;
MCEEVENTMSK1_MDMCMDPAR1_WR .assign 6 ;
MCEEVENTMSK1_MDMCMDPAR0_WR .assign 5 ;
MCEEVENTMSK1_VITACC .assign 4 ;
MCEEVENTMSK1_FIFORD_VALID .assign 3 ;
MCEEVENTMSK1_FIFOWR_READY .assign 2 ;
MCEEVENTMSK1_CLKEN_BAUD .assign 1 ;
MCEEVENTMSK1_PREAMBLE_DONE .assign 0 ;
; --------------------------------------------------------------
; MCEEVENTMSK2
;
MCEEVENTMSK2 .assign 15
MCEEVENTMSK2_MDMGPI1 .assign 15 ;
MCEEVENTMSK2_MDMGPI0 .assign 14 ;
MCEEVENTMSK2_SWQU_SYNCED_IRQ .assign 13 ;
MCEEVENTMSK2_C1BE_B_LOADED .assign 12 ;
MCEEVENTMSK2_C1BE_CMB_ANY_PEAK .assign 11 ;
MCEEVENTMSK2_C1BE_CMB_NEG_PEAK .assign 10 ;
MCEEVENTMSK2_C1BE_CMB_POS_PEAK .assign 9 ;
MCEEVENTMSK2_C1BE_C_ANY_PEAK .assign 8 ;
MCEEVENTMSK2_C1BE_C_NEG_PEAK .assign 7 ;
MCEEVENTMSK2_C1BE_C_POS_PEAK .assign 6 ;
MCEEVENTMSK2_C1BE_B_ANY_PEAK .assign 5 ;
MCEEVENTMSK2_C1BE_B_NEG_PEAK .assign 4 ;
MCEEVENTMSK2_C1BE_B_POS_PEAK .assign 3 ;
MCEEVENTMSK2_C1BE_A_ANY_PEAK .assign 2 ;
MCEEVENTMSK2_C1BE_A_NEG_PEAK .assign 1 ;
MCEEVENTMSK2_C1BE_A_POS_PEAK .assign 0 ;
; --------------------------------------------------------------
; MCEEVENTMSK3
;
MCEEVENTMSK3 .assign 16
MCEEVENTMSK3_SWQU_FALSE_SYNC_IRQ .assign 15 ;
MCEEVENTMSK3_C1BE_G_ANY_PEAK .assign 14 ;
MCEEVENTMSK3_C1BE_G_NEG_PEAK .assign 13 ;
MCEEVENTMSK3_C1BE_G_POS_PEAK .assign 12 ;
MCEEVENTMSK3_C1BE_CMB_DE_ANY_PEAK .assign 11 ;
MCEEVENTMSK3_C1BE_CMB_DE_NEG_PEAK .assign 10 ;
MCEEVENTMSK3_C1BE_CMB_DE_POS_PEAK .assign 9 ;
MCEEVENTMSK3_C1BE_F_ANY_PEAK .assign 8 ;
MCEEVENTMSK3_C1BE_F_NEG_PEAK .assign 7 ;
MCEEVENTMSK3_C1BE_F_POS_PEAK .assign 6 ;
MCEEVENTMSK3_C1BE_E_ANY_PEAK .assign 5 ;
MCEEVENTMSK3_C1BE_E_NEG_PEAK .assign 4 ;
MCEEVENTMSK3_C1BE_E_POS_PEAK .assign 3 ;
MCEEVENTMSK3_C1BE_D_ANY_PEAK .assign 2 ;
MCEEVENTMSK3_C1BE_D_NEG_PEAK .assign 1 ;
MCEEVENTMSK3_C1BE_D_POS_PEAK .assign 0 ;
; --------------------------------------------------------------
; MCEEVENTCLR0
;
MCEEVENTCLR0 .assign 17
MCEEVENTCLR0_CL_RX_IRQ .assign 15 ;
MCEEVENTCLR0_DL_RX_IRQ .assign 14 ;
MCEEVENTCLR0_CL_TX_DONE .assign 13 ;
MCEEVENTCLR0_DL_TX_DONE .assign 12 ;
MCEEVENTCLR0_FRAC_EN .assign 11 ;
MCEEVENTCLR0_BDEC_EN .assign 10 ;
MCEEVENTCLR0_CPEFWEVENT1 .assign 9 ;
MCEEVENTCLR0_CPEFWEVENT0 .assign 8 ;
MCEEVENTCLR0_MDMFIFO_WR .assign 7 ;
MCEEVENTCLR0_COUNTER_IRQ .assign 6 ;
MCEEVENTCLR0_RFECMD_IRQ .assign 5 ;
MCEEVENTCLR0_FIFO_ERR_OVERFLOW .assign 4 ;
MCEEVENTCLR0_FIFO_ERR_UNDERFLOW .assign 3 ;
MCEEVENTCLR0_CLKEN_4BAUD .assign 2 ;
MCEEVENTCLR0_TIMER_IRQ .assign 1 ;
MCEEVENTCLR0_MDMAPI_WR .assign 0 ;
; --------------------------------------------------------------
; MCEEVENTCLR1
;
MCEEVENTCLR1 .assign 18
MCEEVENTCLR1_RAT_EVENT7 .assign 15 ;
MCEEVENTCLR1_RAT_EVENT6 .assign 14 ;
MCEEVENTCLR1_RAT_EVENT5 .assign 13 ;
MCEEVENTCLR1_RAT_EVENT4 .assign 12 ;
MCEEVENTCLR1_RAT_EVENT3 .assign 11 ;
MCEEVENTCLR1_RAT_EVENT2 .assign 10 ;
MCEEVENTCLR1_RAT_EVENT1 .assign 9 ;
MCEEVENTCLR1_RAT_EVENT0 .assign 8 ;
MCEEVENTCLR1_CLKEN_BAUD_F .assign 7 ;
MCEEVENTCLR1_MDMCMDPAR1_WR .assign 6 ;
MCEEVENTCLR1_MDMCMDPAR0_WR .assign 5 ;
MCEEVENTCLR1_VITACC .assign 4 ;
MCEEVENTCLR1_FIFORD_VALID .assign 3 ;
MCEEVENTCLR1_FIFOWR_READY .assign 2 ;
MCEEVENTCLR1_CLKEN_BAUD .assign 1 ;
MCEEVENTCLR1_PREAMBLE_DONE .assign 0 ;
; --------------------------------------------------------------
; MCEEVENTCLR2
;
MCEEVENTCLR2 .assign 19
MCEEVENTCLR2_MDMGPI1 .assign 15 ;
MCEEVENTCLR2_MDMGPI0 .assign 14 ;
MCEEVENTCLR2_SWQU_SYNCED_IRQ .assign 13 ;
MCEEVENTCLR2_C1BE_B_LOADED .assign 12 ;
MCEEVENTCLR2_C1BE_CMB_ANY_PEAK .assign 11 ;
MCEEVENTCLR2_C1BE_CMB_NEG_PEAK .assign 10 ;
MCEEVENTCLR2_C1BE_CMB_POS_PEAK .assign 9 ;
MCEEVENTCLR2_C1BE_C_ANY_PEAK .assign 8 ;
MCEEVENTCLR2_C1BE_C_NEG_PEAK .assign 7 ;
MCEEVENTCLR2_C1BE_C_POS_PEAK .assign 6 ;
MCEEVENTCLR2_C1BE_B_ANY_PEAK .assign 5 ;
MCEEVENTCLR2_C1BE_B_NEG_PEAK .assign 4 ;
MCEEVENTCLR2_C1BE_B_POS_PEAK .assign 3 ;
MCEEVENTCLR2_C1BE_A_ANY_PEAK .assign 2 ;
MCEEVENTCLR2_C1BE_A_NEG_PEAK .assign 1 ;
MCEEVENTCLR2_C1BE_A_POS_PEAK .assign 0 ;
; --------------------------------------------------------------
; MCEEVENTCLR3
;
MCEEVENTCLR3 .assign 20
MCEEVENTCLR3_SWQU_FALSE_SYNC_IRQ .assign 15 ;
MCEEVENTCLR3_C1BE_G_ANY_PEAK .assign 14 ;
MCEEVENTCLR3_C1BE_G_NEG_PEAK .assign 13 ;
MCEEVENTCLR3_C1BE_G_POS_PEAK .assign 12 ;
MCEEVENTCLR3_C1BE_CMB_DE_ANY_PEAK .assign 11 ;
MCEEVENTCLR3_C1BE_CMB_DE_NEG_PEAK .assign 10 ;
MCEEVENTCLR3_C1BE_CMB_DE_POS_PEAK .assign 9 ;
MCEEVENTCLR3_C1BE_F_ANY_PEAK .assign 8 ;
MCEEVENTCLR3_C1BE_F_NEG_PEAK .assign 7 ;
MCEEVENTCLR3_C1BE_F_POS_PEAK .assign 6 ;
MCEEVENTCLR3_C1BE_E_ANY_PEAK .assign 5 ;
MCEEVENTCLR3_C1BE_E_NEG_PEAK .assign 4 ;
MCEEVENTCLR3_C1BE_E_POS_PEAK .assign 3 ;
MCEEVENTCLR3_C1BE_D_ANY_PEAK .assign 2 ;
MCEEVENTCLR3_C1BE_D_NEG_PEAK .assign 1 ;
MCEEVENTCLR3_C1BE_D_POS_PEAK .assign 0 ;
; --------------------------------------------------------------
; MCEPROGRAMSRC
;
MCEPROGRAMSRC .assign 21
MCEPROGRAMSRC_ROMBANK .assign 1 ;
MCEPROGRAMSRC_RAMROM .assign 0 ;
; --------------------------------------------------------------
; MDMAPI
;
MDMAPI .assign 22
MDMAPI_PROTOCOLID .assign 8 ;
MDMAPI_MDMCMD .assign 0 ;
; --------------------------------------------------------------
; MDMCMDPAR0
;
MDMCMDPAR0 .assign 23
MDMCMDPAR0_PAR0 .assign 0 ;
; --------------------------------------------------------------
; MDMCMDPAR1
;
MDMCMDPAR1 .assign 24
MDMCMDPAR1_PAR1 .assign 0 ;
; --------------------------------------------------------------
; MDMCMDPAR2
;
MDMCMDPAR2 .assign 25
MDMCMDPAR2_PAR .assign 0 ;
; --------------------------------------------------------------
; MDMRFCHANNEL
;
MDMRFCHANNEL .assign 26
MDMRFCHANNEL_VALUE .assign 0 ;
; --------------------------------------------------------------
; MDMSTATUS
;
MDMSTATUS .assign 27
MDMSTATUS_VALUE .assign 0 ;
; --------------------------------------------------------------
; MDMFIFOWR
;
MDMFIFOWR .assign 28
MDMFIFOWR_PAYLOADIN .assign 0 ;
; --------------------------------------------------------------
; MDMFIFORD
;
MDMFIFORD .assign 29
MDMFIFORD_PAYLOADOUT .assign 0 ;
; --------------------------------------------------------------
; MDMFIFOWRCTRL
;
MDMFIFOWRCTRL .assign 30
MDMFIFOWRCTRL_FIFOWRPORT .assign 4 ;
MDMFIFOWRCTRL_WORDSZWR .assign 0 ;
; --------------------------------------------------------------
; MDMFIFORDCTRL
;
MDMFIFORDCTRL .assign 31
MDMFIFORDCTRL_FIFORDPORT .assign 4 ;
MDMFIFORDCTRL_WORDSZRD .assign 0 ;
; --------------------------------------------------------------
; MDMFIFOCFG
;
MDMFIFOCFG .assign 32
MDMFIFOCFG_AFULLTHR .assign 8 ;
MDMFIFOCFG_AEMPTYTHR .assign 0 ;
; --------------------------------------------------------------
; MDMFIFOSTA
;
MDMFIFOSTA .assign 33
MDMFIFOSTA_OVERFLOW .assign 5 ;
MDMFIFOSTA_ALMOSTFULL .assign 4 ;
MDMFIFOSTA_ALMOSTEMPTY .assign 3 ;
MDMFIFOSTA_UNDERFLOW .assign 2 ;
MDMFIFOSTA_RXVALID .assign 1 ;
MDMFIFOSTA_TXREADY .assign 0 ;
; --------------------------------------------------------------
; CPEFWEVENT
;
CPEFWEVENT .assign 34
CPEFWEVENT_EVENT3 .assign 3 ;
CPEFWEVENT_EVENT2 .assign 2 ;
CPEFWEVENT_EVENT1 .assign 1 ;
CPEFWEVENT_EVENT0 .assign 0 ;
; --------------------------------------------------------------
; RFESEND
;
RFESEND .assign 35
RFESEND_MCECMD .assign 0 ;
; --------------------------------------------------------------
; RFERCEV
;
RFERCEV .assign 36
RFERCEV_RFECMD .assign 0 ;
; --------------------------------------------------------------
; SMICONF
;
SMICONF .assign 37
SMICONF_SMIENABLE .assign 8 ;
SMICONF_PRESCALER .assign 4 ;
SMICONF_MLENGTH .assign 0 ;
; --------------------------------------------------------------
; SMIDLOUTG
;
SMIDLOUTG .assign 38
SMIDLOUTG_DL .assign 0 ;
; --------------------------------------------------------------
; SMICLOUTG
;
SMICLOUTG .assign 39
SMICLOUTG_CL .assign 0 ;
; --------------------------------------------------------------
; SMIDLINC
;
SMIDLINC .assign 40
SMIDLINC_DL .assign 0 ;
; --------------------------------------------------------------
; SMICLINC
;
SMICLINC .assign 41
SMICLINC_CL .assign 0 ;
; --------------------------------------------------------------
; SMISTA
;
SMISTA .assign 42
SMISTA_INCCLERROR .assign 1 ;
SMISTA_INCDLERROR .assign 0 ;
; --------------------------------------------------------------
; ADCDIGCONF
;
ADCDIGCONF .assign 43
ADCDIGCONF_QBRANCHEN .assign 1 ;
ADCDIGCONF_IBRANCHEN .assign 0 ;
; --------------------------------------------------------------
; MODPRECTRL
;
MODPRECTRL .assign 44
MODPRECTRL_REPS .assign 4 ;
MODPRECTRL_SIZE .assign 0 ;
; --------------------------------------------------------------
; MODSYMMAP0
;
MODSYMMAP0 .assign 45
MODSYMMAP0_SYM3 .assign 12 ;
MODSYMMAP0_SYM2 .assign 8 ;
MODSYMMAP0_SYM1 .assign 4 ;
MODSYMMAP0_SYM0 .assign 0 ;
; --------------------------------------------------------------
; MODSYMMAP1
;
MODSYMMAP1 .assign 46
MODSYMMAP1_SYM7 .assign 12 ;
MODSYMMAP1_SYM6 .assign 8 ;
MODSYMMAP1_SYM5 .assign 4 ;
MODSYMMAP1_SYM4 .assign 0 ;
; --------------------------------------------------------------
; MODSOFTTX
;
MODSOFTTX .assign 47
MODSOFTTX_SOFTSYMBOL .assign 0 ;
; --------------------------------------------------------------
; MDMBAUD
;
MDMBAUD .assign 48
MDMBAUD_RATEWORD .assign 0 ;
; --------------------------------------------------------------
; MDMBAUDPRE
;
MDMBAUDPRE .assign 49
MDMBAUDPRE_ALIGNVALUE .assign 13 ;
MDMBAUDPRE_EXTRATEWORD .assign 8 ;
MDMBAUDPRE_PRESCALER .assign 0 ;
; --------------------------------------------------------------
; MODMAIN
;
MODMAIN .assign 50
MODMAIN_SPREADFACTOR .assign 6 ;
MODMAIN_FECSELECT .assign 2 ;
MODMAIN_MODLEVELS .assign 0 ;
; --------------------------------------------------------------
; DEMMISC0
;
DEMMISC0 .assign 51
DEMMISC0_CMI4FMIXSIGN .assign 12 ;
DEMMISC0_HILBREMOVEREAL .assign 11 ;
DEMMISC0_HILBEN .assign 10 ;
DEMMISC0_CMIXN .assign 0 ;
; --------------------------------------------------------------
; DEMMISC1
;
DEMMISC1 .assign 52
DEMMISC1_MGE2SRCSEL .assign 2 ;
DEMMISC1_CHFIBW .assign 0 ;
; --------------------------------------------------------------
; DEMMISC2
;
DEMMISC2 .assign 53
DEMMISC2_LQIPERIOD .assign 14 ;
DEMMISC2_MLSERUN .assign 13 ;
DEMMISC2_MAFCGAIN .assign 11 ;
DEMMISC2_STIMESTONLY .assign 10 ;
DEMMISC2_STIMTEAPERIOD .assign 7 ;
DEMMISC2_STIMTEAGAIN .assign 4 ;
DEMMISC2_PDIFLINPREDEN .assign 3 ;
DEMMISC2_PDIFDESPECKLEREN .assign 2 ;
DEMMISC2_PDIFIQCONJEN .assign 1 ;
DEMMISC2_PDIFLIMITRANGE .assign 0 ;
; --------------------------------------------------------------
; DEMMISC3
;
DEMMISC3 .assign 54
DEMMISC3_BDE1DVGA .assign 10 ;
DEMMISC3_BDE2DVGA .assign 8 ;
DEMMISC3_BDE1NUMSTAGES .assign 5 ;
DEMMISC3_PDIFDECIM .assign 3 ;
DEMMISC3_BDECNUMSTAGES .assign 0 ;
; --------------------------------------------------------------
; DEMIQMC0
;
DEMIQMC0 .assign 55
DEMIQMC0_GAINFACTOR .assign 8 ;
DEMIQMC0_PHASEFACTOR .assign 0 ;
; --------------------------------------------------------------
; DEMDSBU
;
DEMDSBU .assign 56
DEMDSBU_DSBUDELAY .assign 0 ;
; --------------------------------------------------------------
; DEMDSBU2
;
DEMDSBU2 .assign 57
DEMDSBU2_DSBUAVGLENGTH .assign 0 ;
; --------------------------------------------------------------
; DEMCODC0
;
DEMCODC0 .assign 58
DEMCODC0_ESTSEL .assign 11 ;
DEMCODC0_COMPSEL .assign 9 ;
DEMCODC0_IIRUSEINITIAL .assign 8 ;
DEMCODC0_IIRGAIN .assign 5 ;
DEMCODC0_IIREN .assign 4 ;
DEMCODC0_ACCCONTMODE .assign 3 ;
DEMCODC0_ACCPERIOD .assign 1 ;
DEMCODC0_ACCEN .assign 0 ;
; --------------------------------------------------------------
; DEMFIDC0
;
DEMFIDC0 .assign 59
DEMFIDC0_COMPSEL .assign 4 ;
DEMFIDC0_ACCPERIOD .assign 2 ;
DEMFIDC0_ACCCONTMODE .assign 1 ;
DEMFIDC0_ACCEN .assign 0 ;
; --------------------------------------------------------------
; DEMFEXB0
;
DEMFEXB0 .assign 60
DEMFEXB0_OUT2PASSTHROUGH .assign 13 ;
DEMFEXB0_OUT2SRCSEL .assign 11 ;
DEMFEXB0_OUT1PASSTHROUGH .assign 10 ;
DEMFEXB0_OUT1SRCSEL .assign 8 ;
DEMFEXB0_B4SRCSEL .assign 6 ;
DEMFEXB0_B3SRCSEL .assign 4 ;
DEMFEXB0_B2SRCSEL .assign 2 ;
DEMFEXB0_B1SRCSEL .assign 0 ;
; --------------------------------------------------------------
; DEMDSXB0
;
DEMDSXB0 .assign 61
DEMDSXB0_OUT2PASSTHROUGH .assign 13 ;
DEMDSXB0_OUT1PASSTHROUGH .assign 12 ;
DEMDSXB0_OUTSRCSEL2 .assign 10 ;
DEMDSXB0_OUTSRCSEL1 .assign 8 ;
DEMDSXB0_B4SRCSEL .assign 6 ;
DEMDSXB0_B3SRCSEL .assign 4 ;
DEMDSXB0_B2SRCSEL .assign 2 ;
DEMDSXB0_B1SRCSEL .assign 0 ;
; --------------------------------------------------------------
; DEMD2XB0
;
DEMD2XB0 .assign 62
DEMD2XB0_B3SRCSEL .assign 10 ;
DEMD2XB0_OUT2PASSTHROUGH .assign 9 ;
DEMD2XB0_OUT1PASSTHROUGH .assign 8 ;
DEMD2XB0_OUTSRCSEL2 .assign 6 ;
DEMD2XB0_OUTSRCSEL1 .assign 4 ;
DEMD2XB0_B2SRCSEL .assign 2 ;
DEMD2XB0_B1SRCSEL .assign 0 ;
; --------------------------------------------------------------
; DEMFIFE0
;
DEMFIFE0 .assign 63
DEMFIFE0_FINEFOESEL .assign 11 ;
DEMFIFE0_FOCFFSEL .assign 9 ;
DEMFIFE0_ACCCNTMODE .assign 8 ;
DEMFIFE0_ACCPERIOD .assign 6 ;
DEMFIFE0_ACCEN .assign 5 ;
DEMFIFE0_IIRUSEINITIAL .assign 4 ;
DEMFIFE0_IIRGAIN .assign 1 ;
DEMFIFE0_IIREN .assign 0 ;
; --------------------------------------------------------------
; DEMMAFI0
;
DEMMAFI0 .assign 64
DEMMAFI0_C1C7 .assign 8 ;
DEMMAFI0_C0C8 .assign 0 ;
; --------------------------------------------------------------
; DEMMAFI1
;
DEMMAFI1 .assign 65
DEMMAFI1_C3C5 .assign 8 ;
DEMMAFI1_C2C6 .assign 0 ;
; --------------------------------------------------------------
; DEMMAFI2
;
DEMMAFI2 .assign 66
DEMMAFI2_C4 .assign 0 ;
; --------------------------------------------------------------
; DEMMAFI3
;
DEMMAFI3 .assign 67
DEMMAFI3_K .assign 0 ;
; --------------------------------------------------------------
; DEMC1BE0
;
DEMC1BE0 .assign 68
DEMC1BE0_MASKB .assign 11 ;
DEMC1BE0_MASKA .assign 6 ;
DEMC1BE0_CASCCONF .assign 4 ;
DEMC1BE0_COPYCONF .assign 0 ;
; --------------------------------------------------------------
; DEMC1BE1
;
DEMC1BE1 .assign 69
DEMC1BE1_THRESHOLDB .assign 8 ;
DEMC1BE1_THRESHOLDA .assign 0 ;
; --------------------------------------------------------------
; DEMC1BE2
;
DEMC1BE2 .assign 70
DEMC1BE2_PEAKCONF .assign 8 ;
DEMC1BE2_THRESHOLDC .assign 0 ;
; --------------------------------------------------------------
; DEMC1BE10
;
DEMC1BE10 .assign 71
DEMC1BE10_PEAKCONF_G .assign 15 ;
DEMC1BE10_PEAKCONF_CF .assign 13 ;
DEMC1BE10_MASKE .assign 8 ;
DEMC1BE10_MASKD .assign 3 ;
DEMC1BE10_CASCCONF .assign 0 ;
; --------------------------------------------------------------
; DEMC1BE11
;
DEMC1BE11 .assign 72
DEMC1BE11_THRESHOLDE .assign 8 ;
DEMC1BE11_THRESHOLDD .assign 0 ;
; --------------------------------------------------------------
; DEMC1BE12
;
DEMC1BE12 .assign 73
DEMC1BE12_THRESHOLDG .assign 8 ;
DEMC1BE12_THRESHOLDF .assign 0 ;
; --------------------------------------------------------------
; MDMSYNC0
;
MDMSYNC0 .assign 74
MDMSYNC0_SWA15C0 .assign 0 ;
; --------------------------------------------------------------
; MDMSYNC1
;
MDMSYNC1 .assign 75
MDMSYNC1_SWA31C16 .assign 0 ;
; --------------------------------------------------------------
; MDMSYNC2
;
MDMSYNC2 .assign 76
MDMSYNC2_SWB15C0 .assign 0 ;
; --------------------------------------------------------------
; MDMSYNC3
;
MDMSYNC3 .assign 77
MDMSYNC3_SWB31C16 .assign 0 ;
; --------------------------------------------------------------
; DEMSWQU0
;
DEMSWQU0 .assign 78
DEMSWQU0_SYNC_MODE .assign 7 ;
DEMSWQU0_AUTOMAFC .assign 6 ;
DEMSWQU0_RUN .assign 5 ;
DEMSWQU0_REFLEN .assign 0 ;
; --------------------------------------------------------------
; DEMFB2P0
;
DEMFB2P0 .assign 79
DEMFB2P0_BETA .assign 8 ;
DEMFB2P0_ALPHA .assign 0 ;
; --------------------------------------------------------------
; DEMFB2P1
;
DEMFB2P1 .assign 80
DEMFB2P1_FB2P_OPEN .assign 14 ;
DEMFB2P1_HDIS_PRS .assign 12 ;
DEMFB2P1_IIR_GAIN .assign 10 ;
DEMFB2P1_IIR_BW .assign 7 ;
DEMFB2P1_FB2PLL_LIMIT .assign 0 ;
; --------------------------------------------------------------
; DEMPHAC0
;
DEMPHAC0 .assign 81
DEMPHAC0_REF_B .assign 8 ;
DEMPHAC0_REF_A .assign 0 ;
; --------------------------------------------------------------
; DEMPHAC1
;
DEMPHAC1 .assign 82
DEMPHAC1_PHAC_TR_LEN .assign 10 ;
DEMPHAC1_PHAC_SYM_LEN .assign 7 ;
DEMPHAC1_PHASE_INCR .assign 0 ;
; --------------------------------------------------------------
; DEMPHAC2
;
DEMPHAC2 .assign 83
DEMPHAC2_ALPHA .assign 8 ;
DEMPHAC2_BETA .assign 0 ;
; --------------------------------------------------------------
; DEMPHAC3
;
DEMPHAC3 .assign 84
DEMPHAC3_IIR_BW .assign 0 ;
; --------------------------------------------------------------
; DEMPHAC4
;
DEMPHAC4 .assign 85
DEMPHAC4_TR_15_0 .assign 0 ;
; --------------------------------------------------------------
; DEMPHAC5
;
DEMPHAC5 .assign 86
DEMPHAC5_TR_31_16 .assign 0 ;
; --------------------------------------------------------------
; DEMPHAC6
;
DEMPHAC6 .assign 87
DEMPHAC6_TR_47_32 .assign 0 ;
; --------------------------------------------------------------
; DEMPHAC7
;
DEMPHAC7 .assign 88
DEMPHAC7_TR_63_48 .assign 0 ;
; --------------------------------------------------------------
; DEMC1BEREF0
;
DEMC1BEREF0 .assign 89
DEMC1BEREF0_CAR15C0 .assign 0 ;
; --------------------------------------------------------------
; DEMC1BEREF1
;
DEMC1BEREF1 .assign 90
DEMC1BEREF1_CAR31C16 .assign 0 ;
; --------------------------------------------------------------
; DEMC1BEREF2
;
DEMC1BEREF2 .assign 91
DEMC1BEREF2_CBR15C0 .assign 0 ;
; --------------------------------------------------------------
; DEMC1BEREF3
;
DEMC1BEREF3 .assign 92
DEMC1BEREF3_CBR31C16 .assign 0 ;
; --------------------------------------------------------------
; DEMC1BEREF4
;
DEMC1BEREF4 .assign 93
DEMC1BEREF4_CDR15C0 .assign 0 ;
; --------------------------------------------------------------
; DEMC1BEREF5
;
DEMC1BEREF5 .assign 94
DEMC1BEREF5_CDR31C16 .assign 0 ;
; --------------------------------------------------------------
; DEMC1BEREF6
;
DEMC1BEREF6 .assign 95
DEMC1BEREF6_CER15C0 .assign 0 ;
; --------------------------------------------------------------
; DEMC1BEREF7
;
DEMC1BEREF7 .assign 96
DEMC1BEREF7_CER31C16 .assign 0 ;
; --------------------------------------------------------------
; DEMMLSE4MAP
;
DEMMLSE4MAP .assign 97
DEMMLSE4MAP_MAP_P3 .assign 6 ;
DEMMLSE4MAP_MAP_P1 .assign 4 ;
DEMMLSE4MAP_MAP_M1 .assign 2 ;
DEMMLSE4MAP_MAP_M3 .assign 0 ;
; --------------------------------------------------------------
; DEMC1BE13
;
DEMC1BE13 .assign 98
DEMC1BE13_CORRVALUED .assign 0 ;
; --------------------------------------------------------------
; MODCTRL
;
MODCTRL .assign 99
MODCTRL_CDC_COL_RESTART .assign 12 ;
MODCTRL_DSBUSEL .assign 11 ;
MODCTRL_HDISMODE .assign 10 ;
MODCTRL_PARBITQUALEN .assign 9 ;
MODCTRL_STIMEARLYLATE .assign 7 ;
MODCTRL_EARLYLATE .assign 6 ;
MODCTRL_SOFTPDIFFMODE .assign 5 ;
MODCTRL_SOFTTXENABLE .assign 4 ;
MODCTRL_FECENABLE .assign 3 ;
MODCTRL_FEC5TERMINATE .assign 2 ;
MODCTRL_TONEINSERT .assign 1 ;
MODCTRL_PREAMBLEINSERT .assign 0 ;
; --------------------------------------------------------------
; MODPREAMBLE
;
MODPREAMBLE .assign 100
MODPREAMBLE_WORD .assign 0 ;
; --------------------------------------------------------------
; DEMFRAC0
;
DEMFRAC0 .assign 101
DEMFRAC0_P15C0 .assign 0 ;
; --------------------------------------------------------------
; DEMFRAC1
;
DEMFRAC1 .assign 102
DEMFRAC1_P27C16 .assign 0 ;
; --------------------------------------------------------------
; DEMFRAC2
;
DEMFRAC2 .assign 103
DEMFRAC2_Q15C0 .assign 0 ;
; --------------------------------------------------------------
; DEMFRAC3
;
DEMFRAC3 .assign 104
DEMFRAC3_Q27C16 .assign 0 ;
; --------------------------------------------------------------
; DEMCODC1
;
DEMCODC1 .assign 105
DEMCODC1_COMPIVAL .assign 0 ;
; --------------------------------------------------------------
; DEMCODC2
;
DEMCODC2 .assign 106
DEMCODC2_COMPQVAL .assign 0 ;
; --------------------------------------------------------------
; DEMFIDC1
;
DEMFIDC1 .assign 107
DEMFIDC1_COMPIVAL .assign 0 ;
; --------------------------------------------------------------
; DEMFIDC2
;
DEMFIDC2 .assign 108
DEMFIDC2_COMPQVAL .assign 0 ;
; --------------------------------------------------------------
; DEMFIFE1
;
DEMFIFE1 .assign 109
DEMFIFE1_FOCFBREGVAL .assign 0 ;
; --------------------------------------------------------------
; DEMTHRD0
;
DEMTHRD0 .assign 110
DEMTHRD0_THR2 .assign 8 ;
DEMTHRD0_RESERVED .assign 7 ;
DEMTHRD0_THR1 .assign 0 ;
; --------------------------------------------------------------
; DEMTHRD1
;
DEMTHRD1 .assign 111
DEMTHRD1_THR3 .assign 0 ;
; --------------------------------------------------------------
; DEMMAFC0
;
DEMMAFC0 .assign 112
DEMMAFC0_COMPVAL .assign 0 ;
; --------------------------------------------------------------
; DEMMAFI4
;
DEMMAFI4 .assign 113
DEMMAFI4_TERM_VAL .assign 0 ;
; --------------------------------------------------------------
; DEMSWIMBAL
;
DEMSWIMBAL .assign 114
DEMSWIMBAL_IMBALB .assign 8 ;
DEMSWIMBAL_IMBALA .assign 0 ;
; --------------------------------------------------------------
; DEMSOFTPDIFF
;
DEMSOFTPDIFF .assign 115
DEMSOFTPDIFF_SOFTPDIFF .assign 0 ;
; --------------------------------------------------------------
; DEMDEBUG
;
DEMDEBUG .assign 116
DEMDEBUG_DECSTAGEDEBUG .assign 5 ;
DEMDEBUG_FRONTENDDEBUG .assign 1 ;
DEMDEBUG_LOOPBACKMODE .assign 0 ;
; --------------------------------------------------------------
; VITCTRL
;
VITCTRL .assign 117
VITCTRL_METRSEL .assign 10 ;
VITCTRL_READEPTH .assign 6 ;
VITCTRL_APMRDBACKSEL .assign 2 ;
VITCTRL_ACSITERATIONS .assign 1 ;
VITCTRL_SOFTMETRICS .assign 0 ;
; --------------------------------------------------------------
; VITCOMPUTE
;
VITCOMPUTE .assign 118
VITCOMPUTE_COMPUTE .assign 0 ;
; --------------------------------------------------------------
; VITAPMRDBACK
;
VITAPMRDBACK .assign 119
VITAPMRDBACK_VALUE .assign 0 ;
; --------------------------------------------------------------
; VITSTATE
;
VITSTATE .assign 120
VITSTATE_VALUE .assign 0 ;
; --------------------------------------------------------------
; VITBRMETRIC10
;
VITBRMETRIC10 .assign 121
VITBRMETRIC10_MET1 .assign 8 ;
VITBRMETRIC10_MET0 .assign 0 ;
; --------------------------------------------------------------
; VITBRMETRIC32
;
VITBRMETRIC32 .assign 122
VITBRMETRIC32_MET3 .assign 8 ;
VITBRMETRIC32_MET2 .assign 0 ;
; --------------------------------------------------------------
; VITBRMETRIC54
;
VITBRMETRIC54 .assign 123
VITBRMETRIC54_MET5 .assign 8 ;
VITBRMETRIC54_MET4 .assign 0 ;
; --------------------------------------------------------------
; VITBRMETRIC76
;
VITBRMETRIC76 .assign 124
VITBRMETRIC76_MET7 .assign 8 ;
VITBRMETRIC76_MET6 .assign 0 ;
; --------------------------------------------------------------
; VITBRSEL0
;
VITBRSEL0 .assign 125
VITBRSEL0_BR3MUX .assign 9 ;
VITBRSEL0_BR2MUX .assign 6 ;
VITBRSEL0_BR1MUX .assign 3 ;
VITBRSEL0_BR0MUX .assign 0 ;
; --------------------------------------------------------------
; VITAPMSEL0
;
VITAPMSEL0 .assign 126
VITAPMSEL0_APM3MUX .assign 9 ;
VITAPMSEL0_APM2MUX .assign 6 ;
VITAPMSEL0_APM1MUX .assign 3 ;
VITAPMSEL0_APM0MUX .assign 0 ;
; --------------------------------------------------------------
; VITBRSEL1
;
VITBRSEL1 .assign 127
VITBRSEL1_BR3MUX .assign 9 ;
VITBRSEL1_BR2MUX .assign 6 ;
VITBRSEL1_BR1MUX .assign 3 ;
VITBRSEL1_BR0MUX .assign 0 ;
; --------------------------------------------------------------
; VITAPMSEL1
;
VITAPMSEL1 .assign 128
VITAPMSEL1_APM3MUX .assign 9 ;
VITAPMSEL1_APM2MUX .assign 6 ;
VITAPMSEL1_APM1MUX .assign 3 ;
VITAPMSEL1_APM0MUX .assign 0 ;
; --------------------------------------------------------------
; VITBRSEL2
;
VITBRSEL2 .assign 129
VITBRSEL2_BR3MUX .assign 9 ;
VITBRSEL2_BR2MUX .assign 6 ;
VITBRSEL2_BR1MUX .assign 3 ;
VITBRSEL2_BR0MUX .assign 0 ;
; --------------------------------------------------------------
; VITAPMSEL2
;
VITAPMSEL2 .assign 130
VITAPMSEL2_APM3MUX .assign 9 ;
VITAPMSEL2_APM2MUX .assign 6 ;
VITAPMSEL2_APM1MUX .assign 3 ;
VITAPMSEL2_APM0MUX .assign 0 ;
; --------------------------------------------------------------
; VITBRSEL3
;
VITBRSEL3 .assign 131
VITBRSEL3_BR3MUX .assign 9 ;
VITBRSEL3_BR2MUX .assign 6 ;
VITBRSEL3_BR1MUX .assign 3 ;
VITBRSEL3_BR0MUX .assign 0 ;
; --------------------------------------------------------------
; VITAPMSEL3
;
VITAPMSEL3 .assign 132
VITAPMSEL3_APM3MUX .assign 9 ;
VITAPMSEL3_APM2MUX .assign 6 ;
VITAPMSEL3_APM1MUX .assign 3 ;
VITAPMSEL3_APM0MUX .assign 0 ;
; --------------------------------------------------------------
; VITBRSEL4
;
VITBRSEL4 .assign 133
VITBRSEL4_BR3MUX .assign 9 ;
VITBRSEL4_BR2MUX .assign 6 ;
VITBRSEL4_BR1MUX .assign 3 ;
VITBRSEL4_BR0MUX .assign 0 ;
; --------------------------------------------------------------
; VITAPMSEL4
;
VITAPMSEL4 .assign 134
VITAPMSEL4_APM3MUX .assign 9 ;
VITAPMSEL4_APM2MUX .assign 6 ;
VITAPMSEL4_APM1MUX .assign 3 ;
VITAPMSEL4_APM0MUX .assign 0 ;
; --------------------------------------------------------------
; VITBRSEL5
;
VITBRSEL5 .assign 135
VITBRSEL5_BR3MUX .assign 9 ;
VITBRSEL5_BR2MUX .assign 6 ;
VITBRSEL5_BR1MUX .assign 3 ;
VITBRSEL5_BR0MUX .assign 0 ;
; --------------------------------------------------------------
; VITAPMSEL5
;
VITAPMSEL5 .assign 136
VITAPMSEL5_APM3MUX .assign 9 ;
VITAPMSEL5_APM2MUX .assign 6 ;
VITAPMSEL5_APM1MUX .assign 3 ;
VITAPMSEL5_APM0MUX .assign 0 ;
; --------------------------------------------------------------
; VITBRSEL6
;
VITBRSEL6 .assign 137
VITBRSEL6_BR3MUX .assign 9 ;
VITBRSEL6_BR2MUX .assign 6 ;
VITBRSEL6_BR1MUX .assign 3 ;
VITBRSEL6_BR0MUX .assign 0 ;
; --------------------------------------------------------------
; VITAPMSEL6
;
VITAPMSEL6 .assign 138
VITAPMSEL6_APM3MUX .assign 9 ;
VITAPMSEL6_APM2MUX .assign 6 ;
VITAPMSEL6_APM1MUX .assign 3 ;
VITAPMSEL6_APM0MUX .assign 0 ;
; --------------------------------------------------------------
; VITBRSEL7
;
VITBRSEL7 .assign 139
VITBRSEL7_BR3MUX .assign 9 ;
VITBRSEL7_BR2MUX .assign 6 ;
VITBRSEL7_BR1MUX .assign 3 ;
VITBRSEL7_BR0MUX .assign 0 ;
; --------------------------------------------------------------
; VITAPMSEL7
;
VITAPMSEL7 .assign 140
VITAPMSEL7_APM3MUX .assign 9 ;
VITAPMSEL7_APM2MUX .assign 6 ;
VITAPMSEL7_APM1MUX .assign 3 ;
VITAPMSEL7_APM0MUX .assign 0 ;
; --------------------------------------------------------------
; LOCMULTA
;
LOCMULTA .assign 141
LOCMULTA_AVALUE .assign 0 ;
; --------------------------------------------------------------
; LOCMULTB
;
LOCMULTB .assign 142
LOCMULTB_BVALUE .assign 0 ;
; --------------------------------------------------------------
; LOCMULTC0
;
LOCMULTC0 .assign 143
LOCMULTC0_C15C0 .assign 0 ;
; --------------------------------------------------------------
; LOCMULTC1
;
LOCMULTC1 .assign 144
LOCMULTC1_C31C16 .assign 0 ;
; --------------------------------------------------------------
; TIMCTRL
;
TIMCTRL .assign 145
TIMCTRL_CAPTURESOURCE .assign 8 ;
TIMCTRL_ENABLECAPTURE .assign 7 ;
TIMCTRL_COUNTERSOURCE .assign 5 ;
TIMCTRL_CLEARCOUNTER .assign 4 ;
TIMCTRL_ENABLECOUNTER .assign 3 ;
TIMCTRL_TIMERSOURCE .assign 1 ;
TIMCTRL_ENABLETIMER .assign 0 ;
; --------------------------------------------------------------
; TIMINC
;
TIMINC .assign 146
TIMINC_INCUNIT .assign 0 ;
; --------------------------------------------------------------
; TIMPERIOD
;
TIMPERIOD .assign 147
TIMPERIOD_PERIOD .assign 0 ;
; --------------------------------------------------------------
; TIMCOUNTER
;
TIMCOUNTER .assign 148
TIMCOUNTER_VALUE .assign 0 ;
; --------------------------------------------------------------
; TIMCAPT
;
TIMCAPT .assign 149
TIMCAPT_VALUE .assign 0 ;
; --------------------------------------------------------------
; TIMEBASE
;
TIMEBASE .assign 150
TIMEBASE_FLUSH .assign 0 ;
; --------------------------------------------------------------
; COUNT1IN
;
COUNT1IN .assign 151
COUNT1IN_VAL .assign 0 ;
; --------------------------------------------------------------
; COUNT1RES
;
COUNT1RES .assign 152
COUNT1RES_COUNT .assign 0 ;
; --------------------------------------------------------------
; BRMACC0
;
BRMACC0 .assign 153
BRMACC0_SYM1ST .assign 8 ;
BRMACC0_SYM2ND .assign 0 ;
; --------------------------------------------------------------
; BRMACC1
;
BRMACC1 .assign 154
BRMACC1_METRIC01 .assign 8 ;
BRMACC1_METRIC00 .assign 0 ;
; --------------------------------------------------------------
; BRMACC2
;
BRMACC2 .assign 155
BRMACC2_METRIC11 .assign 8 ;
BRMACC2_METRIC10 .assign 0 ;
; --------------------------------------------------------------
; VITACCCTRL
;
VITACCCTRL .assign 156
VITACCCTRL_POLYNOM1 .assign 9 ;
VITACCCTRL_POLYNOM0 .assign 2 ;
VITACCCTRL_CODELENGTH .assign 0 ;
; --------------------------------------------------------------
; VITACCRDBIT
;
VITACCRDBIT .assign 157
VITACCRDBIT_RXBIT .assign 0 ;
; --------------------------------------------------------------
; MCETRCSEND
;
MCETRCSEND .assign 158
MCETRCSEND_SEND .assign 0 ;
; --------------------------------------------------------------
; MCETRCBUSY
;
MCETRCBUSY .assign 159
MCETRCBUSY_BUSY .assign 0 ;
; --------------------------------------------------------------
; MCETRCCMD
;
MCETRCCMD .assign 160
MCETRCCMD_PARCNT .assign 8 ;
MCETRCCMD_PKTHDR .assign 0 ;
; --------------------------------------------------------------
; MCETRCPAR0
;
MCETRCPAR0 .assign 161
MCETRCPAR0_PAR0 .assign 0 ;
; --------------------------------------------------------------
; MCETRCPAR1
;
MCETRCPAR1 .assign 162
MCETRCPAR1_PAR1 .assign 0 ;
; --------------------------------------------------------------
; RDCAPT0
;
RDCAPT0 .assign 163
RDCAPT0_DEMDSBU1 .assign 15 ;
RDCAPT0_DEMC1BEX .assign 14 ;
RDCAPT0_DEMSOFD0 .assign 13 ;
RDCAPT0_DEMLQIE0 .assign 12 ;
RDCAPT0_DEMSTIM1 .assign 11 ;
RDCAPT0_DEMSTIM0 .assign 10 ;
RDCAPT0_DEMFIFE2 .assign 9 ;
RDCAPT0_DEMPDIF0 .assign 8 ;
RDCAPT0_DEMCA2P0 .assign 7 ;
RDCAPT0_DEMFIDC4 .assign 6 ;
RDCAPT0_DEMFIDC3 .assign 5 ;
RDCAPT0_DEMMGEX2 .assign 4 ;
RDCAPT0_DEMMGEX1 .assign 3 ;
RDCAPT0_DEMDSBU0 .assign 2 ;
RDCAPT0_DEMCODC4 .assign 1 ;
RDCAPT0_DEMCODC3 .assign 0 ;
; --------------------------------------------------------------
; DEMCODC3
;
DEMCODC3 .assign 164
DEMCODC3_ESTOUTI .assign 0 ;
; --------------------------------------------------------------
; DEMCODC4
;
DEMCODC4 .assign 165
DEMCODC4_ESTOUTQ .assign 0 ;
; --------------------------------------------------------------
; DEMMGEx1
;
DEMMGEX1 .assign 166
DEMMGEX1_MGE1ESTOUT .assign 0 ;
; --------------------------------------------------------------
; DEMMGEx2
;
DEMMGEX2 .assign 167
DEMMGEX2_MGE2ESTOUT .assign 0 ;
; --------------------------------------------------------------
; DEMFIDC3
;
DEMFIDC3 .assign 168
DEMFIDC3_ESTOUTI .assign 0 ;
; --------------------------------------------------------------
; DEMFIDC4
;
DEMFIDC4 .assign 169
DEMFIDC4_ESTOUTQ .assign 0 ;
; --------------------------------------------------------------
; DEMCA2P0
;
DEMCA2P0 .assign 170
DEMCA2P0_PHASE .assign 0 ;
; --------------------------------------------------------------
; DEMPDIF0
;
DEMPDIF0 .assign 171
DEMPDIF0_PDIFF .assign 0 ;
; --------------------------------------------------------------
; DEMC1BE3
;
DEMC1BE3 .assign 172
DEMC1BE3_CORRVALUEA .assign 0 ;
; --------------------------------------------------------------
; DEMC1BE4
;
DEMC1BE4 .assign 173
DEMC1BE4_CORRVALUEB .assign 0 ;
; --------------------------------------------------------------
; DEMC1BE5
;
DEMC1BE5 .assign 174
DEMC1BE5_CORRVALUEC .assign 0 ;
; --------------------------------------------------------------
; DEMFIFE2
;
DEMFIFE2 .assign 175
DEMFIFE2_FINEFOCEST .assign 0 ;
; --------------------------------------------------------------
; DEMDSBU0
;
DEMDSBU0 .assign 176
DEMDSBU0_RDPOUT .assign 0 ;
; --------------------------------------------------------------
; DEMDSBU1
;
DEMDSBU1 .assign 177
DEMDSBU1_AVGVAL .assign 0 ;
; --------------------------------------------------------------
; DEMSTIM0
;
DEMSTIM0 .assign 178
DEMSTIM0_EVENTS .assign 0 ;
; --------------------------------------------------------------
; DEMSTIM1
;
DEMSTIM1 .assign 179
DEMSTIM1_GARDNERERROR .assign 4 ;
DEMSTIM1_DELTA .assign 0 ;
; --------------------------------------------------------------
; DEMSWQU1
;
DEMSWQU1 .assign 180
DEMSWQU1_MAFCCOMPVAL .assign 2 ;
DEMSWQU1_SWSEL .assign 1 ;
DEMSWQU1_SYNCED .assign 0 ;
; --------------------------------------------------------------
; DEMLQIE0
;
DEMLQIE0 .assign 181
DEMLQIE0_LQI .assign 0 ;
; --------------------------------------------------------------
; DEMSOFD0
;
DEMSOFD0 .assign 182
DEMSOFD0_SOFTSYMBOL .assign 0 ;
; --------------------------------------------------------------
; RDCAPT1
;
RDCAPT1 .assign 183
RDCAPT1_DEMHDIS0 .assign 13 ;
RDCAPT1_DEMFB2P2 .assign 12 ;
RDCAPT1_DEMPHAC .assign 11 ;
RDCAPT1_DEMMAFI5 .assign 10 ;
RDCAPT1_DEMMLSE4BITS .assign 9 ;
RDCAPT1_DEMPNSOFT .assign 8 ;
RDCAPT1_DEMMLSEBIT .assign 7 ;
RDCAPT1_DEMTHRD4 .assign 6 ;
RDCAPT1_DEMBDEC0 .assign 5 ;
RDCAPT1_DEMBDEC1 .assign 4 ;
RDCAPT1_DEMCHFI0 .assign 3 ;
RDCAPT1_DEMCHFI1 .assign 2 ;
RDCAPT1_DEMFRAC4 .assign 1 ;
RDCAPT1_DEMFRAC5 .assign 0 ;
; --------------------------------------------------------------
; DEMTHRD4
;
DEMTHRD4 .assign 184
DEMTHRD4_DECISION .assign 0 ;
; --------------------------------------------------------------
; DEMMLSEBIT
;
DEMMLSEBIT .assign 185
DEMMLSEBIT_MLSEBIT .assign 0 ;
; --------------------------------------------------------------
; DEMMLSE4BITS
;
DEMMLSE4BITS .assign 186
DEMMLSE4BITS_MLSE4BITS .assign 0 ;
; --------------------------------------------------------------
; DEMBDEC0
;
DEMBDEC0 .assign 187
DEMBDEC0_IVAL .assign 0 ;
; --------------------------------------------------------------
; DEMBDEC1
;
DEMBDEC1 .assign 188
DEMBDEC1_QVAL .assign 0 ;
; --------------------------------------------------------------
; DEMCHFI0
;
DEMCHFI0 .assign 189
DEMCHFI0_IVAL .assign 0 ;
; --------------------------------------------------------------
; DEMCHFI1
;
DEMCHFI1 .assign 190
DEMCHFI1_QVAL .assign 0 ;
; --------------------------------------------------------------
; DEMFRAC4
;
DEMFRAC4 .assign 191
DEMFRAC4_IVAL .assign 0 ;
; --------------------------------------------------------------
; DEMFRAC5
;
DEMFRAC5 .assign 192
DEMFRAC5_QVAL .assign 0 ;
; --------------------------------------------------------------
; DEMPNSOFT
;
DEMPNSOFT .assign 193
DEMPNSOFT_PNSOFT .assign 0 ;
; --------------------------------------------------------------
; DEMMAFI5
;
DEMMAFI5 .assign 194
DEMMAFI5_MAFIOUT .assign 0 ;
; --------------------------------------------------------------
; DEMC1BE6
;
DEMC1BE6 .assign 195
DEMC1BE6_VAL .assign 0 ;
; --------------------------------------------------------------
; DEMC1BE7
;
DEMC1BE7 .assign 196
DEMC1BE7_VAL .assign 0 ;
; --------------------------------------------------------------
; DEMC1BE8
;
DEMC1BE8 .assign 197
DEMC1BE8_VAL .assign 0 ;
; --------------------------------------------------------------
; DEMC1BE9
;
DEMC1BE9 .assign 198
DEMC1BE9_VAL .assign 0 ;
; --------------------------------------------------------------
; DEMC1BEA
;
DEMC1BEA .assign 199
DEMC1BEA_QUALB .assign 6 ;
DEMC1BEA_QUALA .assign 0 ;
; --------------------------------------------------------------
; MDMSPAR0
;
MDMSPAR0 .assign 200
MDMSPAR0_VAL .assign 0 ;
; --------------------------------------------------------------
; MDMSPAR1
;
MDMSPAR1 .assign 201
MDMSPAR1_VAL .assign 0 ;
; --------------------------------------------------------------
; MDMSPAR2
;
MDMSPAR2 .assign 202
MDMSPAR2_VAL .assign 0 ;
; --------------------------------------------------------------
; MDMSPAR3
;
MDMSPAR3 .assign 203
MDMSPAR3_VAL .assign 0 ;
; --------------------------------------------------------------
; DEMSOFD1
;
DEMSOFD1 .assign 204
DEMSOFD1_SOFTX0 .assign 0 ;
; --------------------------------------------------------------
; DEMSOFD2
;
DEMSOFD2 .assign 205
DEMSOFD2_SOFTX1 .assign 0 ;
; --------------------------------------------------------------
; DEMSOFD3
;
DEMSOFD3 .assign 206
DEMSOFD3_SOFTX2 .assign 0 ;
; --------------------------------------------------------------
; DEMSOFD4
;
DEMSOFD4 .assign 207
DEMSOFD4_SOFTX3 .assign 0 ;
; --------------------------------------------------------------
; DEMC1BE14
;
DEMC1BE14 .assign 208
DEMC1BE14_CORRVALUEE .assign 0 ;
; --------------------------------------------------------------
; DEMC1BE15
;
DEMC1BE15 .assign 209
DEMC1BE15_CORRVALUEF .assign 0 ;
; --------------------------------------------------------------
; DEMC1BE16
;
DEMC1BE16 .assign 210
DEMC1BE16_VAL .assign 0 ;
; --------------------------------------------------------------
; DEMC1BE17
;
DEMC1BE17 .assign 211
DEMC1BE17_VAL .assign 0 ;
; --------------------------------------------------------------
; DEMC1BE18
;
DEMC1BE18 .assign 212
DEMC1BE18_VAL .assign 0 ;
; --------------------------------------------------------------
; DEMC1BE19
;
DEMC1BE19 .assign 213
DEMC1BE19_VAL .assign 0 ;
; --------------------------------------------------------------
; DEMC1BE20
;
DEMC1BE20 .assign 214
DEMC1BE20_CORRVALUEG .assign 0 ;
; --------------------------------------------------------------
; DEMDSBU3
;
DEMDSBU3 .assign 215
DEMDSBU3_WRPOUT .assign 0 ;
; --------------------------------------------------------------
; MCEDUMP0
;
MCEDUMP0 .assign 216
MCEDUMP0_DONE .assign 0 ;
; --------------------------------------------------------------
; MCEGPO0
;
MCEGPO0 .assign 217
MCEGPO0_HWDATAMUX .assign 11 ;
MCEGPO0_HWCLKSTRETCH .assign 9 ;
MCEGPO0_HWCLKMUX .assign 5 ;
MCEGPO0_FWCTRL .assign 4 ;
MCEGPO0_GPO3 .assign 3 ;
MCEGPO0_GPO2 .assign 2 ;
MCEGPO0_GPO1 .assign 1 ;
MCEGPO0_GPO0 .assign 0 ;
; --------------------------------------------------------------
; DEMPHAC8
;
DEMPHAC8 .assign 218
DEMPHAC8_METRIC01 .assign 8 ;
DEMPHAC8_METRIC00 .assign 0 ;
; --------------------------------------------------------------
; DEMPHAC9
;
DEMPHAC9 .assign 219
DEMPHAC9_METRIC11 .assign 8 ;
DEMPHAC9_METRIC10 .assign 0 ;
; --------------------------------------------------------------
; DEMFB2P2
;
DEMFB2P2 .assign 220
DEMFB2P2_VAL .assign 0 ;
; --------------------------------------------------------------
; DEMHDIS0
;
DEMHDIS0 .assign 221
DEMHDIS0_VAL .assign 0 ;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;; mce_ram_bank.asm
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
.DEFINE LMD_DATA_SPACE 1 ;; LMD Data Space (Tables)
.DEFINE MDMCONF_IQDUMP 12 ;; Configuration Information
.DEFINE MAIN 48 ;; Main Program
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;; dbg.asm
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
__DBG__ .assign 1
;;; Include file for handling debug print in TOPsm
;;; --------------------------------------------------------------------------------
;;; Macro for handling code generated from DBG_PRINT0
.MACRO _DBG0 cmd
.ifdef __DBG__
lli \cmd, r0
jsr _DBG_PRINT
.endif __DBG__
.ENDM
;;; --------------------------------------------------------------------------------
;;; Macro for handling code generated from DBG_PRINT1
.MACRO _DBG1 cmd, reg0
.ifdef __DBG__
lli \cmd, r0
output \reg0, MCETRCPAR0
jsr _DBG_PRINT
.endif __DBG__
.ENDM
;;; --------------------------------------------------------------------------------
;;; Macro for handling code generated from DBG_PRINT2
.MACRO _DBG2 cmd, reg0, reg1
.ifdef __DBG__
lli \cmd, r0
output \reg0, MCETRCPAR0
output \reg1, MCETRCPAR1
jsr _DBG_PRINT
.endif __DBG__
.ENDM
;;; --------------------------------------------------------------------------------
;;; Macro for inserting handling code for debug printing - insert once in source file
.MACRO DBG_FUNC
.ifdef __DBG__
;;; DBG_PRINT
;;; R0 = pkt hdr
_DBG_PRINT:
output r0, MCETRCCMD ; R0 = pkt hdr
_DBG_PRINT_WAIT:
input MCETRCBUSY, r0 ; Wait until BUSY is released
btst 0, r0 ; Test bit 0
bne _DBG_PRINT_WAIT
outbset MCETRCSEND_SEND, MCETRCSEND
rts
.endif __DBG__
.ENDM
Reference in New Issue View Git Blame Copy Permalink