727 lines
19 KiB
Plaintext
727 lines
19 KiB
Plaintext
0000 .DATA 0x0000
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0000 .DATA 0x0000
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0000 .DATA 0x0000
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0000 .DATA 0x0000
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0000 .DATA 0x0000
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0000 .DATA 0x0000
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0000 .DATA 0x0000
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0000 .DATA 0x0000
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0000 .DATA 0x0000
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0000 .DATA 0x0000
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0000 .DATA 0x0000
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0000 .DATA 0x0000
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0000 .DATA 0x0000
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0000 .DATA 0x0000
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0001 .DATA 0x0001
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0003 .DATA 0x0003
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0007 .DATA 0x0007
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000f .DATA 0x000F
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0017 .DATA 0x0017
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003f .DATA 0x003F
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0043 .DATA 0x0043
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0050 .DATA 0x0050
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0054 .DATA 0x0054
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0080 .DATA 0x0080
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0082 .DATA 0x0082
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017f .DATA 0x017F
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0300 .DATA 0x0300
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0387 .DATA 0x0387
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0510 .DATA 0x0510
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0006 .DATA 0x06
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06f0 .DATA 0x06F0
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07ff .DATA 0x07FF
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0800 .DATA 0x0800
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091e .DATA 0x091E
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0c30 .DATA 0x0C30
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0fff .DATA 0x0FFF
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2fcf .DATA 0x2FCF
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3d1f .DATA 0x3D1F
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3f9d .DATA 0x3F9D
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4074 .DATA 0x4074
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5014 .DATA 0x5014
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8000 .DATA 0x8000
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8080 .DATA 0x8080
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aa00 .DATA 0xAA00
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c02f .DATA 0xC02F
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f800 .DATA 0xF800
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ff00 .DATA 0xFF00
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1611 add 1, r1
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1611 add 1, r1
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1612 add 1, r2
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1612 add 1, r2
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1613 add 1, r3
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1618 add 1, r8
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1618 add 1, r8
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161c add 1, r12
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1610 add 1,r0
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1630 add 3, r0
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1630 add 3,r0
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1401 add r0, r1
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1402 add r0, r2
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1404 add r0, r4
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14bc add r11, r12
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14bc add r11, r12
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1426 add r2, r6
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1426 add r2, r6
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1426 add r2, r6
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0620 and 2, r0
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0622 and 2, r2
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0633 and 3, r3
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063e and 3, r14
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0670 and 7, r0
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0410 and r1, r0
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0410 and r1,r0
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0410 and r1,r0
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0420 and r2, r0
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2a70 bclr 7, r0
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2a73 bclr 7, r3
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41a4 beq CAPT_FREQUENCY
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426a beq GEN_FSK_AVG_LEN_CORRECT
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427c beq GEN_FSK_DSBU_AVG_LEN_16_SYMBOLS_CHECK
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4289 beq GEN_FSK_DSBU_AVG_LEN_8_SYMBOLS
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41b8 beq IIR_K4
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41bf beq IIR_K8
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4166 beq LOOP_SAMPLES_FIFO_BLIND
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4173 beq LOOP_SAMPLES_FIFO_BLIND_DEMFRAC4WR
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417e beq LOOP_SAMPLES_FIFO_BLIND_DEMFRAC5WR
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4224 beq LOOP_SAMPLES_FIFO_SYNC
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4231 beq LOOP_SAMPLES_FIFO_SYNC_DEMFRAC4WR
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423c beq LOOP_SAMPLES_FIFO_SYNC_DEMFRAC5WR
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4199 beq LOOP_SAMPLES_TRANSPARENT_FIFO
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40bf beq MTX_Iqdump_Common_Preamble_16bitSyncWord
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40c9 beq MTX_Iqdump_Common_Preamble_RFESEND
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40ee beq MTX_Iqdump_Common_Preamble_Send_One_SW
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412e beq MTX_MFSK_SymbolLoop
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41c6 beq NO_IIR_FILTER
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40a0 beq ZERO_DONE
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49e2 bmi Neg_Sat
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45a4 bne CAPT_FREQUENCY
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45f3 bne DUMP_SAMPLES
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4618 bne DUMP_SAMPLES_FIFO
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457e bne LOOP_SAMPLES_FIFO_BLIND_DEMFRAC5WR
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463c bne LOOP_SAMPLES_FIFO_SYNC_DEMFRAC5WR
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44e2 bne MTX_Iqdump_Common_Preamble_Loop
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4526 bne MTX_MFSK_ToneLoop
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464c bne RFE_Started
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4572 bne TEST_PATTERN_ADD_BLIND
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4630 bne TEST_PATTERN_ADD_SYNC
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46d1 bne _DBG_PRINT_WAIT
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4eb3 bpl MRX_GenFSK_CommonEnd
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4eb3 bpl MRX_GenFSK_CommonEnd
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4eb3 bpl MRX_GenFSK_CommonEnd
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4cc1 bpl MTX_Iqdump_Common_Preamble_ShortSyncWord
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4de0 bpl Pos_Sat
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2200 btst 0, r0
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2200 btst 0, r0
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2201 btst 0, r1
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2201 btst 0, r1
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2201 btst 0, r1
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2201 btst 0, r1
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2210 btst 1, r0
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2210 btst 1, r0
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22f0 btst 15, r0
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2230 btst 3, r0
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2263 btst 6, r3
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2273 btst 7, r3
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2200 btst MCEEVENT2_C1BE_A_POS_PEAK, r0
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2200 btst MCEEVENT2_C1BE_A_POS_PEAK, r0
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1e04 cmp 0, r4
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1e04 cmp 0, r4
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1e04 cmp 0, r4
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1e09 cmp 0, r9
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1e09 cmp 0, r9
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1e0e cmp 0, r14
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1e20 cmp 2, r0
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1e22 cmp 2, r2
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1e2e cmp 2, r14
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1e3e cmp 3, r14
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1c01 cmp r0, r1
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1c03 cmp r0, r3
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1c10 cmp r1, r0
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1ca8 cmp r10, r8
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1ca8 cmp r10, r8
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1cd0 cmp r13, r0
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1ce0 cmp r14, r0
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1c4c cmp r4, r12
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1c4c cmp r4, r12
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1c4c cmp r4, r12
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8990 input BRMACC0, r0
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8980 input COUNT1RES, r0
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8980 input COUNT1RES, r0
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8982 input COUNT1RES, r2
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8982 input COUNT1RES, r2
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8984 input COUNT1RES, r4
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8984 input COUNT1RES, r4
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8440 input DEMC1BE0, r0
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8af0 input DEMFIFE2,r0
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8bf0 input DEMFRAC4, r0
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8bf0 input DEMFRAC4, r0
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8c00 input DEMFRAC5, r0
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8c00 input DEMFRAC5, r0
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8b54 input DEMLQIE0, r4
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8ab2 input DEMPDIF0, r2
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80b0 input MCEEVENT2, r0
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80b0 input MCEEVENT2, r0
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89f0 input MCETRCBUSY, r0
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8162 input MDMAPI, r2
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8170 input MDMCMDPAR0, r0
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8170 input MDMCMDPAR0, r0
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8170 input MDMCMDPAR0, r0
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8173 input MDMCMDPAR0, r3
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8184 input MDMCMDPAR1, r4
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8184 input MDMCMDPAR1, r4
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8184 input MDMCMDPAR1, r4
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8190 input MDMCMDPAR2, r0
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81d1 input MDMFIFORD, r1
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8210 input MDMFIFOSTA, r0
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8212 input MDMFIFOSTA, r2
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8c90 input MDMSPAR1, r0
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8ca1 input MDMSPAR2, r1
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8ca1 input MDMSPAR2, r1
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8ca1 input MDMSPAR2, r1
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8ca1 input MDMSPAR2, r1
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81b0 input MDMSTATUS, r0
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81b1 input MDMSTATUS, r1
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84a0 input MDMSYNC0, r0
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84a0 input MDMSYNC0, r0
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84a2 input MDMSYNC0, r2
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84b0 input MDMSYNC1, r0
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84b0 input MDMSYNC1, r0
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84b0 input MDMSYNC1, r0
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84b4 input MDMSYNC1, r4
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84c0 input MDMSYNC2, r0
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84c0 input MDMSYNC2, r0
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84d0 input MDMSYNC3, r0
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84d0 input MDMSYNC3, r0
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84d0 input MDMSYNC3, r0
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8630 input MODCTRL, r0
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8240 input RFERCEV, r0
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8230 input RFESEND, r0
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89ce input VITACCCTRL, r14
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6c01 jmp (r1)
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607d jmp CMD_OK_END
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607d jmp CMD_OK_END
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607d jmp CMD_OK_END
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607d jmp CMD_OK_END
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607d jmp CMD_OK_END
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6044 jmp CMD_PROC
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6295 jmp GEN_FSK_CALC_DEMSWIMBAL
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627e jmp GEN_FSK_DSBU_AVG_LEN_16_SYMBOLS
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61c7 jmp HARD_DECISION
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61c7 jmp HARD_DECISION
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61c7 jmp HARD_DECISION
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61fa jmp LOOP_SAMPLES
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6148 jmp LOOP_SAMPLES_BLIND
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6166 jmp LOOP_SAMPLES_FIFO_BLIND
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6224 jmp LOOP_SAMPLES_FIFO_SYNC
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6199 jmp LOOP_SAMPLES_TRANSPARENT_FIFO
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6088 jmp MCFG_Entry
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6088 jmp MCFG_Entry
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6088 jmp MCFG_Entry
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6088 jmp MCFG_Entry
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6088 jmp MCFG_Entry
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6088 jmp MCFG_Entry
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6087 jmp MNOP_Entry
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6087 jmp MNOP_Entry
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6087 jmp MNOP_Entry
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6087 jmp MNOP_Entry
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6087 jmp MNOP_Entry
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6087 jmp MNOP_Entry
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6087 jmp MNOP_Entry
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6087 jmp MNOP_Entry
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6087 jmp MNOP_Entry
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6087 jmp MNOP_Entry
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6087 jmp MNOP_Entry
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6087 jmp MNOP_Entry
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6087 jmp MNOP_Entry
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6087 jmp MNOP_Entry
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6087 jmp MNOP_Entry
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6087 jmp MNOP_Entry
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6087 jmp MNOP_Entry
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6087 jmp MNOP_Entry
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6087 jmp MNOP_Entry
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6087 jmp MNOP_Entry
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6087 jmp MNOP_Entry
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6087 jmp MNOP_Entry
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6087 jmp MNOP_Entry
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6087 jmp MNOP_Entry
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6087 jmp MNOP_Entry
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614e jmp MRX_Entry_FIFO_BLIND
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614e jmp MRX_Entry_FIFO_BLIND
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6200 jmp MRX_Entry_FIFO_SYNC
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613e jmp MRX_Entry_REG_BLIND
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61e4 jmp MRX_Entry_REG_SYNC
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6186 jmp MRX_Entry_TRANSPARENT_FIFO
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6244 jmp MRX_SETUP
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6104 jmp MTX_Entry
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6104 jmp MTX_Entry
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6104 jmp MTX_Entry
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6104 jmp MTX_Entry
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6104 jmp MTX_Entry
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60c9 jmp MTX_Iqdump_Common_Preamble_RFESEND
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60c9 jmp MTX_Iqdump_Common_Preamble_RFESEND
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6112 jmp MTX_MFSK
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6030 jmp START_PROCESS
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61ee jmp SYNC_SEARCH
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6213 jmp SYNC_SEARCH_FIFO
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65d0 jsr MDMFIFOWR_AND_WAIT10
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65d0 jsr MDMFIFOWR_AND_WAIT10
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65d0 jsr MDMFIFOWR_AND_WAIT10
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65d0 jsr MDMFIFOWR_AND_WAIT10
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66ca jsr MODCTRL_CLR
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66ca jsr MODCTRL_CLR
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6644 jsr MRX_SETUP
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6644 jsr MRX_SETUP
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6644 jsr MRX_SETUP
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6644 jsr MRX_SETUP
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6644 jsr MRX_SETUP
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64a5 jsr MTX_Iqdump_Common_Preamble
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64f5 jsr MTX_Iqdump_Termination
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64f5 jsr MTX_Iqdump_Termination
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65d9 jsr SignExt_and_Saturate
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65d9 jsr SignExt_and_Saturate
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65d9 jsr SignExt_and_Saturate
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65d9 jsr SignExt_and_Saturate
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66d0 jsr _DBG_PRINT
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66d0 jsr _DBG_PRINT
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66d0 jsr _DBG_PRINT
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66d0 jsr _DBG_PRINT
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66d0 jsr _DBG_PRINT
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66d0 jsr _DBG_PRINT
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66d0 jsr _DBG_PRINT
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66d0 jsr _DBG_PRINT
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66d0 jsr _DBG_PRINT
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66d0 jsr _DBG_PRINT
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66d0 jsr _DBG_PRINT
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66d0 jsr _DBG_PRINT
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66d0 jsr _DBG_PRINT
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66d0 jsr _DBG_PRINT
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66d0 jsr _DBG_PRINT
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c080 lli "########################### Blind REGISTER MODE -> IQ Dump starting at once ########################"
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c090 lli "########################### Blind RFC FIFO Mode -> IQ Dump starting at once (DataRate <= 12,5 kbps) ########################"
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c0a0 lli "########################### Transparent FIFO Mode -> PDIFF streaming starting at once ########################"
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c0b0 lli "########################### Transparent FIFO Mode Stop AGC ########################"
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c0c0 lli "########################### IQ Dump REGISTER MODE, RX started, Wait for Sync ########################"
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c0d0 lli "########################### Sync Found REGISTER MODE -> IQ Dump starting ########################"
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c0e0 lli "########################### IQ Dump through RFC FIFO, RX started, Wait for Sync (DataRate <= 12.5 kbps) ########################"
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c0f0 lli "########################### Sync Found RFC FIFO MODE-> IQ samples through FIFO starting ########################"
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c100 lli "########################### RX Started ########################"
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c110 lli "All bits received, MCE Ending"
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c040 lli "IQDump___ NoFEC, TX Started"
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c050 lli "IQDump___ Multi-level FSK TX Mode"
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c030 lli "MCFG - IQ Dump Configuration"
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c060 lli "Starting MFSK Symbol Loop"
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c070 lli "Stopping MFSK Symbol Loop"
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c000 lli 0x0, r0
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c000 lli 0x0, r0
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c030 lli 0x03, r0
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c030 lli 0x03,r0
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c040 lli 0x04, r0
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c100 lli 0x10, r0
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ffc0 lli 0x3FC, r0
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c801 lli 0x80, r1
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cd90 lli 0xD9, r0
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c0b0 lli 11, r0
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c0f3 lli 15, r3
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c0f5 lli 15, r5
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c100 lli 16, r0
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c100 lli 16, r0
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c020 lli 2, r0
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c18b lli 24, r11
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c18b lli 24, r11
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c035 lli 3, r5
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c035 lli 3, r5
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c035 lli 3, r5
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c035 lli 3, r5
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c1f2 lli 31, r2
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c200 lli 32, r0
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c050 lli 5, r0
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c050 lli 5, r0
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c4f2 lli DEMFB2P0, r2
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c0c1 lli MDMCONF_IQDUMP, r1
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c2b2 lli MDMCONF_IQDUMP_FIRST_REG, r2
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c4e0 lli MDMCONF_IQDUMP_LAST_REG, r0
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c750 lli VITCTRL, r0
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6f13 lmd (r1), r3
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78a0 lmd CORR_DEFG_THR, r0
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7842 lmd DEMC1BE0_MASKA_BITS, r2
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7810 lmd DEMENABLE0_RX_IQDUMP, r0
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7820 lmd DEMENABLE1_RX_IQDUMP, r0
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7851 lmd IQDUMP_MASK_BITS_15_8, r1
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7851 lmd IQDUMP_MASK_BITS_15_8, r1
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787d lmd IQDUMP_MAX_POS_VAL, r13
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787d lmd IQDUMP_MAX_POS_VAL, r13
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788e lmd IQDUMP_MIN_NEG_VAL, r14
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788e lmd IQDUMP_MIN_NEG_VAL, r14
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786a lmd IQDUMP_TEST_MAX_VAL, r10
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786a lmd IQDUMP_TEST_MAX_VAL, r10
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789d lmd TRANSPARENT_CAPT, r13
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78b0 lmd TX_TONE_COUNT, r0
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7830 lmd VITACCCTRL_REG_DEFAULT,r0
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69d2 loop LOOP_MDMFIFOWR
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6960 loop LOOP_SAMPLES_FIFO_BLIND_WAIT
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6a20 loop LOOP_SAMPLES_FIFO_SYNC_WAIT
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6992 loop LOOP_SAMPLES_TRANSPARENT_FIFO_WAIT
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688e loop MCFG_Iqdump_Loop
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68bc loop MTX_Iqdump_Common_Preamble_SyncWord_ShiftLoop1
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68c7 loop MTX_Iqdump_Common_Preamble_SyncWord_ShiftLoop2
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689d loop ZERO_LOOP
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1200 mov 0, r0
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1202 mov 0, r2
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1203 mov 0, r3
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1204 mov 0, r4
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1205 mov 0, r5
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1208 mov 0, r8
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1208 mov 0, r8
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120c mov 0, r12
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120c mov 0, r12
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120c mov 0, r12
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13f0 mov 0x1F, r0
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13f3 mov 0x1F, r3
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13f3 mov 0x1F, r3
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1218 mov 1, r8
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1218 mov 1, r8
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1220 mov 2, r0
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1210 mov CMD_OK, r0
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1101 mov pc, r1
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1000 mov r0, r0
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1000 mov r0, r0
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1000 mov r0, r0
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1001 mov r0, r1
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1001 mov r0, r1
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1003 mov r0, r3
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1013 mov r1, r3
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1015 mov r1, r5
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10a9 mov r10, r9
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10a9 mov r10, r9
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10a9 mov r10, r9
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10a9 mov r10, r9
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10d0 mov r13, r0
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10e0 mov r14, r0
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1020 mov r2, r0
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1021 mov r2, r1
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1026 mov r2, r6
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1030 mov r3, r0
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1056 mov r5, r6
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1056 mov r5, r6
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1056 mov r5, r6
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1065 mov r6, r5
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1065 mov r6, r5
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1065 mov r6, r5
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1080 mov r8, r0
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1080 mov r8, r0
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1090 mov r9, r0
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1090 mov r9, r0
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0000 nop
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0000 nop
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0000 nop
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0004 or r0,r4
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0010 or r1, r0
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0012 or r1, r2
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0020 or r2, r0
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0020 or r2, r0
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0042 or r4, r2
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a230 outbclr 0, RFESEND
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a235 outbclr 5, RFESEND
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a35d outbclr DEMMISC2_MLSERUN,DEMMISC2
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a4e5 outbclr DEMSWQU0_RUN, DEMSWQU0
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a0d2 outbclr MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0
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a0d2 outbclr MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0
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a0d2 outbclr MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0
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a0d2 outbclr MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0
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a0d2 outbclr MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0
|
|
a0d2 outbclr MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0
|
|
a0d3 outbclr MCEEVENT0_FIFO_ERR_UNDERFLOW, MCEEVENTMSK0
|
|
a0d0 outbclr MCEEVENT0_MDMAPI_WR, MCEEVENTMSK0
|
|
a0d5 outbclr MCEEVENT0_RFECMD_IRQ, MCEEVENTMSK0
|
|
a0d1 outbclr MCEEVENT0_TIMER_IRQ, MCEEVENTMSK0
|
|
a0d1 outbclr MCEEVENT0_TIMER_IRQ, MCEEVENTMSK0
|
|
a0e1 outbclr MCEEVENT1_CLKEN_BAUD, MCEEVENTMSK1
|
|
a0e8 outbclr MCEEVENT1_RAT_EVENT0, MCEEVENTMSK1
|
|
a0e8 outbclr MCEEVENT1_RAT_EVENT0, MCEEVENTMSK1
|
|
a0f0 outbclr MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTMSK2
|
|
a0f0 outbclr MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTMSK2
|
|
a0f0 outbclr MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTMSK2
|
|
a0f0 outbclr MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTMSK2
|
|
a0f0 outbclr MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTMSK2
|
|
a0f0 outbclr MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTMSK2
|
|
a0f0 outbclr MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTMSK2
|
|
a0f3 outbclr MCEEVENT2_C1BE_B_POS_PEAK, MCEEVENTMSK2
|
|
a0f3 outbclr MCEEVENT2_C1BE_B_POS_PEAK, MCEEVENTMSK2
|
|
a0f3 outbclr MCEEVENT2_C1BE_B_POS_PEAK, MCEEVENTMSK2
|
|
a0f3 outbclr MCEEVENT2_C1BE_B_POS_PEAK, MCEEVENTMSK2
|
|
a0f3 outbclr MCEEVENT2_C1BE_B_POS_PEAK, MCEEVENTMSK2
|
|
a008 outbclr MDMENABLE_FB2PLL, MDMENABLE
|
|
a003 outbclr MDMENABLE_MODULATOR, MDMENABLE
|
|
a002 outbclr MDMENABLE_TIMEBASE, MDMENABLE
|
|
a630 outbclr MODCTRL_PREAMBLEINSERT, MODCTRL
|
|
a634 outbclr MODCTRL_SOFTTXENABLE, MODCTRL
|
|
b070 outbset 0, MCESTROBES0
|
|
b230 outbset 0,RFESEND
|
|
b230 outbset 0,RFESEND
|
|
b231 outbset 1, RFESEND
|
|
b231 outbset 1, RFESEND
|
|
b231 outbset 1, RFESEND
|
|
b235 outbset 5, RFESEND
|
|
b0d2 outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0
|
|
b0d2 outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0
|
|
b0d2 outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0
|
|
b0d2 outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0
|
|
b0d2 outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0
|
|
b112 outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTCLR0
|
|
b112 outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTCLR0
|
|
b112 outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTCLR0
|
|
b112 outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTCLR0
|
|
b112 outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTCLR0
|
|
b112 outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTCLR0
|
|
b112 outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTCLR0
|
|
b112 outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTCLR0
|
|
b112 outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTCLR0
|
|
b112 outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTCLR0
|
|
b118 outbset MCEEVENT0_CPEFWEVENT0, MCEEVENTCLR0
|
|
b0d3 outbset MCEEVENT0_FIFO_ERR_UNDERFLOW, MCEEVENTMSK0
|
|
b113 outbset MCEEVENT0_FIFO_ERR_UNDERFLOW, MCEEVENTCLR0
|
|
b0d0 outbset MCEEVENT0_MDMAPI_WR, MCEEVENTMSK0
|
|
b110 outbset MCEEVENT0_MDMAPI_WR, MCEEVENTCLR0
|
|
b0d5 outbset MCEEVENT0_RFECMD_IRQ, MCEEVENTMSK0
|
|
b115 outbset MCEEVENT0_RFECMD_IRQ, MCEEVENTCLR0
|
|
b0d1 outbset MCEEVENT0_TIMER_IRQ, MCEEVENTMSK0
|
|
b0d1 outbset MCEEVENT0_TIMER_IRQ, MCEEVENTMSK0
|
|
b111 outbset MCEEVENT0_TIMER_IRQ, MCEEVENTCLR0
|
|
b111 outbset MCEEVENT0_TIMER_IRQ, MCEEVENTCLR0
|
|
b111 outbset MCEEVENT0_TIMER_IRQ, MCEEVENTCLR0
|
|
b111 outbset MCEEVENT0_TIMER_IRQ, MCEEVENTCLR0
|
|
b0e1 outbset MCEEVENT1_CLKEN_BAUD, MCEEVENTMSK1
|
|
b121 outbset MCEEVENT1_CLKEN_BAUD, MCEEVENTCLR1
|
|
b121 outbset MCEEVENT1_CLKEN_BAUD, MCEEVENTCLR1
|
|
b121 outbset MCEEVENT1_CLKEN_BAUD, MCEEVENTCLR1
|
|
b0e0 outbset MCEEVENT1_PREAMBLE_DONE, MCEEVENTMSK1
|
|
b0e0 outbset MCEEVENT1_PREAMBLE_DONE, MCEEVENTMSK1
|
|
b120 outbset MCEEVENT1_PREAMBLE_DONE, MCEEVENTCLR1
|
|
b120 outbset MCEEVENT1_PREAMBLE_DONE, MCEEVENTCLR1
|
|
b120 outbset MCEEVENT1_PREAMBLE_DONE, MCEEVENTCLR1
|
|
b120 outbset MCEEVENT1_PREAMBLE_DONE, MCEEVENTCLR1
|
|
b0e8 outbset MCEEVENT1_RAT_EVENT0, MCEEVENTMSK1
|
|
b0e8 outbset MCEEVENT1_RAT_EVENT0, MCEEVENTMSK1
|
|
b128 outbset MCEEVENT1_RAT_EVENT0, MCEEVENTCLR1
|
|
b128 outbset MCEEVENT1_RAT_EVENT0, MCEEVENTCLR1
|
|
b0f0 outbset MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTMSK2
|
|
b0f0 outbset MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTMSK2
|
|
b130 outbset MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTCLR2
|
|
b130 outbset MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTCLR2
|
|
b130 outbset MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTCLR2
|
|
b130 outbset MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTCLR2
|
|
b074 outbset MCESTROBES0_EVENT0, MCESTROBES0
|
|
b074 outbset MCESTROBES0_EVENT0, MCESTROBES0
|
|
b074 outbset MCESTROBES0_EVENT0, MCESTROBES0
|
|
b074 outbset MCESTROBES0_EVENT0, MCESTROBES0
|
|
b074 outbset MCESTROBES0_EVENT0, MCESTROBES0
|
|
b9e0 outbset MCETRCSEND_SEND, MCETRCSEND
|
|
b006 outbset MDMENABLE_ADCDIG, MDMENABLE
|
|
b004 outbset MDMENABLE_DEMODULATOR, MDMENABLE
|
|
b008 outbset MDMENABLE_FB2PLL, MDMENABLE
|
|
b003 outbset MDMENABLE_MODULATOR, MDMENABLE
|
|
b003 outbset MDMENABLE_MODULATOR, MDMENABLE
|
|
b002 outbset MDMENABLE_TIMEBASE, MDMENABLE
|
|
b002 outbset MDMENABLE_TIMEBASE, MDMENABLE
|
|
b002 outbset MDMENABLE_TIMEBASE, MDMENABLE
|
|
b016 outbset MDMINIT_ADCDIG, MDMINIT
|
|
b014 outbset MDMINIT_DEMODULATOR, MDMINIT
|
|
b013 outbset MDMINIT_MODULATOR, MDMINIT
|
|
b013 outbset MDMINIT_MODULATOR, MDMINIT
|
|
b012 outbset MDMINIT_TIMEBASE, MDMINIT
|
|
b012 outbset MDMINIT_TIMEBASE, MDMINIT
|
|
b012 outbset MDMINIT_TIMEBASE, MDMINIT
|
|
b63c outbset MODCTRL_CDC_COL_RESTART, MODCTRL
|
|
b633 outbset MODCTRL_FECENABLE, MODCTRL
|
|
b630 outbset MODCTRL_PREAMBLEINSERT, MODCTRL
|
|
b634 outbset MODCTRL_SOFTTXENABLE, MODCTRL
|
|
ba3c outbset RDCAPT0_DEMLQIE0, RDCAPT0
|
|
ba38 outbset RDCAPT0_DEMPDIF0, RDCAPT0
|
|
ba38 outbset RDCAPT0_DEMPDIF0, RDCAPT0
|
|
b910 outbset TIMCTRL_ENABLETIMER, TIMCTRL
|
|
7203 outclr DEMENABLE0
|
|
7204 outclr DEMENABLE1
|
|
720d outclr MCEEVENTMSK0
|
|
720e outclr MCEEVENTMSK1
|
|
720f outclr MCEEVENTMSK2
|
|
7210 outclr MCEEVENTMSK3
|
|
7206 outclr MDMENABLE_ADCDIG, MDMENABLE
|
|
7204 outclr MDMENABLE_DEMODULATOR, MDMENABLE
|
|
7202 outclr MDMENABLE_TIMEBASE, MDMENABLE
|
|
721e outclr MDMFIFOWRCTRL
|
|
721b outclr MDMSTATUS
|
|
7263 outclr MODCTRL
|
|
722c outclr MODPRECTRL
|
|
7223 outclr RFESEND
|
|
7223 outclr RFESEND
|
|
7291 outclr TIMCTRL
|
|
7291 outclr TIMCTRL
|
|
7291 outclr TIMCTRL
|
|
7291 outclr TIMCTRL
|
|
9010 output r0, MDMINIT
|
|
9030 output r0, DEMENABLE0
|
|
9040 output r0, DEMENABLE1
|
|
9050 output r0, DEMINIT0
|
|
9060 output r0, DEMINIT1
|
|
9170 output r0, MDMCMDPAR0
|
|
91b0 output r0, MDMSTATUS
|
|
91e0 output r0, MDMFIFOWRCTRL
|
|
91e0 output r0, MDMFIFOWRCTRL
|
|
91f0 output r0, MDMFIFORDCTRL
|
|
91f0 output r0, MDMFIFORDCTRL
|
|
92c0 output r0, MODPRECTRL
|
|
92f0 output r0, MODSOFTTX
|
|
9380 output r0, DEMDSBU
|
|
9440 output r0, DEMC1BE0
|
|
9480 output r0, DEMC1BE11
|
|
9490 output r0, DEMC1BE12
|
|
9590 output r0, DEMC1BEREF0
|
|
95a0 output r0, DEMC1BEREF1
|
|
95b0 output r0, DEMC1BEREF2
|
|
95c0 output r0, DEMC1BEREF3
|
|
9630 output r0, MODCTRL
|
|
9640 output r0, MODPREAMBLE
|
|
9910 output r0, TIMCTRL
|
|
9930 output r0, TIMPERIOD
|
|
9930 output r0, TIMPERIOD
|
|
9970 output r0, COUNT1IN
|
|
9970 output r0, COUNT1IN
|
|
9970 output r0, COUNT1IN
|
|
9970 output r0, COUNT1IN
|
|
9970 output r0, COUNT1IN
|
|
9970 output r0, COUNT1IN
|
|
9990 output r0, BRMACC0
|
|
9a00 output r0, MCETRCCMD
|
|
99c0 output r0,VITACCCTRL
|
|
91c1 output r1, MDMFIFOWR
|
|
92f1 output r1, MODSOFTTX
|
|
9a3d output r13, RDCAPT0
|
|
9642 output r2, MODPREAMBLE
|
|
9722 output r2, DEMSWIMBAL
|
|
6e23 output r3, (r2)
|
|
6e23 output r3, (r2)
|
|
92c3 output r3, MODPRECTRL
|
|
94e3 output r3, DEMSWQU0
|
|
91b4 output r4, MDMSTATUS
|
|
9644 output r4, MODPREAMBLE
|
|
92c5 output r5, MODPRECTRL
|
|
9b75 output r5, RDCAPT1
|
|
9b75 output r5, RDCAPT1
|
|
9b75 output r5, RDCAPT1
|
|
9b75 output r5, RDCAPT1
|
|
91c6 output r6, MDMFIFOWR
|
|
7303 outset DEMENABLE0
|
|
7304 outset DEMENABLE1
|
|
7305 outset DEMINIT0
|
|
7305 outset DEMINIT0
|
|
7306 outset DEMINIT1
|
|
7306 outset DEMINIT1
|
|
7311 outset MCEEVENTCLR0
|
|
7311 outset MCEEVENTCLR0
|
|
7311 outset MCEEVENTCLR0
|
|
7311 outset MCEEVENTCLR0
|
|
7311 outset MCEEVENTCLR0
|
|
7311 outset MCEEVENTCLR0
|
|
7311 outset MCEEVENTCLR0
|
|
7311 outset MCEEVENTCLR0
|
|
7312 outset MCEEVENTCLR1
|
|
7312 outset MCEEVENTCLR1
|
|
7312 outset MCEEVENTCLR1
|
|
7312 outset MCEEVENTCLR1
|
|
7312 outset MCEEVENTCLR1
|
|
7312 outset MCEEVENTCLR1
|
|
7312 outset MCEEVENTCLR1
|
|
7312 outset MCEEVENTCLR1
|
|
7313 outset MCEEVENTCLR2
|
|
7391 outset TIMCTRL
|
|
7391 outset TIMCTRL
|
|
7000 rts
|
|
7000 rts
|
|
7000 rts
|
|
7000 rts
|
|
7000 rts
|
|
7000 rts
|
|
7000 rts
|
|
7000 rts
|
|
7000 rts
|
|
3126 sl0 2, r6
|
|
3130 sl0 3, r0
|
|
3136 sl0 3, r6
|
|
3151 sl0 5, r1
|
|
3151 sl0 5, r1
|
|
3152 sl0 5, r2
|
|
3154 sl0 5, r4
|
|
3150 sl0 5,r0
|
|
3180 sl0 8, r0
|
|
3180 sl0 8, r0
|
|
3182 sl0 8, r2
|
|
3182 sl0 8, r2
|
|
3184 sl0 8, r4
|
|
3184 sl0 8, r4
|
|
3162 sl0 DEMC1BE0_MASKA, r2
|
|
3911 sr0 1, r1
|
|
3912 sr0 1, r2
|
|
3914 sr0 1, r4
|
|
3924 sr0 2, r4
|
|
3930 sr0 3,r0
|
|
3952 sr0 5, r2
|
|
3963 sr0 6, r3
|
|
3976 sr0 7, r6
|
|
3980 sr0 8, r0
|
|
3982 sr0 8, r2
|
|
3983 sr0 8, r3
|
|
3832 sr0 r3, r2
|
|
3834 sr0 r3, r4
|
|
3d16 srx 1, r6
|
|
3d26 srx 2, r6
|
|
3d30 srx 3, r0
|
|
3d36 srx 3, r6
|
|
3d80 srx 8, r0
|
|
3d82 srx 8, r2
|
|
1a10 sub 1, r0
|
|
1a10 sub 1, r0
|
|
1a13 sub 1, r3
|
|
1a15 sub 1, r5
|
|
1a19 sub 1, r9
|
|
1a19 sub 1, r9
|
|
1a42 sub 4, r2
|
|
1a44 sub 4, r4
|
|
1a80 sub 8, r0
|
|
1a80 sub 8, r0
|
|
1a82 sub 8, r2
|
|
1a84 sub 8, r4
|
|
1802 sub r0, r2
|
|
1803 sub r0, r3
|
|
1820 sub r2,r0
|
|
1820 sub r2,r0
|
|
1830 sub r3, r0
|
|
1832 sub r3, r2
|
|
1850 sub r5, r0
|
|
1856 sub r5,r6
|
|
1856 sub r5,r6
|
|
7100 wait
|
|
7100 wait
|
|
7100 wait
|
|
7100 wait
|
|
7100 wait
|
|
7100 wait
|
|
7100 wait
|
|
7100 wait
|
|
7100 wait
|
|
7100 wait
|
|
7100 wait
|
|
7100 wait
|
|
7100 wait
|
|
7100 wait
|
|
7100 wait
|
|
7100 wait
|
|
7100 wait
|
|
7100 wait
|
|
7100 wait
|
|
7100 wait
|
|
7100 wait
|
|
7100 wait
|
|
7100 wait
|
|
7100 wait
|