rpi baremetal stuff
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32
jazelle.c
32
jazelle.c
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@ -39,6 +39,7 @@
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// newlib assumed
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#endif // platform
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@ -50,7 +51,7 @@
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// Cypress FX3 | ARM926EJ-S | 0x41069265 | 0x07926069 | 0x64100004
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// TI Nspire | ARM926EJ-S?| 0x41069265?| ??? | 0x64100004? // TODO
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// Wii Starlet | ARM926EJ-S?| ??? | ??? | ??? // TODO
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// RPi v1.2 B+ |ARM1176JZF-S| 0x410FB767 | 0x07B7617F | 0x74100064
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// RPi v1.2 B+ |ARM1176JZF-S| 0x410FB767 | 0x07B7617F | 0x74100064 // FIXME: insn enumeration broken due to caching or something
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// Ninty .3DS | ARM11MPCore| 0x410FB025?| ??? | 0x74100064? // TODO
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// ??? TODO | Cortex-A8 | ??? | ??? | ???
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// Xilinx Zynq7| Cortex-A9MP| 0x413FC090 | 0x4BA00477 | 0xF4100168
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@ -203,14 +204,15 @@ static void DC_FlushAll(void) {
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"add r1, r1, #0x40000000\n"
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"cmp r1, #0\n"
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"bne outer_loop\n"
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#elif __ARM_ARCH == 6 && defined(__ARM_ARCH_6KZ__)
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"mov r0, #0\n"
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"mcr p15, 0, r0, c7, c10, 0\n" // clean & flush entire data cache
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#elif __ARM_ARCH == 6 && defined(__ARM_ARCH_6KZ__)
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// FIXME: ARM11 code no worky
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"mov r0, #0\n"
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"mcr p15, 0, r0, c7, c14, 0\n" // Clean and Invalidate Entire Data Cache
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#else
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#error "wut"
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#endif
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"mov r0, #0\n"
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"mcr p15, 0, r0, c7, c10, 4 @ drain write buffer\n" // ARM9, ARM11 ok
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"bx lr\n"
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:
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@ -221,9 +223,22 @@ static void DC_FlushAll(void) {
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__attribute__((__unused__))
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static inline void DC_InvalidateAll(void) {
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asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r"(0)); // ARM9, ARM11 ok
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#if __ARM_ARCH == 6
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// FIXME: ARM11 code no worky
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asm volatile("mcr p15, 0, %0, c7, c7, 0" : : "r"(0)); // ARM9, ARM11 ok
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asm volatile("mcr p15, 0, %0, c8, c7, 0" : : "r"(0)); // invalidate tlb
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asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r"(0)); // dsb
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#endif
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}
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static inline void IC_InvalidateAll(void) {
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asm volatile("mcr p15, 0, %0, c7, c5, 0" : : "r"(0)); // ARM9, ARM11 ok
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#if __ARM_ARCH == 6
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// FIXME: ARM11 code no worky
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asm volatile("mcr p15, 0, %0, c7, c7, 0" : : "r"(0)); // ARM9, ARM11 ok
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asm volatile("mcr p15, 0, %0, c8, c7, 0" : : "r"(0)); // invalidate tlb
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asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r"(0)); // dsb
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asm volatile("mcr p15, 0, %0, c7, c5, 4" : : "r"(0)); // flush prefetch buffer
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#endif
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}
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#elif __ARM_ARCH == 7 && defined(__ARM_ARCH_7A__)
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#include "cache_cortexa.c" /* go sue me */
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@ -340,13 +355,15 @@ static void handler_idiv(void) {
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// r0 = 3
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// r1 = 4
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// r2 = 2
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// editing the above has no effect
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// editing the above has no effect (not on ARM9, nor on ARM11)
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// NOTE: these depend on the stack content, i.e. it's not a moving register
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// window. pushes happen in the following order: r0,r1,r2,r3
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// TODO: when the 'register stack cache' is full, what happens? does
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// it loop or does it act in a FIFO way, moving r0<-r1<-r2<-r3?
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// how can the fillrate be known??? (libjz says r5 & 3 but i
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// dont see anything like that, maybe its an ARM11 thing?)
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// TODO: Hackspire also says something about the low bits of r5, not
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// seeing this on ARM9 nor ARM11...
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// "r4: Copy of local variable 0. Only valid when local variable 0 is a
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// single word (i.e. int, float, or Object; not long or double)"
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// -Hackspire
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@ -526,8 +543,9 @@ static uint8_t bytecode_test1[] = {
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0x06, // iconst_3
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0x07, // iconst_4
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0x05, // iconst_2
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0xFE, // ??? (r5 readout)
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// FIXME: if we put 0xFE here instead, the end result is 11 on RPi. why?
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0x6C, // idiv
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0xFE, // ??? (r5 readout)
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0x04, // iconst_1
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0x60, // iadd
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0x60, // iadd
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@ -562,7 +580,7 @@ void jazelle_main(void) {
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uint32_t aid = arm_get_id();
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uint32_t jid = jazelle_get_id();
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iprintf("hello world! ARM coreID=0x%lx jazelle ID=0x%lx\r\n", aid, jid);
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while (jid == 0) ;
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if (jid == 0) return;
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int r = jazelle_exec(bytecode_test1);
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iprintf("retcode=%d; r5 was 0x%08lx\r\n", r, backup_r5);
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19
rpi/Makefile
19
rpi/Makefile
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@ -5,8 +5,8 @@ OPENOCD_PORT_TELNET ?= 4444
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PREFIX ?= arm-none-eabi-
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CC = $(PREFIX)gcc
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CFLAGS = -mcpu=arm1176jzf-s -Wall
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LDFLAGS = -T rpi.ld -nostartfiles -nostdlib
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CFLAGS = -mcpu=arm1176jzf-s -Wall -O2
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LDFLAGS = -T rpi.ld -nostartfiles -Wl,-Map=rpi.map -Wl,--cref
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GDB ?= $(PREFIX)gdb
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PYTHON3 ?= python3
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NC ?= nc
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@ -16,13 +16,13 @@ LNXCC = $(LNXPREFIX)gcc
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default: all
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all: rpi.elf
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all: rpi.elf rpi.img
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rpi.o: rpi.c
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$(CC) $(CFLAGS) -c -o "$@" "$<"
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rpi.elf: rpi.o
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$(CC) $(CFLAGS) $(LDFLAGS) -o "$@" $^
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vectors.o: vectors.s
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$(CC) -mcpu=arm1176jzf-s -c -o "$@" "$<"
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#jazelle.S: ../jazelle.c
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# $(CC) $(CFLAGS) -S -o "$@" "$<"
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@ -30,6 +30,15 @@ rpi.elf: rpi.o
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jazelle.o: ../jazelle.c
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$(CC) $(CFLAGS) -c -o "$@" "$<"
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nl-glue.o: nl-glue.c
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$(CC) $(CFLAGS) -c -o "$@" "$<"
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rpi.elf: rpi.o vectors.o nl-glue.o jazelle.o
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$(CC) $(CFLAGS) $(LDFLAGS) -o "$@" $^
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rpi.img: rpi.elf
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$(PREFIX)objcopy -O binary "$<" "$@"
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jazlinux: linux.c ../jazelle.c
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$(LNXCC) $(CLFAGS) -o "$@" $^
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@ -0,0 +1,98 @@
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/* glue code for Newlib */
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#include <sys/types.h>
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#include <sys/stat.h>
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void uart_putc(char c);
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void uart_puts(const char* s);
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void uart_putdata(const uint8_t* p, size_t size);
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/* Newlib's assert() calls this function if the assertion fails */
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void __assert_func (const char *file, int line, const char *func, const char *failedexpr)
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{
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if (file != NULL) {
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char linestrbuf[16], *linestr = &linestrbuf[sizeof(linestrbuf)];
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uart_puts(file);
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uart_putc(':');
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/* Avoid using newlib functions like itoa so as not to trigger
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a recursive assert... */
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*--linestr = '\0';
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while (line >= 10 && linestr != &linestrbuf[1]) {
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*--linestr = '0' + (line % 10);
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line /= 10;
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}
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*--linestr = '0' + line;
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uart_puts(linestr);
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uart_puts(": ");
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}
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if (func != NULL) {
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uart_puts(func);
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uart_puts(": ");
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}
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uart_puts("Assertion ");
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if (failedexpr != NULL) {
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uart_putc('`');
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uart_puts(failedexpr);
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uart_puts("' ");
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}
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uart_puts("failed.\n");
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//Fx3UartTxFlush();
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for(;;) ;
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}
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int _write(int fd, char* data, int size) {
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if (fd >= 0 && fd < 3) {
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if (size > 0)
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uart_putdata((const uint8_t*)data, (size_t)size);
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//Fx3UartTxFlush();
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return size;
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}
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return -1;
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}
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int _close(int fd) { (void)fd; return 0; }
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int _stat(char *file, struct stat *st) {
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(void)file;
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st->st_mode = S_IFCHR;
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return 0;
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}
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int _read(int fd, char *ptr, int len) { (void)fd; (void)ptr; (void)len; return 0; }
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int _lseek(int fd, int ptr, int dir) { (void)fd; (void)ptr; (void)dir; return 0; }
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int _isatty(int fd) { (void)fd; return 1; }
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int _fstat(int fd, struct stat *st) {
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(void)fd;
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st->st_mode = S_IFCHR;
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return 0;
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}
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#define HEAPSIZE (256*1024*1024)
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extern uint8_t _heap[];
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caddr_t _sbrk_r(int incr) {
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static uint8_t* heap_end = 0;
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uint8_t* prev_heap_end;
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/* initialize */
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if (heap_end == 0)
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heap_end = _heap;
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prev_heap_end = heap_end;
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if (heap_end + incr - _heap > HEAPSIZE) {
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/* heap overflow - announce on stderr */
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_write (2, "Heap overflow!\r\n", 16);
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for (;;) asm volatile("nop");
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}
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heap_end += incr;
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return (caddr_t)prev_heap_end;
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}
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288
rpi/rpi.c
288
rpi/rpi.c
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@ -5,245 +5,71 @@
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#include <stdio.h>
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#include <string.h>
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// known ID table:
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// Chip name | ARM core | ARM CPUID | JTAG IDCODE | Jazelle ID
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// ------------+------------+------------+-------------+----------- Jazelle DBX:
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// ??? | ARM7EJ-S | ??? | ??? | ???
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// Cypress FX3 | ARM926EJ-S | 0x41069265 | 0x07926069 | 0x64100004
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// TI Nspire | ARM926EJ-S?| 0x41069265?| ??? | 0x64100004?
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// RPi v1.?? | ARM11??? | ??? | ??? | ???
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// Ninty ?3DS | ARM11MPCore| 0x410FB025?| ??? | 0x74100064?
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// Xilinx Zynq7| Cortex-A9MP| 0x413FC090 | 0x4BA00477 | 0xF4100168
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// ------------+------------+------------+-------------+----------- Jazelle RCT:
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// Xilinx Zynq7| Cortex-A9MP| 0x413FC090 | 0x4BA00477 | 0xF4100168
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// TODO: others (BeagleBoard Cortex-A8? Other A9s?)
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//-------------------------------------------------------------------------
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//-------------------------------------------------------------------------
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// TODO: immediate next steps:
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// * check if we can override jazelle insn execution with custom handlers
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// * check what the control registers actually do
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// * enumerate what all insns do
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extern void jazelle_main(void);
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__attribute__((__naked__))
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static uint32_t arm_get_id(void) {
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asm volatile(
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"mrc p15, 0, r0, c0, c0, 0\n"
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"bkpt #4\n"
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"bx lr\n"
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);
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#define GPFSEL1 (*(volatile uint32_t*)0x20200004)
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#define GPSET0 (*(volatile uint32_t*)0x2020001C)
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#define GPCLR0 (*(volatile uint32_t*)0x20200028)
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#define GPPUD (*(volatile uint32_t*)0x20200094)
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#define GPPUDCLK0 (*(volatile uint32_t*)0x20200098)
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#define AUX_ENABLES (*(volatile uint32_t*)0x20215004)
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#define AUX_MU_IO_REG (*(volatile uint32_t*)0x20215040)
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#define AUX_MU_IER_REG (*(volatile uint32_t*)0x20215044)
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#define AUX_MU_IIR_REG (*(volatile uint32_t*)0x20215048)
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#define AUX_MU_LCR_REG (*(volatile uint32_t*)0x2021504C)
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#define AUX_MU_MCR_REG (*(volatile uint32_t*)0x20215050)
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#define AUX_MU_LSR_REG (*(volatile uint32_t*)0x20215054)
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#define AUX_MU_MSR_REG (*(volatile uint32_t*)0x20215058)
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#define AUX_MU_SCRATCH (*(volatile uint32_t*)0x2021505C)
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#define AUX_MU_CNTL_REG (*(volatile uint32_t*)0x20215060)
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#define AUX_MU_STAT_REG (*(volatile uint32_t*)0x20215064)
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#define AUX_MU_BAUD_REG (*(volatile uint32_t*)0x20215068)
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void uart_putc(char c) {
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while (!(AUX_MU_LSR_REG & 0x20)) asm volatile("nop");
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AUX_MU_IO_REG = c;
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}
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void uart_puts(const char* s) {
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for (; s && *s; ++s) {
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uart_putc(*s);
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}
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}
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void uart_putdata(const uint8_t* p, size_t size) {
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for (size_t i = 0; i < size; ++i) {
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uart_putc((char)p[i]);
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}
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}
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__attribute__((__naked__))
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static uint32_t jazelle_get_id(void) {
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asm volatile(
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"mrc p14, 7, r0, c0, c0, 0\n"
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"bkpt #5\n"
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"bx lr\n"
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);
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}
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int main() {
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AUX_ENABLES=1;
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AUX_MU_IER_REG=0;
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AUX_MU_CNTL_REG=0;
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AUX_MU_LCR_REG=3;
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AUX_MU_MCR_REG=0;
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AUX_MU_IER_REG=0;
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AUX_MU_IIR_REG=0xC6;
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AUX_MU_BAUD_REG=270;
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__attribute__((__aligned__(1024)))
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static struct {
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void* handlers[512];
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uint8_t stack[256];
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uint8_t locals[256];
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} jazelle_block;
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uint32_t ra = GPFSEL1;
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ra&=~(7<<12); //gpio14
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ra|=2<<12; //alt5
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GPFSEL1=ra;
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/*
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* c0: Jazelle Identity register (read-only)
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Bits 0-11: Subarchitecture-defined bits (reads as 4, meaning unknown)
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Bits 12-19: Subarchitecture (reads as 0, Jazelle V1 according to documentation)
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Bits 20-27: Implementor (reads as 0x41, ARM Limited according to documentation)
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Bits 28-31: Architecture (reads as 6, ARMv5TEJ according to documentation)
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c1: Operating System Control register
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Bit 0: Configuration Disabled (CD) (documented)
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Bit 1: Configuration Valid (CV) (documented)
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c2: Main Configuration register
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Bit 0: Jazelle Enable (JE) (documented)
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Bits 26-28: Unknown
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Bit 29: If set, array object contains its elements directly, otherwise it contains a pointer to its elements
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Bit 31: Disable array instructions if set?
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c3: Array object layout register
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Bits 0-7: Unknown
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Bits 8-11: Offset (in words) within array object of first element or of pointer to first element
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Bits 12-15: Offset (in words) within array object of length
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Bit 16: If set, offset to length is subtracted, otherwise added
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Bits 17-19: Array length shift value (number of elements = stored length >> this)
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Bits 20-21: Disable array instructions if set?
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*/
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GPPUD=0;
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for (int ra=0;ra<150;ra++) asm volatile("nop");
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GPPUDCLK0=(1<<14);
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for (int ra=0;ra<150;ra++) asm volatile("nop");
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GPPUDCLK0=0;
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static uint32_t jazelle_exit_save;
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AUX_MU_CNTL_REG=2;
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//uart_putc('A');
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__attribute__((__naked__))
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static int jazelle_exec_native(const void* bytecode, const void* block) {
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// inline asm parameters seems to be borking in GCC sooooo lets do it this way
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(void)bytecode; (void)block; (void)&jazelle_exit_save;
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asm volatile(
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"push {r4-r12,lr}\n"
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"mov lr, r0\n"
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// init handler table pointer and stack pointer
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"mov r5, r1\n"
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"add r6, r5, #0x800\n"
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"add r7, r5, #0x900\n"
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// "r8: Pointer to constant pool? (haven't checked this yet)" -Hackspire
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// set configuration valid & jazelle enable bits
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"mov r0, #2\n"
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"mcr p14, 7, r0, c1, c0, 0\n"
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"mov r0, #1\n"
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"mcr p14, 7, r0, c2, c0, 0\n"
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// apparently there's no good way to find the exit point from jazelle,
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// so we're going to hack that into the stuff now
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"ldr r12, =jazelle_exit_save\n"
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||||
"adr r0, .Ljazend\n"
|
||||
"str r0, [r12]\n"
|
||||
|
||||
// switch to jazelle mode
|
||||
"adr r12, .Lno_jazelle\n"
|
||||
"bxj r12\n"
|
||||
|
||||
".Ljazend:\n"
|
||||
"mov r0, #0\n"
|
||||
"b .Lend\n"
|
||||
|
||||
".Lno_jazelle:\n"
|
||||
"bkpt #1\n"
|
||||
"mov r0, #1\n"
|
||||
|
||||
".Lend:\n"
|
||||
"mov r5, #0\n"
|
||||
"mcr p14, 7, %r5, c1, c0, 0\n"
|
||||
"mcr p14, 7, %r5, c2, c0, 0\n"
|
||||
|
||||
"pop {r4-r12,lr}\n"
|
||||
"bx lr\n"
|
||||
|
||||
".pool\n"
|
||||
);
|
||||
}
|
||||
|
||||
|
||||
|
||||
__attribute__((__naked__))
|
||||
static void handler_idiv(void) {
|
||||
// r0 = 3
|
||||
// r1 = 4
|
||||
// r2 = 2
|
||||
// editing the above has no effect
|
||||
// NOTE: these depend on the stack content, i.e. it's not a moving register
|
||||
// window. pushes happen in the following order: r0,r1,r2,r3
|
||||
// TODO: when the 'register stack cache' is full, what happens? does
|
||||
// it loop or does it act in a FIFO way, moving r0<-r1<-r2<-r3?
|
||||
// how can the fillrate be known??? (libjz says r5 & 3 but i
|
||||
// dont see anything like that, maybe its an ARM11 thing?)
|
||||
// "r4: Copy of local variable 0. Only valid when local variable 0 is a
|
||||
// single word (i.e. int, float, or Object; not long or double)"
|
||||
// -Hackspire
|
||||
//
|
||||
// [r6-4] is stack top (2)
|
||||
// [r6-8] is 4
|
||||
// etc
|
||||
// use the above to manipulate the stack, eg. "iadd" is implemented as:
|
||||
// - add r1, r2 // or equivalently, read from stack i guess
|
||||
// - str r1, [r6, #-8] // store to the place where it will be read
|
||||
// - sub r6, #4 // pop off & discard stack top element
|
||||
// NOTE: this input usage (with r1 and r2) is NOT robust at all, use memory
|
||||
// reads instead!
|
||||
|
||||
asm volatile(
|
||||
"bkpt #3\n"
|
||||
// FIXME: read out stack contents in a better way
|
||||
"add r1, r2\n"
|
||||
"str r1, [r6,#-8]\n"
|
||||
"sub r6, #4\n"
|
||||
|
||||
// return to jazelle (yes lr has to be incremented otherwise the
|
||||
// current instruction keeps getting executed in a loop)
|
||||
"add lr, #1\n"
|
||||
"bxj r12\n" // FIXME: r12 can be modified by jazelle so it should be restored to something
|
||||
);
|
||||
}
|
||||
|
||||
__attribute__((__naked__))
|
||||
static void handler_ireturn(void) {
|
||||
int result;
|
||||
asm volatile(
|
||||
"bkpt #2\n"
|
||||
"ldr %[res], [r6, #-4]!\n"
|
||||
:[res]"=r"(result)
|
||||
);
|
||||
//iprintf("result=%d\r\n", result); // FIXME: save & restore r0-r3 if ret implemented properly
|
||||
|
||||
// get back to original code
|
||||
// TODO: later stage: get back to previous bytecode stuff
|
||||
asm volatile(
|
||||
"ldr r12, %[exsav]\n"
|
||||
"bx r12\n"
|
||||
:
|
||||
:[exsav]"m"(jazelle_exit_save)
|
||||
:"r12"
|
||||
);
|
||||
__builtin_unreachable();
|
||||
}
|
||||
|
||||
static int jazelle_exec(const uint8_t* bytecode) {
|
||||
jazelle_block.handlers[0x6C] = handler_idiv;
|
||||
jazelle_block.handlers[0xAC] = handler_ireturn;
|
||||
/*
|
||||
* +000-3FF: Unhandled bytecodes
|
||||
The stack is flushed to memory before calling any of these handlers, so they may modify r0-r3 freely
|
||||
+400: Null pointer exception
|
||||
+404: Array index out of bounds exception
|
||||
+40C: Jazelle mode entered with JE = 0
|
||||
+410: Configuration invalid (Jazelle mode entered with CV = 0)
|
||||
CV is automatically set to 1 on entering this handler
|
||||
+414: Prefetch abort occurred in middle of instruction
|
||||
-Hackspire
|
||||
*/
|
||||
const void* block = &jazelle_block;
|
||||
|
||||
return jazelle_exec_native(bytecode, block);
|
||||
}
|
||||
|
||||
|
||||
// https://github.com/SonoSooS/libjz/wiki/Java-instruction-set
|
||||
static uint8_t bytecode_test1[] = {
|
||||
0x06, // iconst_3
|
||||
0x07, // iconst_4
|
||||
0x05, // iconst_2
|
||||
0x6C, // idiv
|
||||
0x04, // iconst_1
|
||||
0x60, // iadd
|
||||
0x60, // iadd
|
||||
0xAC, // ireturn
|
||||
};
|
||||
|
||||
void jazelle_main(void) {
|
||||
uint32_t aid = arm_get_id();
|
||||
uint32_t jid = jazelle_get_id();
|
||||
asm volatile("bkpt #0\n");
|
||||
//iprintf("hello world! ARM coreID=0x%lx jazelle ID=0x%lx\r\n", aid, jid);
|
||||
while (jid == 0) ;
|
||||
|
||||
int r = jazelle_exec(bytecode_test1);
|
||||
//iprintf("retcode=%d\r\n", r);
|
||||
|
||||
while (true) ;
|
||||
}
|
||||
|
||||
void main(void) {
|
||||
jazelle_main();
|
||||
}
|
||||
|
||||
__attribute__((__naked__, __section__(".entry")))
|
||||
void _start(void) {
|
||||
asm volatile(
|
||||
"ldr sp, =0x00010000\n"
|
||||
"bl main\n"
|
||||
"1: b 1b\n"
|
||||
".pool\n"
|
||||
);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
25
rpi/rpi.ld
25
rpi/rpi.ld
|
|
@ -1,35 +1,44 @@
|
|||
|
||||
ENTRY(_start)
|
||||
|
||||
MEMORY
|
||||
{
|
||||
ram : ORIGIN = 0x8000, LENGTH = 0x80000
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x00001000;
|
||||
/*. = 0x00001000;*/
|
||||
|
||||
.text :
|
||||
{
|
||||
*(.entry*)
|
||||
*(.text*)
|
||||
*(.rodata*)
|
||||
}
|
||||
} > ram
|
||||
.data :
|
||||
{
|
||||
*(.data*)
|
||||
}
|
||||
} > ram
|
||||
|
||||
.ARM.extab :
|
||||
/*.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
}
|
||||
} > ram
|
||||
__exidx_start = .;
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
}
|
||||
__exidx_end = .;
|
||||
} > ram
|
||||
__exidx_end = .;*/
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.bss*)
|
||||
}
|
||||
} > ram
|
||||
__bss_end = .;
|
||||
|
||||
_heap = .;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,113 @@
|
|||
@ vim: set ft=armv5:
|
||||
|
||||
.section ".entry", "awx", %progbits
|
||||
.global VECTORS
|
||||
VECTORS:
|
||||
ldr pc, reset_handler
|
||||
ldr pc, undefined_handler
|
||||
ldr pc, swi_handler
|
||||
ldr pc, prefetch_handler
|
||||
ldr pc, data_handler
|
||||
ldr pc, unused_handler
|
||||
ldr pc, irq_handler
|
||||
ldr pc, fiq_handler
|
||||
|
||||
reset_handler:
|
||||
.4byte _start
|
||||
undefined_handler:
|
||||
.4byte hang
|
||||
swi_handler:
|
||||
.4byte hang
|
||||
prefetch_handler:
|
||||
.4byte hang
|
||||
data_handler:
|
||||
.4byte hang
|
||||
unused_handler:
|
||||
.4byte hang
|
||||
irq_handler:
|
||||
.4byte hang
|
||||
fiq_handler:
|
||||
.4byte hang
|
||||
|
||||
|
||||
.global _start
|
||||
_start:
|
||||
@ copy over exception vectors
|
||||
mov r0, #0x8000
|
||||
mov r1, #0
|
||||
ldmia r0!, {r2-r9}
|
||||
stmia r1!, {r2-r9}
|
||||
ldmia r0!, {r2-r9}
|
||||
stmia r1!, {r2-r9}
|
||||
|
||||
@ IRQ mode
|
||||
mov r0, #0xd2
|
||||
msr cpsr_c, r0
|
||||
mov sp, #0x8000
|
||||
@ FIQ mode
|
||||
mov r0, #0xd1
|
||||
msr cpsr_c, r0
|
||||
mov sp, #0x4000
|
||||
@ SVC mode
|
||||
mov r0, #0xd3
|
||||
msr cpsr_c, r0
|
||||
mov sp, #0x08000000
|
||||
|
||||
mov r0, #0
|
||||
mcr p15, 0, r0, c3, c0, 0 @ disable write buffer
|
||||
mcr p15, 0, r0, c2, c0, 0 @ disable icache & dcache
|
||||
mcr p15, 0, r0, c2, c0, 1
|
||||
|
||||
@ disable stuff
|
||||
mrc p15, 0, r0, c1, c0, 0
|
||||
ldr r1, =((1<<12)|(1<<2)|(1<<0)) @ icache/dcache/mpu enable bits
|
||||
bic r0, r1
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
|
||||
@ clear bss
|
||||
ldr r0, =__bss_start
|
||||
ldr r1, =__bss_end
|
||||
mov r2, #0
|
||||
mov r3, #0
|
||||
zeroloop:
|
||||
strd r2, r3, [r0], #8
|
||||
cmp r0, r1
|
||||
bne zeroloop
|
||||
|
||||
bl main
|
||||
|
||||
@ fallthru
|
||||
hang:
|
||||
b hang
|
||||
|
||||
.pool
|
||||
|
||||
/*.section ".text.utils", "ax", %progbits
|
||||
|
||||
.global PUT32
|
||||
PUT32:
|
||||
str r1,[r0]
|
||||
bx lr
|
||||
|
||||
.global GET32
|
||||
GET32:
|
||||
ldr r0,[r0]
|
||||
;@ bx lr
|
||||
|
||||
.global dummy
|
||||
dummy:
|
||||
bx lr*/
|
||||
|
||||
|
||||
|
||||
;@-------------------------------------------------------------------------
|
||||
;@
|
||||
;@ Copyright (c) 2012 David Welch dwelch@dwelch.com
|
||||
;@
|
||||
;@ Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
|
||||
;@
|
||||
;@ The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
;@
|
||||
;@ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
;@
|
||||
;@-------------------------------------------------------------------------
|
||||
Loading…
Reference in New Issue