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stuff

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Triss 2022-01-21 05:15:36 +01:00
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*.o
*.d
*.img
*.elf
*.map

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CC = arm-none-eabi-gcc
CGENFLAGS = -mcpu=arm926ej-s -mthumb-interwork -fno-pie
WARN = -Wall -Wextra -Werror
OPTIMIZE = -g -Og
INCLUDE = -I.
GENDEP = -MMD -MP
DEFS = -DPLL_FBDIV=20
CFLAGS = -std=gnu17 $(CGENFLAGS) $(WARN) $(OPTIMIZE) $(INCLUDE) $(GENDEP) $(DEFS)
LDFLAGS = -static -nostartfiles -T bsp/fx3.ld -Wl,-z,max-page-size=4096,-Map,$(basename $@).map
VPATH = bsp
OBJS = main.o usb.o gpif.o gctl.o gpio.o uart.o util.o dma.o irq.o cache.o vectors.o
all : jazelle.img
jazelle.img: jazelle.elf
python3 elf2img.py $< $@
clean :
rm -f jazelle.img jazelle.elf jazelle.map $(OBJS) $(OBJS:.o=.d)
jazelle.elf : $(OBJS)
$(CC) $(CFLAGS) $(LDFLAGS) -o $@ $^
-include $(OBJS:.o=.d)

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# Jacking (Jazelle hacking (Jean gazelle hacking))
**Jazelle reverse engineering effort**
not the first one, but hopefully one that properly documents some stuff
## Workflow
Currently targetting the Cypress FX3.
### Compiling
```
$ make
```
Needs an `arm-none-eabi` toolchain.
### Running/debugging
#### Setup
```
$ openocd -f ./arm926ejs_fx3.cfg -c "transport select jtag" -c "adapter speed 1000" -c "init"
```
#### Running code
```
$ printf 'reset halt\nload_image jazelle.elf\nexit\n' | nc localhost 4444
gdb -ex 'target extended-remote localhost:3333' -ex 'set $pc=_start' -ex 'b jazelle_exec' -ex c jazelle.elf
```
## Credits
FX3 base code: gratuitously stolen from https://github.com/zeldin/fx3lafw/
Jazelle info this project is based on:
* https://hackspire.org/index.php/Jazelle
* https://github.com/SonoSooS/libjz

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#
# OpenOCD configuration file for Cypress FX3 (ARM926EJ-S).
#
# FX3 has a standard ARM JTAG TAP and can work with a standard ARM926EJ-S configuration.
#
# The interface selected below is the CY7C65215 based JTAG debug probe. If another
# debug probe is being used, just replace the "interface cy7c65215" line with the
# appropriate interface name.
#
gdb_port 3333
adapter driver openjtag
openjtag_variant cy7c65215
######################################
# Target: CYPRESS FX3 ARM926EJ-S
######################################
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME fx3
}
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
set _ENDIAN little
}
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x07926069
}
#delays on reset lines
adapter srst delay 200
jtag_ntrst_delay 200
adapter speed 1000
reset_config trst_and_srst srst_pulls_trst
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
jtag_rclk 3
######################
# Target configuration
######################
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
#-variant arm926ejs
#adapter speed 1000

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/*
* Copyright (C) 2018 Marcus Comstedt
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include <bsp/cache.h>
void Fx3CacheEnableCaches(void)
{
Fx3CacheInvalidateICacheAndDCache();
/* Set I and C bit in Control register */
uint32_t creg;
__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 0" : "=r"(creg));
creg |= (1UL << 12) | (1UL << 2);
__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 0" : : "r"(creg));
}

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/*
* Copyright (C) 2018 Marcus Comstedt
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef BSP_CACHE_H_
#define BSP_CACHE_H_
#include <stdint.h>
static inline void Fx3CacheInvalidateICacheAndDCache(void)
{
__asm__ __volatile__("mcr p15, 0, %0, c7, c7, 0" : : "r"(0));
}
static inline void Fx3CacheInvalidateICache(void)
{
__asm__ __volatile__("mcr p15, 0, %0, c7, c5, 0" : : "r"(0));
}
static inline void Fx3CacheCleanDCache(void)
{
__asm__ __volatile__("1: mrc p15, 0, r15, c7, c10, 3; bne 1b" ::: "cc");
}
static inline void Fx3CacheCleanDCacheEntry(volatile void *ptr)
{
__asm__ __volatile__("mcr p15, 0, %0, c7, c10, 1" : : "r"(((uint32_t)ptr) & ~0x1FUL));
}
static inline void Fx3CacheInvalidateDCacheEntry(volatile void *ptr)
{
__asm__ __volatile__("mcr p15, 0, %0, c7, c6, 1" : : "r"(((uint32_t)ptr) & ~0x1FUL));
}
extern void Fx3CacheEnableCaches(void);
#endif /* BSP_CACHE_H_ */

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/*
* Copyright (C) 2018 Marcus Comstedt
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include <bsp/dma.h>
#include <bsp/regaccess.h>
#include <bsp/cache.h>
#include <bsp/uart.h>
#include <rdb/dma.h>
#define FX3_SCK_STATUS_DEFAULT \
( FX3_SCK_STATUS_SUSP_TRANS | \
FX3_SCK_STATUS_EN_CONS_EVENTS | \
FX3_SCK_STATUS_EN_PROD_EVENTS | \
FX3_SCK_STATUS_TRUNCATE )
static uint16_t Fx3DmaDescriptorFirstUnallocated = 1;
static uint16_t Fx3DmaDescriptorFreeListHead = 0;
uint16_t Fx3DmaAllocateDescriptor(void)
{
uint16_t r;
if ((r = Fx3DmaDescriptorFreeListHead)) {
/* Pick first off free list */
volatile struct Fx3DmaDescriptor *desc = FX3_DMA_DESCRIPTOR(r);
Fx3DmaDescriptorFreeListHead = desc->dscr_chain;
} else if(Fx3DmaDescriptorFirstUnallocated < 768) {
/* Allocate a fresh one */
r = Fx3DmaDescriptorFirstUnallocated++;
}
return r;
}
void Fx3DmaFreeDescriptor(uint16_t d)
{
if (d) {
/* Put on head of free list */
volatile struct Fx3DmaDescriptor *desc = FX3_DMA_DESCRIPTOR(d);
desc->dscr_chain = Fx3DmaDescriptorFreeListHead;
Fx3DmaDescriptorFreeListHead = d;
}
}
void Fx3DmaAbortSocket(uint32_t socket)
{
Fx3ClearReg32(socket + FX3_SCK_STATUS,
FX3_SCK_STATUS_GO_ENABLE |
FX3_SCK_STATUS_WRAPUP);
Fx3WriteReg32(socket + FX3_SCK_INTR, ~0);
while((Fx3ReadReg32(socket + FX3_SCK_STATUS) & FX3_SCK_STATUS_ENABLED))
;
}
static void Fx3DmaFillDescriptor(uint16_t descriptor, uint32_t buffer,
uint32_t sync, uint32_t size,
uint16_t wrchain, uint16_t rdchain)
{
volatile struct Fx3DmaDescriptor *desc = FX3_DMA_DESCRIPTOR(descriptor);
if (!(size & FX3_DSCR_SIZE_BUFFER_SIZE_MASK))
size |= 1UL << FX3_DSCR_SIZE_BUFFER_SIZE_SHIFT;
desc->dscr_buffer = buffer;
desc->dscr_sync = sync;
desc->dscr_size = size;
desc->dscr_chain =
(wrchain << FX3_DSCR_CHAIN_WR_NEXT_DSCR_SHIFT) |
(rdchain << FX3_DSCR_CHAIN_RD_NEXT_DSCR_SHIFT);
Fx3CacheCleanDCacheEntry(desc);
}
static void Fx3DmaTransferStart(uint32_t socket, uint16_t descriptor,
uint32_t status, uint32_t size, uint32_t count)
{
Fx3WriteReg32(socket + FX3_SCK_STATUS, FX3_SCK_STATUS_DEFAULT);
while((Fx3ReadReg32(socket + FX3_SCK_STATUS) & FX3_SCK_STATUS_ENABLED))
;
Fx3WriteReg32(socket + FX3_SCK_STATUS, status);
Fx3WriteReg32(socket + FX3_SCK_INTR, ~0UL);
Fx3WriteReg32(socket + FX3_SCK_DSCR,
(0UL << FX3_SCK_DSCR_DSCR_LOW_SHIFT) |
(0UL << FX3_SCK_DSCR_DSCR_COUNT_SHIFT) |
(descriptor << FX3_SCK_DSCR_DSCR_NUMBER_SHIFT));
Fx3WriteReg32(socket + FX3_SCK_SIZE, size);
Fx3WriteReg32(socket + FX3_SCK_COUNT, count);
Fx3SetReg32(socket + FX3_SCK_STATUS,
FX3_SCK_STATUS_GO_ENABLE);
}
static void Fx3DmaWaitForEvent(uint32_t socket, uint32_t event)
{
for(;;) {
uint32_t status = Fx3ReadReg32(socket + FX3_SCK_INTR);
if (status & FX3_SCK_INTR_ERROR) {
Fx3UartTxString("DMA error\n");
return;
}
if (status & event)
return;
/* timeout? */
}
}
void Fx3DmaFillDescriptorThrough(uint32_t prod_socket, uint32_t cons_socket,
uint16_t descriptor, volatile void *buffer,
uint16_t length, uint16_t wrchain, uint16_t rdchain)
{
Fx3DmaFillDescriptor(descriptor, (uint32_t)buffer,
FX3_DSCR_SYNC_EN_PROD_INT |
FX3_DSCR_SYNC_EN_PROD_EVENT |
(FX3_DMA_SOCKET_IP(prod_socket) << FX3_DSCR_SYNC_PROD_IP_SHIFT) |
(FX3_DMA_SOCKET_SCK(prod_socket) << FX3_DSCR_SYNC_PROD_SCK_SHIFT) |
FX3_DSCR_SYNC_EN_CONS_INT |
FX3_DSCR_SYNC_EN_CONS_EVENT |
(FX3_DMA_SOCKET_IP(cons_socket) << FX3_DSCR_SYNC_CONS_IP_SHIFT) |
(FX3_DMA_SOCKET_SCK(cons_socket) << FX3_DSCR_SYNC_CONS_SCK_SHIFT),
(length + 15) & FX3_DSCR_SIZE_BUFFER_SIZE_MASK,
wrchain, rdchain);
}
void Fx3DmaFillDescriptorRead(uint32_t socket, uint16_t descriptor,
const volatile void *buffer, uint16_t length,
uint16_t chain)
{
Fx3DmaFillDescriptor(descriptor, (uint32_t)buffer,
FX3_DSCR_SYNC_EN_PROD_INT |
FX3_DSCR_SYNC_EN_PROD_EVENT |
(0x3FUL << FX3_DSCR_SYNC_PROD_IP_SHIFT) |
FX3_DSCR_SYNC_EN_CONS_INT |
FX3_DSCR_SYNC_EN_CONS_EVENT |
(FX3_DMA_SOCKET_IP(socket) << FX3_DSCR_SYNC_CONS_IP_SHIFT) |
(FX3_DMA_SOCKET_SCK(socket) << FX3_DSCR_SYNC_CONS_SCK_SHIFT),
(length << FX3_DSCR_SIZE_BYTE_COUNT_SHIFT) |
((length + 15) & FX3_DSCR_SIZE_BUFFER_SIZE_MASK) |
FX3_DSCR_SIZE_BUFFER_OCCUPIED, chain, chain);
}
void Fx3DmaFillDescriptorWrite(uint32_t socket, uint16_t descriptor,
volatile void *buffer, uint16_t length,
uint16_t chain)
{
Fx3DmaFillDescriptor(descriptor, (uint32_t)buffer,
FX3_DSCR_SYNC_EN_PROD_INT |
FX3_DSCR_SYNC_EN_PROD_EVENT |
(FX3_DMA_SOCKET_IP(socket) << FX3_DSCR_SYNC_PROD_IP_SHIFT) |
(FX3_DMA_SOCKET_SCK(socket) << FX3_DSCR_SYNC_PROD_SCK_SHIFT) |
FX3_DSCR_SYNC_EN_CONS_INT |
FX3_DSCR_SYNC_EN_CONS_EVENT |
(0x3FUL << FX3_DSCR_SYNC_CONS_IP_SHIFT),
(length + 15) & FX3_DSCR_SIZE_BUFFER_SIZE_MASK, chain, chain);
}
void Fx3DmaSimpleTransferRead(uint32_t socket, uint16_t descriptor,
const volatile void *buffer, uint16_t length)
{
Fx3DmaFillDescriptorRead(socket, descriptor, buffer, length, 0xFFFFU);
Fx3DmaTransferStart(socket, descriptor,
FX3_SCK_STATUS_DEFAULT | FX3_SCK_STATUS_UNIT, 1, 0);
Fx3DmaWaitForEvent(socket, FX3_SCK_INTR_CONSUME_EVENT);
}
void Fx3DmaSimpleTransferWrite(uint32_t socket, uint16_t descriptor,
volatile void *buffer, uint16_t length)
{
Fx3DmaFillDescriptorWrite(socket, descriptor, buffer, length, 0xFFFFU);
Fx3DmaTransferStart(socket, descriptor,
FX3_SCK_STATUS_DEFAULT | FX3_SCK_STATUS_UNIT, 1, 0);
Fx3DmaWaitForEvent(socket, FX3_SCK_INTR_PRODUCE_EVENT);
}
void Fx3DmaStartProducer(uint32_t socket, uint16_t descriptor,
uint32_t size, uint32_t count)
{
Fx3DmaTransferStart(socket, descriptor,
FX3_SCK_STATUS_SUSP_TRANS |
FX3_SCK_STATUS_EN_PROD_EVENTS |
FX3_SCK_STATUS_TRUNCATE,
size, count);
}
void Fx3DmaStartConsumer(uint32_t socket, uint16_t descriptor,
uint32_t size, uint32_t count)
{
Fx3DmaTransferStart(socket, descriptor,
FX3_SCK_STATUS_SUSP_TRANS |
FX3_SCK_STATUS_EN_CONS_EVENTS |
FX3_SCK_STATUS_TRUNCATE,
size, count);
}

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/*
* Copyright (C) 2018 Marcus Comstedt
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef BSP_DMA_H_
#define BSP_DMA_H_
#include <stdint.h>
#define FX3_LPP_DMA_SCK(n) (0xE0008000+((n)<<7))
#define FX3_PIB_DMA_SCK(n) (0xE0018000+((n)<<7))
#define FX3_UIB_DMA_SCK(n) (0xE0038000+((n)<<7))
#define FX3_UIBIN_DMA_SCK(n) (0xE0048000+((n)<<7))
#define FX3_DMA_SOCKET_IP(s) (((s) >> 16) & 0x3FUL)
#define FX3_DMA_SOCKET_SCK(s) (((s) >> 7) & 0xFFUL)
#define FX3_DMA_DESCRIPTOR(n) /* 1 <= n < 768 */ \
((volatile struct Fx3DmaDescriptor *)(void *)(0x40000000 + ((n) << 4)))
#define FX3_LPP_DMA_GLOBL 0xE000FF00
#define FX3_PIB_DMA_GLOBL 0xE001FF00
#define FX3_UIB_DMA_GLOBL 0xE003FF00
#define FX3_UIBIN_DMA_GLOBL 0xE004FF00
struct Fx3DmaDescriptor {
uint32_t dscr_buffer;
uint32_t dscr_sync;
uint32_t dscr_chain;
uint32_t dscr_size;
};
extern uint16_t Fx3DmaAllocateDescriptor(void);
extern void Fx3DmaFreeDescriptor(uint16_t d);
extern void Fx3DmaAbortSocket(uint32_t socket);
extern void Fx3DmaFillDescriptorThrough(uint32_t prod_socket, uint32_t cons_socket,
uint16_t descriptor, volatile void *buffer, uint16_t length,
uint16_t wrchain, uint16_t rdchain);
extern void Fx3DmaFillDescriptorRead(uint32_t socket, uint16_t descriptor,
const volatile void *buffer,
uint16_t length, uint16_t chain);
extern void Fx3DmaFillDescriptorWrite(uint32_t socket, uint16_t descriptor,
volatile void *buffer, uint16_t length,
uint16_t chain);
extern void Fx3DmaSimpleTransferRead(uint32_t socket, uint16_t descriptor,
const volatile void *buffer, uint16_t length);
extern void Fx3DmaSimpleTransferWrite(uint32_t socket, uint16_t descriptor,
volatile void *buffer, uint16_t length);
extern void Fx3DmaStartProducer(uint32_t socket, uint16_t descriptor,
uint32_t size, uint32_t count);
extern void Fx3DmaStartConsumer(uint32_t socket, uint16_t descriptor,
uint32_t size, uint32_t count);
#endif /* BSP_DMA_H_ */

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/*
* Copyright (C) 2018 Marcus Comstedt
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
ENTRY(_start)
SECTIONS
{
. = 0x40003000;
/* Stacks in DTCM */
__stack_sys = 0x10002000; /* 6KB */
__stack_undef = 0x10000800; /* 128B */
__stack_abort = 0x10000780; /* 128B */
__stack_firq = 0x10000700; /* 256B */
__stack_irq = 0x10000600; /* 1KB */
__stack_super = 0x10000200; /* 512B */
.text :
{
*(.init*)
*(.text*)
*(.fini*)
*(.rodata*)
*(.eh_frame*)
. = ALIGN(4);
}
.data :
{
*(.init_array*)
*(.fini_array*)
*(.got)
*(.data*)
. = ALIGN(4);
}
.bss :
{
__bss_start__ = .;
*(.bss*)
. = ALIGN(4);
__bss_end__ = .;
}
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
}
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
}
__exidx_end = .;
_end = .;
__heap_end = 0x40040000;
}

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/*
* Copyright (C) 2018 Marcus Comstedt
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include <bsp/gctl.h>
#include <bsp/regaccess.h>
#include <bsp/util.h>
#include <rdb/gctl.h>
void Fx3GctlInitClock(void)
{
/* Select minimum scalers for all clocks */
Fx3WriteReg32(FX3_GCTL_CPU_CLK_CFG,
(1UL << FX3_GCTL_CPU_CLK_CFG_MMIO_DIV_SHIFT) |
(1UL << FX3_GCTL_CPU_CLK_CFG_DMA_DIV_SHIFT) |
(3UL << FX3_GCTL_CPU_CLK_CFG_SRC_SHIFT) |
((CPU_DIV - 1UL) << FX3_GCTL_CPU_CLK_CFG_CPU_DIV_SHIFT));
Fx3UtilDelayUs(10);
/* Change PLL feedback divisor if needed */
if (Fx3GetField32(FX3_GCTL_PLL_CFG, FBDIV) != PLL_FBDIV) {
Fx3SetField32(FX3_GCTL_PLL_CFG, FBDIV, PLL_FBDIV);
Fx3UtilDelayUs(10);
while ((Fx3ReadReg32(FX3_GCTL_PLL_CFG) & FX3_GCTL_PLL_CFG_PLL_LOCK) == 0)
;
Fx3UtilDelayUs(10);
}
}
void Fx3GctlInitIoMatrix(Fx3GctlPinAltFunc_t alt_func)
{
/* Disable all GPIO overrides */
Fx3WriteReg32(FX3_GCTL_GPIO_SIMPLE, 0);
Fx3WriteReg32(FX3_GCTL_GPIO_SIMPLE+4, 0);
Fx3WriteReg32(FX3_GCTL_GPIO_COMPLEX, 0);
Fx3WriteReg32(FX3_GCTL_GPIO_COMPLEX+4, 0);
Fx3UtilDelayUs(1);
/* Configure matrix */
Fx3WriteReg32(FX3_GCTL_IOMATRIX,
(alt_func << FX3_GCTL_IOMATRIX_S1CFG_SHIFT) |
(alt_func == FX3_GCTL_ALTFUNC_GPIF32BIT_UART_I2S?
FX3_GCTL_IOMATRIX_S0CFG : 0));
}
void Fx3GctlHardReset(void)
{
Fx3UtilDelayUs(5);
Fx3ClearReg32(FX3_GCTL_CONTROL, FX3_GCTL_CONTROL_HARD_RESET_N);
Fx3UtilDelayUs(5);
}

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/*
* Copyright (C) 2018 Marcus Comstedt
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef BSP_GCTL_H_
#define BSP_GCTL_H_
#include <stdint.h>
#ifndef PLL_FBDIV
#define PLL_FBDIV 21 /* -> SYS_CLK = 403200000 */
#endif
#define SYS_CLK (19200000 * PLL_FBDIV)
#ifndef CPU_DIV
#define CPU_DIV 2
#endif
#define CPU_CLK (SYS_CLK / CPU_DIV)
/* Alternate function for GPIO 33-57 */
typedef enum {
FX3_GCTL_ALTFUNC_GPIO = 0,
FX3_GCTL_ALTFUNC_GPIO_UART = 1,
FX3_GCTL_ALTFUNC_GPIO_SPI = 2,
FX3_GCTL_ALTFUNC_GPIO_I2S = 3,
FX3_GCTL_ALTFUNC_UART_SPI_I2S = 4,
FX3_GCTL_ALTFUNC_GPIF32BIT_UART_I2S = 5
} Fx3GctlPinAltFunc_t;
extern void Fx3GctlInitClock(void);
extern void Fx3GctlInitIoMatrix(Fx3GctlPinAltFunc_t alt_func);
extern void Fx3GctlHardReset(void);
#endif /* BSP_GCTL_H_ */

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/*
* Copyright (C) 2018 Marcus Comstedt
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include <bsp/gpif.h>
#include <bsp/regaccess.h>
#include <bsp/irq.h>
#include <bsp/util.h>
#include <bsp/uart.h>
#include <rdb/gctl.h>
#include <rdb/pib.h>
#include <rdb/vic.h>
static void Fx3GpifPibIsr(void) __attribute__ ((isr ("IRQ")));
static void Fx3GpifPibIsr(void)
{
uint32_t req = Fx3ReadReg32(FX3_PIB_INTR) & Fx3ReadReg32(FX3_PIB_INTR_MASK);
Fx3WriteReg32(FX3_PIB_INTR, req);
Fx3UartTxString("Fx3GpifPibIsr\n");
if (req & FX3_PIB_INTR_GPIF_ERR) {
Fx3UartTxString(" GPIF ERROR\n");
/* Pause on error */
Fx3SetReg32(FX3_GPIF_WAVEFORM_CTRL_STAT, FX3_GPIF_WAVEFORM_CTRL_STAT_PAUSE);
}
if (req & FX3_PIB_INTR_GPIF_INTERRUPT) {
Fx3UartTxString(" GPIF\n");
uint32_t gpif_req = Fx3ReadReg32(FX3_GPIF_INTR) & Fx3ReadReg32(FX3_GPIF_INTR_MASK);
Fx3WriteReg32(FX3_GPIF_INTR, gpif_req);
if (gpif_req & FX3_GPIF_INTR_GPIF_INTR)
Fx3UartTxString(" INTR\n");
if (gpif_req & FX3_GPIF_INTR_GPIF_DONE)
Fx3UartTxString(" DONE\n");
}
Fx3WriteReg32(FX3_VIC_ADDRESS, 0);
}
void Fx3GpifStart(uint8_t state, uint8_t alpha)
{
Fx3WriteReg32(FX3_GPIF_INTR, Fx3ReadReg32(FX3_GPIF_INTR));
Fx3WriteReg32(FX3_GPIF_INTR_MASK,
FX3_GPIF_INTR_MASK_GPIF_INTR | FX3_GPIF_INTR_MASK_GPIF_DONE);
Fx3SetField32(FX3_GPIF_WAVEFORM_CTRL_STAT, ALPHA_INIT, alpha);
Fx3SetReg32(FX3_GPIF_WAVEFORM_CTRL_STAT,
FX3_GPIF_WAVEFORM_CTRL_STAT_WAVEFORM_VALID);
Fx3WriteReg32(FX3_GPIF_WAVEFORM_SWITCH,
(Fx3ReadReg32(FX3_GPIF_WAVEFORM_SWITCH) &
~(FX3_GPIF_WAVEFORM_SWITCH_DESTINATION_STATE_SHIFT |
FX3_GPIF_WAVEFORM_SWITCH_TERMINAL_STATE_MASK |
FX3_GPIF_WAVEFORM_SWITCH_SWITCH_NOW |
FX3_GPIF_WAVEFORM_SWITCH_WAVEFORM_SWITCH)) |
(state << FX3_GPIF_WAVEFORM_SWITCH_DESTINATION_STATE_SHIFT));
Fx3SetReg32(FX3_GPIF_WAVEFORM_SWITCH,
FX3_GPIF_WAVEFORM_SWITCH_SWITCH_NOW |
FX3_GPIF_WAVEFORM_SWITCH_WAVEFORM_SWITCH);
}
void Fx3GpifStop(void)
{
Fx3SetReg32(FX3_GPIF_WAVEFORM_CTRL_STAT, FX3_GPIF_WAVEFORM_CTRL_STAT_PAUSE);
Fx3UtilDelayUs(10);
Fx3WriteReg32(FX3_GPIF_WAVEFORM_CTRL_STAT, 0);
}
void Fx3GpifInvalidate(void)
{
unsigned i;
Fx3WriteReg32(FX3_GPIF_CONFIG, 0x220);
for (i=0; i<256; i++) {
Fx3WriteReg32(FX3_GPIF_LEFT_WAVEFORM + i*16 + 8, 0);
Fx3WriteReg32(FX3_GPIF_RIGHT_WAVEFORM + i*16 + 8, 0);
}
for (i=0; i<4; i++)
Fx3WriteReg32(FX3_GPIF_THREAD_CONFIG + i*4, 0);
}
static void Fx3GpifConfigureCommon(const uint16_t *functions,
uint16_t num_functions,
const uint32_t *registers,
uint16_t num_registers)
{
unsigned i;
if (functions && num_functions) {
if (num_functions > 32)
num_functions = 32;
for(i=0; i<num_functions; i++) {
Fx3WriteReg32(FX3_GPIF_FUNCTION + i*4, functions[i]);
}
}
if (registers && num_registers) {
for(i=num_registers; i--; )
Fx3WriteReg32(FX3_GPIF_CONFIG + i*4, registers[i]);
}
}
void Fx3GpifConfigure(const Fx3GpifWaveform_t *waveforms,
uint16_t num_waveforms,
const uint16_t *functions, uint16_t num_functions,
const Fx3GpifRegisters_t *registers)
{
unsigned i;
if (waveforms && num_waveforms) {
for(i=0; i<num_waveforms; i++) {
const Fx3GpifWaveform_t *left = &waveforms[waveforms[i].left];
const Fx3GpifWaveform_t *right = &waveforms[waveforms[i].right];
unsigned pos = waveforms[i].state[0] & FX3_GPIF_LEFT_WAVEFORM_NEXT_STATE_MASK;
Fx3WriteReg32(FX3_GPIF_LEFT_WAVEFORM + pos*16 + 0, left->state[0]);
Fx3WriteReg32(FX3_GPIF_LEFT_WAVEFORM + pos*16 + 4, left->state[1]);
Fx3WriteReg32(FX3_GPIF_LEFT_WAVEFORM + pos*16 + 8, left->state[2]);
Fx3WriteReg32(FX3_GPIF_RIGHT_WAVEFORM + pos*16 + 0, right->state[0]);
Fx3WriteReg32(FX3_GPIF_RIGHT_WAVEFORM + pos*16 + 4, right->state[1]);
Fx3WriteReg32(FX3_GPIF_RIGHT_WAVEFORM + pos*16 + 8, right->state[2]);
}
}
Fx3GpifConfigureCommon(functions, num_functions, &registers->config,
sizeof(*registers)/sizeof(uint32_t));
}
void Fx3GpifConfigureCompat(const Fx3GpifWaveformCompat_t *waveforms,
const uint8_t *waveform_select,
uint16_t num_waveforms,
const uint16_t *functions, uint16_t num_functions,
const uint32_t *registers, uint16_t num_registers)
{
unsigned i;
if (waveforms && num_waveforms) {
for(i=0; i<num_waveforms; i++) {
const Fx3GpifWaveformCompat_t *w =
&waveforms[waveform_select? waveform_select[i]:i];
Fx3WriteReg32(FX3_GPIF_LEFT_WAVEFORM + i*16 + 0, w->left[0]);
Fx3WriteReg32(FX3_GPIF_LEFT_WAVEFORM + i*16 + 4, w->left[1]);
Fx3WriteReg32(FX3_GPIF_LEFT_WAVEFORM + i*16 + 8, w->left[2]);
Fx3WriteReg32(FX3_GPIF_RIGHT_WAVEFORM + i*16 + 0, w->right[0]);
Fx3WriteReg32(FX3_GPIF_RIGHT_WAVEFORM + i*16 + 4, w->right[1]);
Fx3WriteReg32(FX3_GPIF_RIGHT_WAVEFORM + i*16 + 8, w->right[2]);
}
}
Fx3GpifConfigureCommon(functions, num_functions, registers, num_registers);
}
void Fx3GpifPibStart(uint16_t clock_divisor_x2)
{
Fx3WriteReg32(FX3_GCTL_PIB_CORE_CLK,
(((clock_divisor_x2 >> 1)-1) << FX3_GCTL_PIB_CORE_CLK_DIV_SHIFT) |
(3UL << FX3_GCTL_PIB_CORE_CLK_SRC_SHIFT));
if (clock_divisor_x2 & 1)
Fx3SetReg32(FX3_GCTL_PIB_CORE_CLK, FX3_GCTL_PIB_CORE_CLK_HALFDIV);
Fx3SetReg32(FX3_GCTL_PIB_CORE_CLK, FX3_GCTL_PIB_CORE_CLK_CLK_EN);
Fx3WriteReg32(FX3_PIB_POWER, 0);
Fx3UtilDelayUs(10);
Fx3SetReg32(FX3_PIB_POWER, FX3_PIB_POWER_RESETN);
while(!(Fx3ReadReg32(FX3_PIB_POWER) & FX3_PIB_POWER_ACTIVE))
;
Fx3ClearReg32(FX3_PIB_DLL_CTRL, FX3_PIB_DLL_CTRL_ENABLE);
Fx3UtilDelayUs(1);
Fx3WriteReg32(FX3_PIB_DLL_CTRL,
(clock_divisor_x2<11? FX3_PIB_DLL_CTRL_HIGH_FREQ : 0UL) |
FX3_PIB_DLL_CTRL_ENABLE);
Fx3UtilDelayUs(1);
Fx3ClearReg32(FX3_PIB_DLL_CTRL, FX3_PIB_DLL_CTRL_DLL_RESET_N);
Fx3UtilDelayUs(1);
Fx3SetReg32(FX3_PIB_DLL_CTRL, FX3_PIB_DLL_CTRL_DLL_RESET_N);
Fx3UtilDelayUs(1);
while(!(Fx3ReadReg32(FX3_PIB_DLL_CTRL) & FX3_PIB_DLL_CTRL_DLL_STAT))
;
Fx3WriteReg32(FX3_VIC_VEC_ADDRESS + (FX3_IRQ_GPIF_CORE<<2), Fx3GpifPibIsr);
Fx3WriteReg32(FX3_PIB_INTR, Fx3ReadReg32(FX3_PIB_INTR));
Fx3WriteReg32(FX3_PIB_INTR_MASK, FX3_PIB_INTR_MASK_GPIF_ERR |
FX3_PIB_INTR_MASK_GPIF_INTERRUPT);
Fx3WriteReg32(FX3_VIC_INT_ENABLE, (1UL << FX3_IRQ_GPIF_CORE));
}
void Fx3GpifPibStop(void)
{
Fx3WriteReg32(FX3_PIB_INTR_MASK, 0UL);
Fx3WriteReg32(FX3_VIC_INT_CLEAR, (1UL << FX3_IRQ_GPIF_CORE));
Fx3WriteReg32(FX3_PIB_INTR_MASK, 0UL);
Fx3WriteReg32(FX3_PIB_INTR, ~0UL);
Fx3WriteReg32(FX3_PIB_POWER, 0UL);
Fx3UtilDelayUs(10);
Fx3ClearReg32(FX3_GCTL_PIB_CORE_CLK, FX3_GCTL_PIB_CORE_CLK_CLK_EN);
}
Fx3GpifStat_t Fx3GpifGetStat(uint8_t *current_state)
{
uint32_t stat = Fx3ReadReg32(FX3_GPIF_WAVEFORM_CTRL_STAT);
if (current_state)
*current_state =
(stat & FX3_GPIF_WAVEFORM_CTRL_STAT_CURRENT_STATE_MASK)
>> FX3_GPIF_WAVEFORM_CTRL_STAT_CURRENT_STATE_SHIFT;
return (stat & FX3_GPIF_WAVEFORM_CTRL_STAT_GPIF_STAT_MASK)
>> FX3_GPIF_WAVEFORM_CTRL_STAT_GPIF_STAT_SHIFT;
}

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/*
* Copyright (C) 2018 Marcus Comstedt
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef BSP_GPIF_H_
#define BSP_GPIF_H_
#include <stdint.h>
#include <rdb/gpif.h>
/* Perform bitwise operations on the following constants to achieve the
corresponding logical operations on the four 1-bit operands */
#define FX3_GPIF_FUNCTION_Fa 0xAAAAU
#define FX3_GPIF_FUNCTION_Fb 0xCCCCU
#define FX3_GPIF_FUNCTION_Fc 0xF0F0U
#define FX3_GPIF_FUNCTION_Fd 0xFF00U
/* Fixed function alphas and betas */
/* (Alpha 4-7 and Beta 0-3 are user defined) */
#define FX3_GPIF_ALPHA_DQ_OEN (1UL<<0) /* Alpha 0 */
#define FX3_GPIF_ALPHA_UPDATE_DOUT (1UL<<1) /* Alpha 1 */
#define FX3_GPIF_ALPHA_SAMPLE_DIN (1UL<<2) /* Alpha 2 */
#define FX3_GPIF_ALPHA_SAMPLE_AIN (1UL<<3) /* Alpha 3 */
#define FX3_GPIF_BETA_THREAD_0 (0UL<<4) /* Beta 4&5 */
#define FX3_GPIF_BETA_THREAD_1 (1UL<<4) /* - " - */
#define FX3_GPIF_BETA_THREAD_2 (2UL<<4) /* - " - */
#define FX3_GPIF_BETA_THREAD_3 (3UL<<4) /* - " - */
#define FX3_GPIF_BETA_RQ_POP (1UL<<6) /* Beta 6 */
#define FX3_GPIF_BETA_WQ_PUSH (1UL<<7) /* Beta 7 */
#define FX3_GPIF_BETA_RQ_POP_ADDR (1UL<<8) /* Beta 8 */
#define FX3_GPIF_BETA_WQ_PUSH_ADDR (1UL<<9) /* Beta 9 */
#define FX3_GPIF_BETA_A_OEN (1UL<<10) /* Beta 10 */
/* 11 = ? */
#define FX3_GPIF_BETA_COUNT_CTRL (1UL<<12) /* Beta 12 */
#define FX3_GPIF_BETA_LD_CTRL_COUNT (1UL<<13) /* Beta 13 */
#define FX3_GPIF_BETA_COUNT_ADDR (1UL<<14) /* Beta 14 */
#define FX3_GPIF_BETA_LD_ADDR_COUNT (1UL<<15) /* Beta 15 */
#define FX3_GPIF_BETA_COUNT_DATA (1UL<<16) /* Beta 16 */
#define FX3_GPIF_BETA_LD_DATA_COUNT (1UL<<17) /* Beta 17 */
#define FX3_GPIF_BETA_INTR_CPU (1UL<<18) /* Beta 18 */
#define FX3_GPIF_BETA_INTR_HOST (1UL<<19) /* Beta 19 */
#define FX3_GPIF_BETA_UPDATE_AOUT (1UL<<20) /* Beta 20 */
#define FX3_GPIF_BETA_REGISTER_ACCESS (1UL<<21) /* Beta 21 */
/* 22, 23, 24 = ? */
#define FX3_GPIF_BETA_ASSERT_DRQ (1UL<<25) /* Beta 25 */
#define FX3_GPIF_BETA_DEASSERT_DRQ (1UL<<26) /* Beta 26 */
/* 27, 28, 29 = ? */
#define FX3_GPIF_BETA_COMMIT (1UL<<30) /* Beta 30 */
#define FX3_GPIF_BETA_PP_ACCESS (1UL<<31) /* Beta 31 */
/* For compatibility with GPIF II Designer output */
typedef struct {
uint32_t left[3], right[3];
} Fx3GpifWaveformCompat_t;
typedef struct {
uint32_t state[3];
uint16_t left, right;
} Fx3GpifWaveform_t;
#define GPIF_START_STATE(n) {(n)&0xff,0,0}
#define GPIF_STATE(n,Fa,Fb,Fc,Fd,f0,f1,AL,AR,B,rep,BD) { \
((n)&0xff)|(((Fa)&0x1f)<<8)|(((Fb)&0x1f)<<13)|(((Fc)&0x1f)<<18)|(((Fd)&0x1f)<<23)|(((f0)&0xf)<<28), \
(((f0)&0x10)>>4)|(((f1)&0x1f)<<1)|(((AL)&0xff)<<6)|(((AR)&0xff)<<14)|(((B)&0x3ff)<<22), \
(((B)&0xfffffc00)>>10)|(((rep)&0xff)<<22)|(((BD)&1)<<30)|(1UL<<31)}
typedef enum {
FX3_GPIF_CTRL_BUS_DIRECTION_INPUT = 0,
FX3_GPIF_CTRL_BUS_DIRECTION_OUTPUT,
FX3_GPIF_CTRL_BUS_DIRECTION_BIDIR,
FX3_GPIF_CTRL_BUS_DIRECTION_OPEN_DRAIN,
} Fx3GpifCtrlBusDirection_t;
typedef enum {
FX3_GPIF_OEN_CFG_OUTPUT = 0,
FX3_GPIF_OEN_CFG_INPUT,
FX3_GPIF_OEN_CFG_DYNAMIC, /* Controlled by alpha/beta */
} Fx3GpifOenCfg_t;
typedef enum {
FX3_GPIF_LAMBDA_INDEX_CTL0 = 0, /* GPIO 17 */
FX3_GPIF_LAMBDA_INDEX_CTL1, /* GPIO 18 */
FX3_GPIF_LAMBDA_INDEX_CTL2, /* GPIO 19 */
FX3_GPIF_LAMBDA_INDEX_CTL3, /* GPIO 20 */
FX3_GPIF_LAMBDA_INDEX_CTL4, /* GPIO 21 */
FX3_GPIF_LAMBDA_INDEX_CTL5, /* GPIO 22 */
FX3_GPIF_LAMBDA_INDEX_CTL6, /* GPIO 23 */
FX3_GPIF_LAMBDA_INDEX_CTL7, /* GPIO 24 */
FX3_GPIF_LAMBDA_INDEX_CTL8, /* GPIO 25 */
FX3_GPIF_LAMBDA_INDEX_CTL9, /* GPIO 26 */
FX3_GPIF_LAMBDA_INDEX_CTL10, /* GPIO 27 */
FX3_GPIF_LAMBDA_INDEX_CTL11, /* GPIO 28 */
FX3_GPIF_LAMBDA_INDEX_CTL12, /* GPIO 29 */
FX3_GPIF_LAMBDA_INDEX_CTL13, /* GPIO 49 */
FX3_GPIF_LAMBDA_INDEX_CTL14, /* GPIO 48 */
FX3_GPIF_LAMBDA_INDEX_CTL15, /* GPIO 47 */
FX3_GPIF_LAMBDA_INDEX_OUT_REG_CR_VALID = 16,
FX3_GPIF_LAMBDA_INDEX_IN_REG_CR_VALID = 17,
FX3_GPIF_LAMBDA_INDEX_CTRL_CNT_HIT = 18,
FX3_GPIF_LAMBDA_INDEX_ADDR_CNT_HIT = 19,
FX3_GPIF_LAMBDA_INDEX_DATA_CNT_HIT = 20,
FX3_GPIF_LAMBDA_INDEX_CTRL_CMP_MATCH = 21,
FX3_GPIF_LAMBDA_INDEX_ADDR_CMP_MATCH = 22,
FX3_GPIF_LAMBDA_INDEX_DATA_CMP_MATCH = 23,
FX3_GPIF_LAMBDA_INDEX_DMA_WM = 24,
FX3_GPIF_LAMBDA_INDEX_DMA_RDY_ADDR = 25,
FX3_GPIF_LAMBDA_INDEX_DMA_RDY = 26,
/* 27, 28 = ? */
FX3_GPIF_LAMBDA_INDEX_INTR_PEND = 29,
FX3_GPIF_LAMBDA_INDEX_FW_TRG = 30,
FX3_GPIF_LAMBDA_INDEX_OUT_ADDR_VALID = 31,
} Fx3GpifLambdaIndex_t;
typedef enum {
FX3_GPIF_OMEGA_INDEX_ALPHA4 = 0,
FX3_GPIF_OMEGA_INDEX_ALPHA5,
FX3_GPIF_OMEGA_INDEX_ALPHA6,
FX3_GPIF_OMEGA_INDEX_ALPHA7,
FX3_GPIF_OMEGA_INDEX_BETA0 = 8,
FX3_GPIF_OMEGA_INDEX_BETA1,
FX3_GPIF_OMEGA_INDEX_BETA2,
FX3_GPIF_OMEGA_INDEX_BETA3,
FX3_GPIF_OMEGA_INDEX_EMPTY_FULL_TH0 = 16,
FX3_GPIF_OMEGA_INDEX_EMPTY_FULL_TH1,
FX3_GPIF_OMEGA_INDEX_EMPTY_FULL_TH2,
FX3_GPIF_OMEGA_INDEX_EMPTY_FULL_TH3,
FX3_GPIF_OMEGA_INDEX_PARTIAL_TH0,
FX3_GPIF_OMEGA_INDEX_PARTIAL_TH1,
FX3_GPIF_OMEGA_INDEX_PARTIAL_TH2,
FX3_GPIF_OMEGA_INDEX_PARTIAL_TH3,
FX3_GPIF_OMEGA_INDEX_EMPTY_FULL_CURRENT,
FX3_GPIF_OMEGA_INDEX_PARTIAL_CURRENT,
FX3_GPIF_OMEGA_INDEX_PP_DRQR5,
FX3_GPIF_OMEGA_INDEX_CONSTANT_0 = 31
} Fx3GpifOmegaIndex_t;
typedef struct {
uint32_t config;
uint32_t bus_config;
uint32_t bus_config2;
uint32_t ad_config;
uint32_t status;
uint32_t intr;
uint32_t intr_mask;
uint32_t serial_in_config;
uint32_t serial_out_config;
uint32_t ctrl_bus_direction;
uint32_t ctrl_bus_default;
uint32_t ctrl_bus_polarity;
uint32_t ctrl_bus_toggle;
uint32_t ctrl_bus_select[16];
uint32_t ctrl_count_config;
uint32_t ctrl_count_reset;
uint32_t ctrl_count_limit;
uint32_t addr_count_config;
uint32_t addr_count_reset;
uint32_t addr_count_limit;
uint32_t state_count_config;
uint32_t state_count_limit;
uint32_t data_count_config;
uint32_t data_count_reset;
uint32_t data_count_limit;
uint32_t ctrl_comp_value;
uint32_t ctrl_comp_mask;
uint32_t data_comp_value;
uint32_t data_comp_mask;
uint32_t addr_comp_value;
uint32_t addr_comp_mask;
uint32_t data_ctrl;
uint32_t ingress_data[4];
uint32_t egress_data[4];
uint32_t ingress_address[4];
uint32_t egress_address[4];
uint32_t thread_config[4];
uint32_t lambda_stat;
uint32_t alpha_stat;
uint32_t beta_stat;
uint32_t waveform_ctrl_stat;
uint32_t waveform_switch;
uint32_t waveform_switch_timeout;
uint32_t crc_config;
uint32_t crc_data;
uint32_t beta_deassert;
} Fx3GpifRegisters_t;
typedef enum {
FX3_GPIF_INVALID = 0,
FX3_GPIF_ARMED = 2,
FX3_GPIF_RUNNING,
FX3_GPIF_DONE,
FX3_GPIF_PAUSED,
FX3_GPIF_SWITCHING,
FX3_GPIF_ERROR,
} Fx3GpifStat_t;
extern void Fx3GpifStart(uint8_t state, uint8_t alpha);
extern void Fx3GpifStop(void);
extern void Fx3GpifInvalidate(void);
extern void Fx3GpifConfigure(const Fx3GpifWaveform_t *waveforms,
uint16_t num_waveforms,
const uint16_t *functions, uint16_t num_functions,
const Fx3GpifRegisters_t *registers);
extern void Fx3GpifConfigureCompat(const Fx3GpifWaveformCompat_t *waveforms,
const uint8_t *waveform_select,
uint16_t num_waveforms,
const uint16_t *functions, uint16_t num_functions,
const uint32_t *registers, uint16_t num_registers);
extern void Fx3GpifPibStart(uint16_t clock_divisor_x2);
extern void Fx3GpifPibStop(void);
extern Fx3GpifStat_t Fx3GpifGetStat(uint8_t *current_state);
#endif /* BSP_GPIF_H_ */

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/*
* Copyright (C) 2018 Marcus Comstedt
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include <bsp/gpio.h>
#include <bsp/regaccess.h>
#include <bsp/util.h>
#include <rdb/gpio.h>
#include <rdb/gctl.h>
void Fx3GpioInitClock(void)
{
Fx3WriteReg32(FX3_GCTL_GPIO_FAST_CLK,
FX3_GCTL_GPIO_FAST_CLK_CLK_EN |
(3UL << FX3_GCTL_GPIO_FAST_CLK_SRC_SHIFT) |
((GPIO_FAST_DIV - 1UL) << FX3_GCTL_GPIO_FAST_CLK_DIV_SHIFT));
Fx3UtilDelayUs(10);
Fx3WriteReg32(FX3_GCTL_GPIO_SLOW_CLK,
FX3_GCTL_GPIO_SLOW_CLK_CLK_EN |
((GPIO_SLOW_DIV - 1UL) << FX3_GCTL_GPIO_SLOW_CLK_DIV_SHIFT));
Fx3UtilDelayUs(10);
}
void Fx3GpioSetupSimple(uint8_t num, uint32_t config)
{
if (num < 61 &&
!(Fx3ReadReg32(FX3_GCTL_GPIO_COMPLEX + ((num & 32) >> 3))
& (1UL << (num & 31)))) {
Fx3WriteReg32(FX3_GPIO_SIMPLE + (num << 2), config);
Fx3SetReg32(FX3_GCTL_GPIO_SIMPLE + ((num & 32) >> 3),
1UL << (num & 31));
}
}
void Fx3GpioSetupComplex(uint8_t num, uint32_t config, uint32_t timer,
uint32_t period, uint32_t threshold)
{
if (num < 61) {
// There are only 8 instances of complex GPIO. The low 3 bits of
// the GPIO number selects which instance it is connected to.
uint8_t instance = num & 7;
if (!(Fx3ReadReg32(FX3_GCTL_GPIO_COMPLEX + ((num & 32) >> 3))
& (1UL << (num & 31)))) {
// Check for conflicting simple I/O
if ((Fx3ReadReg32(FX3_GCTL_GPIO_SIMPLE + ((num & 32) >> 3))
& (1UL << (num & 31))))
// GPIO already in use
return;
// Check for conflicting complex I/O
uint32_t mask = 0x01010101UL << instance;
if ((Fx3ReadReg32(FX3_GCTL_GPIO_COMPLEX + 0) & mask) ||
(Fx3ReadReg32(FX3_GCTL_GPIO_COMPLEX + 4) & mask))
// Instance already in use
return;
}
Fx3ClearReg32(FX3_PIN_STATUS + (instance << 4), FX3_PIN_STATUS_ENABLE);
Fx3WriteReg32(FX3_PIN_TIMER + (instance << 4), timer);
Fx3WriteReg32(FX3_PIN_PERIOD + (instance << 4), period);
Fx3WriteReg32(FX3_PIN_THRESHOLD + (instance << 4), threshold);
Fx3WriteReg32(FX3_PIN_STATUS + (instance << 4), config);
Fx3SetReg32(FX3_GCTL_GPIO_COMPLEX + ((num & 32) >> 3),
1UL << (num & 31));
}
}
void Fx3GpioSetOutputValueSimple(uint8_t num, uint8_t value)
{
if (num < 61) {
Fx3WriteReg32(FX3_GPIO_SIMPLE + (num << 2),
(Fx3ReadReg32(FX3_GPIO_SIMPLE + (num << 2)) &
~(FX3_GPIO_SIMPLE_INTR | FX3_GPIO_SIMPLE_OUT_VALUE)) |
(value & FX3_GPIO_SIMPLE_OUT_VALUE));
}
}
uint8_t Fx3GpioGetInputValueSimple(uint8_t num)
{
if (num < 61) {
return (Fx3ReadReg32(FX3_GPIO_SIMPLE + (num << 2)) & FX3_GPIO_SIMPLE_IN_VALUE) >> 1;
} else {
return 0;
}
}

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/*
* Copyright (C) 2018 Marcus Comstedt
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef BSP_GPIO_H_
#define BSP_GPIO_H_
#include <stdint.h>
#include <rdb/gpio.h>
#include <bsp/gctl.h>
#ifndef GPIO_FAST_DIV
#define GPIO_FAST_DIV 2
#endif
#ifndef GPIO_SLOW_DIV
#define GPIO_SLOW_DIV 48
#endif
#define GPIO_FAST_CLK (SYS_CLK / GPIO_FAST_DIV)
#define GPIO_SLOW_CLK (GPIO_FAST_CLK / GPIO_SLOW_DIV)
typedef enum {
FX3_GPIO_TIMER_MODE_SHUTDOWN = 0,
FX3_GPIO_TIMER_MODE_FAST_CLK,
FX3_GPIO_TIMER_MODE_SLOW_CLK,
FX3_GPIO_TIMER_MODE_STANDBY_CLK,
FX3_GPIO_TIMER_MODE_POS_EDGE,
FX3_GPIO_TIMER_MODE_NEG_EDGE,
FX3_GPIO_TIMER_MODE_ANY_EDGE,
} Fx3GpioTimerMode_t;
typedef enum {
FX3_GPIO_INTR_MODE_NONE = 0,
FX3_GPIO_INTR_MODE_POS_EDGE,
FX3_GPIO_INTR_MODE_NEG_EDGE,
FX3_GPIO_INTR_MODE_ANY_EDGE,
FX3_GPIO_INTR_MODE_LOW_LEVEL,
FX3_GPIO_INTR_MODE_HIGH_LEVEL,
FX3_GPIO_INTR_MODE_TIMER_THRESHOLD,
FX3_GPIO_INTR_MODE_TIMER_0,
} Fx3GpioIntrMode_t;
typedef enum {
FX3_GPIO_PIN_MODE_STATIC = 0,
FX3_GPIO_PIN_MODE_TOGGLE,
FX3_GPIO_PIN_MODE_SAMPLENOW,
FX3_GPIO_PIN_MODE_PULSENOW,
FX3_GPIO_PIN_MODE_PULSE,
FX3_GPIO_PIN_MODE_PWM,
FX3_GPIO_PIN_MODE_MEASURE_LOW,
FX3_GPIO_PIN_MODE_MEASURE_HIGH,
FX3_GPIO_PIN_MODE_MEASURE_LOW_ONCE,
FX3_GPIO_PIN_MODE_MEASURE_HIGH_ONCE,
FX3_GPIO_PIN_MODE_MEASURE_NEG,
FX3_GPIO_PIN_MODE_MEASURE_POS,
FX3_GPIO_PIN_MODE_MEASURE_ANY,
FX3_GPIO_PIN_MODE_MEASURE_NEG_ONCE,
FX3_GPIO_PIN_MODE_MEASURE_POS_ONCE,
FX3_GPIO_PIN_MODE_MEASURE_ANY_ONCE,
} Fx3GpioPinMode_t;
extern void Fx3GpioInitClock(void);
extern void Fx3GpioSetupSimple(uint8_t num, uint32_t config);
extern void Fx3GpioSetupComplex(uint8_t num, uint32_t config, uint32_t timer,
uint32_t period, uint32_t threshold);
extern void Fx3GpioSetOutputValueSimple(uint8_t num, uint8_t value);
extern uint8_t Fx3GpioGetInputValueSimple(uint8_t num);
#endif /* BSP_GPIO_H_ */

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/*
* Copyright (C) 2018 Marcus Comstedt
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include <bsp/irq.h>
#include <bsp/regaccess.h>
#include <bsp/cache.h>
#include <rdb/vic.h>
void Fx3IrqInit(void)
{
Fx3WriteReg32(FX3_VIC_INT_CLEAR, ~0UL);
Fx3WriteReg32(FX3_VIC_INT_SELECT, 0UL);
Fx3IrqInstallVectors();
Fx3CacheCleanDCache();
Fx3CacheInvalidateICache();
/* Move vector base to 0 */
uint32_t creg;
__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 0" : "=r"(creg));
creg &= ~(1UL << 13);
__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 0" : : "r"(creg));
}

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/*
* Copyright (C) 2018 Marcus Comstedt
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef BSP_IRQ_H_
#define BSP_IRQ_H_
#include <stdint.h>
typedef enum {
FX3_IRQ_GCTL_CORE = 0,
FX3_IRQ_SW_INTR = 1,
FX3_IRQ_WATCHDOG_TIMER = 4,
FX3_IRQ_GPIF_DMA = 6,
FX3_IRQ_GPIF_CORE = 7,
FX3_IRQ_USB_DMA = 8,
FX3_IRQ_USB_CORE = 9,
FX3_IRQ_STORAGE_DMA = 11,
FX3_IRQ_STORAGE0_CORE = 12,
FX3_IRQ_STORAGE1_CORE = 13,
FX3_IRQ_I2C_CORE = 15,
FX3_IRQ_I2S_CORE = 16,
FX3_IRQ_SPI_CORE = 17,
FX3_IRQ_UART_CORE = 18,
FX3_IRQ_GPIO_CORE = 19,
FX3_IRQ_PERIPH_DMA = 20,
FX3_IRQ_GCTL_POWER = 21,
} Fx3IrqSource_t;
static inline void Fx3IrqEnableInterrupts(void)
{
uint32_t cpsr;
__asm__ __volatile__("mrs %0,cpsr" : "=r"(cpsr));
__asm__ __volatile__("msr cpsr_c,%0" : : "r"(cpsr&0x3f));
}
static inline void Fx3IrqDisableInterrupts(void)
{
uint32_t cpsr;
__asm__ __volatile__("mrs %0,cpsr" : "=r"(cpsr));
__asm__ __volatile__("msr cpsr_c,%0" : : "r"(cpsr|0xc0));
}
extern void Fx3IrqInit(void);
extern void Fx3IrqInstallVectors(void);
#endif /* BSP_IRQ_H_ */

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/*
* Copyright (C) 2018 Marcus Comstedt
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef BSP_REGACCESS_H_
#define BSP_REGACCESS_H_
#include <stdint.h>
#define Fx3ReadReg32(a) (*(volatile uint32_t *)(void*)(a))
#define Fx3WriteReg32(a, v) ((*(volatile uint32_t *)(void*)(a))=(uint32_t)(v))
#define Fx3SetReg32(a, v) Fx3WriteReg32((a), Fx3ReadReg32((a)) | (v))
#define Fx3ClearReg32(a, v) Fx3WriteReg32((a), Fx3ReadReg32((a)) & ~(v))
#define Fx3SetField32(a, f, v) Fx3WriteReg32((a), (Fx3ReadReg32((a)) & ~(a ## _ ## f ## _MASK)) | (((v) << (a ## _ ## f ## _SHIFT)) & (a ## _ ## f ## _MASK)))
#define Fx3GetField32(a, f) ((Fx3ReadReg32((a)) & (a ## _ ## f ## _MASK)) >> (a ## _ ## f ## _SHIFT))
#endif /* BSP_REGACCESS_H_ */

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/*
* Copyright (C) 2018 Marcus Comstedt
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include <bsp/uart.h>
#include <bsp/gctl.h>
#include <bsp/regaccess.h>
#include <bsp/util.h>
#include <rdb/uart.h>
#include <rdb/gctl.h>
void Fx3UartInit(uint32_t baud_rate, Fx3UartParity_t parity, Fx3UartStopBits_t stop_bits)
{
/* Configure baud rate generator */
Fx3WriteReg32(FX3_GCTL_UART_CORE_CLK,
(((SYS_CLK/16 / baud_rate - 1) << FX3_GCTL_UART_CORE_CLK_DIV_SHIFT) & FX3_GCTL_UART_CORE_CLK_DIV_MASK) |
(3UL << FX3_GCTL_UART_CORE_CLK_SRC_SHIFT) |
FX3_GCTL_UART_CORE_CLK_CLK_EN);
/* Reset UART */
Fx3WriteReg32(FX3_UART_POWER, 0);
Fx3UtilDelayUs(10);
Fx3WriteReg32(FX3_UART_POWER, FX3_UART_POWER_RESETN);
while(!(Fx3ReadReg32(FX3_UART_POWER) & FX3_UART_POWER_ACTIVE))
;
/* Configure and enable UART */
Fx3WriteReg32(FX3_UART_CONFIG,
stop_bits | parity |
FX3_UART_CONFIG_ENABLE |
FX3_UART_CONFIG_TX_ENABLE);
}
void Fx3UartTxByte(uint8_t byte)
{
while(!(Fx3ReadReg32(FX3_UART_STATUS) & FX3_UART_STATUS_TX_SPACE))
;
Fx3WriteReg32(FX3_UART_EGRESS_DATA, byte);
}
void Fx3UartTxBytes(const uint8_t *byte, size_t cnt)
{
while(cnt--)
Fx3UartTxByte(*byte++);
}
extern void Fx3UartTxChar(char c)
{
if (c == '\n')
Fx3UartTxByte('\r');
Fx3UartTxByte(c);
}
extern void Fx3UartTxString(const char *str)
{
char c;
while ((c = *str++))
Fx3UartTxChar(c);
}
void Fx3UartTxFlush(void)
{
while(!(Fx3ReadReg32(FX3_UART_STATUS) & FX3_UART_STATUS_TX_DONE))
;
}

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/*
* Copyright (C) 2018 Marcus Comstedt
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef BSP_UART_H_
#define BSP_UART_H_
#include <stdint.h>
#include <stddef.h>
#include <rdb/uart.h>
typedef enum {
FX3_UART_NO_PARITY = 0,
FX3_UART_EVEN_PARITY = FX3_UART_CONFIG_PARITY,
FX3_UART_ODD_PARITY = FX3_UART_CONFIG_PARITY | FX3_UART_CONFIG_PARITY_ODD,
FX3_UART_SPACE_PARITY = FX3_UART_CONFIG_PARITY | FX3_UART_CONFIG_PARITY_STICKY,
FX3_UART_MARK_PARITY = FX3_UART_CONFIG_PARITY | FX3_UART_CONFIG_PARITY_STICKY | FX3_UART_CONFIG_TX_STICKY_BIT | FX3_UART_CONFIG_RX_STICKY_BIT,
} Fx3UartParity_t;
typedef enum {
FX3_UART_1_STOP_BIT = 1UL << FX3_UART_CONFIG_STOP_BITS_SHIFT,
FX3_UART_2_STOP_BITS = 2UL << FX3_UART_CONFIG_STOP_BITS_SHIFT,
} Fx3UartStopBits_t;
extern void Fx3UartInit(uint32_t baud_rate, Fx3UartParity_t parity, Fx3UartStopBits_t stop_bits);
extern void Fx3UartTxByte(uint8_t byte);
extern void Fx3UartTxBytes(const uint8_t *byte, size_t cnt);
extern void Fx3UartTxChar(char c);
extern void Fx3UartTxString(const char *str);
extern void Fx3UartTxFlush(void);
#endif /* BSP_UART_H_ */

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/*
* Copyright (C) 2018 Marcus Comstedt
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include <bsp/usb.h>
#include <bsp/regaccess.h>
#include <bsp/dma.h>
#include <bsp/irq.h>
#include <bsp/util.h>
#include <bsp/uart.h>
#include <rdb/gctl.h>
#include <rdb/uib.h>
#include <rdb/uibin.h>
#include <rdb/vic.h>
static const struct Fx3UsbCallbacks *Fx3UsbUserCallbacks = NULL;
static void Fx3UsbGctlCoreIsr(void) __attribute__ ((isr ("IRQ")));
static void Fx3UsbUsbCoreIsr(void) __attribute__ ((isr ("IRQ")));
static void Fx3UsbGctlPowerIsr(void) __attribute__ ((isr ("IRQ")));
static void Fx3UsbWritePhyReg(uint16_t phy_addr, uint16_t phy_val)
{
if (!(Fx3ReadReg32(FX3_OTG_CTRL) & FX3_OTG_CTRL_SSDEV_ENABLE))
return;
Fx3WriteReg32(0xe0033024, phy_addr);
Fx3WriteReg32(0xe0033024, phy_addr | (1UL << 16));
while(!(Fx3ReadReg32(0xe0033028) & (1UL << 16)))
;
Fx3WriteReg32(0xe0033024, phy_addr);
while((Fx3ReadReg32(0xe0033028) & (1UL << 16)))
;
Fx3WriteReg32(0xe0033024, phy_val);
Fx3WriteReg32(0xe0033024, phy_val | (1UL << 17));
while(!(Fx3ReadReg32(0xe0033028) & (1UL << 16)))
;
Fx3WriteReg32(0xe0033024, phy_val);
while((Fx3ReadReg32(0xe0033028) & (1UL << 16)))
;
Fx3WriteReg32(0xe0033024, phy_val | (1UL << 19));
while(!(Fx3ReadReg32(0xe0033028) & (1UL << 16)))
;
Fx3WriteReg32(0xe0033024, phy_val);
while((Fx3ReadReg32(0xe0033028) & (1UL << 16)))
;
}
static void Fx3UsbConnectHighSpeed(void)
{
Fx3UsbWritePhyReg(0x1005, 0x0000);
/* Force the link state machine into SS.Disabled. */
Fx3WriteReg32(FX3_LNK_LTSSM_STATE,(0UL << (6)) | (1UL << 12));
/* Change EPM config to full speed */
Fx3ClearReg32(FX3_GCTL_UIB_CORE_CLK, FX3_GCTL_UIB_CORE_CLK_CLK_EN);
Fx3UtilDelayUs(5);
Fx3WriteReg32(FX3_GCTL_UIB_CORE_CLK,
(2UL << FX3_GCTL_UIB_CORE_CLK_PCLK_SRC_SHIFT) |
(2UL << FX3_GCTL_UIB_CORE_CLK_EPMCLK_SRC_SHIFT));
Fx3SetReg32(FX3_GCTL_UIB_CORE_CLK, FX3_GCTL_UIB_CORE_CLK_CLK_EN);
Fx3UtilDelayUs(5);
/* Switch the EPM to USB 2.0 mode, turn off USB 3.0 PHY and remove Rx Termination. */
Fx3ClearReg32(FX3_OTG_CTRL, FX3_OTG_CTRL_SSDEV_ENABLE);
Fx3UtilDelayUs(5);
Fx3ClearReg32(FX3_OTG_CTRL, FX3_OTG_CTRL_SSEPM_ENABLE);
Fx3ClearReg32(FX3_UIB_INTR_MASK, FX3_UIB_INTR_DEV_CTL_INT |
FX3_UIB_INTR_DEV_EP_INT |
FX3_UIB_INTR_LNK_INT |
FX3_UIB_INTR_PROT_INT |
FX3_UIB_INTR_PROT_EP_INT |
FX3_UIB_INTR_EPM_URUN);
*(volatile uint32_t *)(void*)(FX3_LNK_PHY_CONF) &= 0x1FFFFFFFUL;
Fx3WriteReg32(FX3_LNK_PHY_MPLL_STATUS,0x910410);
/* Power cycle the PHY blocks. */
Fx3ClearReg32(FX3_GCTL_CONTROL, FX3_GCTL_CONTROL_USB_POWER_EN);
Fx3UtilDelayUs(5);
Fx3SetReg32(FX3_GCTL_CONTROL, FX3_GCTL_CONTROL_USB_POWER_EN);
Fx3UtilDelayUs(10);
/* Clear USB 2.0 interrupts. */
Fx3WriteReg32(FX3_DEV_CTRL_INTR, ~0UL);
Fx3WriteReg32(FX3_DEV_EP_INTR, ~0UL);
Fx3WriteReg32(FX3_OTG_INTR, ~0UL);
/* Clear and disable USB 3.0 interrupts. */
Fx3WriteReg32(FX3_LNK_INTR_MASK, 0UL);
Fx3WriteReg32(FX3_LNK_INTR, ~0UL);
Fx3WriteReg32(FX3_PROT_INTR_MASK, 0UL);
Fx3WriteReg32(FX3_PROT_INTR, ~0UL);
Fx3SetReg32(FX3_UIB_INTR_MASK, FX3_UIB_INTR_DEV_CTL_INT |
FX3_UIB_INTR_DEV_EP_INT |
FX3_UIB_INTR_LNK_INT |
FX3_UIB_INTR_PROT_INT |
FX3_UIB_INTR_PROT_EP_INT |
FX3_UIB_INTR_EPM_URUN);
/* Disable EP0-IN and EP0-OUT (USB-2). */
Fx3ClearReg32(FX3_DEV_EPI_CS+0, FX3_DEV_EPI_CS_VALID);
Fx3ClearReg32(FX3_DEV_EPO_CS+0, FX3_DEV_EPO_CS_VALID);
Fx3WriteReg32(FX3_EHCI_PORTSC, (1UL << 22));
Fx3WriteReg32(FX3_DEV_PWR_CS, (1UL << 2) | (1UL << 3));
/* Enable USB 2.0 PHY. */
Fx3UtilDelayUs(2);
Fx3SetReg32(FX3_OTG_CTRL, (1UL << 13));
Fx3UtilDelayUs(100);
Fx3WriteReg32(FX3_PHY_CONF, 0xd4a480UL);
Fx3WriteReg32(FX3_PHY_CLK_AND_TEST, 0xa0000011UL);
Fx3UtilDelayUs(80);
Fx3ClearReg32(FX3_GCTL_UIB_CORE_CLK, FX3_GCTL_UIB_CORE_CLK_CLK_EN);
Fx3UtilDelayUs(5);
Fx3WriteReg32(FX3_GCTL_UIB_CORE_CLK,
(2UL << FX3_GCTL_UIB_CORE_CLK_PCLK_SRC_SHIFT) |
(0UL << FX3_GCTL_UIB_CORE_CLK_EPMCLK_SRC_SHIFT));
Fx3SetReg32(FX3_GCTL_UIB_CORE_CLK, FX3_GCTL_UIB_CORE_CLK_CLK_EN);
Fx3UtilDelayUs(5);
/* For USB 2.0 connections, enable pull-up on D+ pin. */
Fx3ClearReg32(FX3_DEV_PWR_CS, (1UL << 3));
}
static void Fx3UsbConnectSuperSpeed(void)
{
Fx3WriteReg32(FX3_LNK_PHY_TX_TRIM, 0x0b569011UL);
Fx3UsbWritePhyReg(0x1006, 0x180);
Fx3UsbWritePhyReg(0x1024, 0x0080);
/* Switch EPM clock to USB 3.0 mode */
Fx3ClearReg32(FX3_GCTL_UIB_CORE_CLK, FX3_GCTL_UIB_CORE_CLK_CLK_EN);
Fx3UtilDelayUs(5);
Fx3WriteReg32(FX3_GCTL_UIB_CORE_CLK,
(1UL << FX3_GCTL_UIB_CORE_CLK_PCLK_SRC_SHIFT) |
(1UL << FX3_GCTL_UIB_CORE_CLK_EPMCLK_SRC_SHIFT));
Fx3SetReg32(FX3_GCTL_UIB_CORE_CLK, FX3_GCTL_UIB_CORE_CLK_CLK_EN);
Fx3UtilDelayUs(5);
Fx3WriteReg32(FX3_LNK_PHY_CONF,
FX3_LNK_PHY_CONF_RX_TERMINATION_ENABLE |
FX3_LNK_PHY_CONF_RX_TERMINATION_OVR_VAL |
FX3_LNK_PHY_CONF_RX_TERMINATION_OVR |
(1UL << FX3_LNK_PHY_CONF_PHY_MODE_SHIFT));
Fx3SetReg32(FX3_OTG_CTRL, FX3_OTG_CTRL_SSEPM_ENABLE);
/* Reset EPM mux */
Fx3SetReg32(FX3_IEPM_CS,
FX3_IEPM_CS_EPM_MUX_RESET |
FX3_IEPM_CS_EPM_FLUSH);
Fx3UtilDelayUs(1);
Fx3ClearReg32(FX3_IEPM_CS,
FX3_IEPM_CS_EPM_MUX_RESET |
FX3_IEPM_CS_EPM_FLUSH);
Fx3UtilDelayUs(1);
Fx3UsbWritePhyReg(0x0030, 0x00c0);
Fx3UsbWritePhyReg(0x1010, 0x0080);
Fx3WriteReg32(FX3_EEPM_ENDPOINT+0,
(512UL << FX3_EEPM_ENDPOINT_PACKET_SIZE_SHIFT));
Fx3WriteReg32(FX3_IEPM_ENDPOINT+0,
(512UL << FX3_IEPM_ENDPOINT_PACKET_SIZE_SHIFT));
}
static void Fx3UsbEnablePhy(void)
{
Fx3WriteReg32(FX3_OTG_INTR, ~0UL);
Fx3WriteReg32(FX3_LNK_INTR, ~0UL);
Fx3WriteReg32(FX3_LNK_INTR_MASK,
FX3_LNK_INTR_MASK_LTSSM_RESET |
FX3_LNK_INTR_MASK_LTSSM_DISCONNECT |
FX3_LNK_INTR_MASK_LTSSM_CONNECT |
FX3_LNK_INTR_MASK_LGO_U3 |
FX3_LNK_INTR_MASK_LTSSM_STATE_CHG);
Fx3WriteReg32(FX3_PROT_EP_INTR_MASK, 0);
Fx3WriteReg32(FX3_PROT_INTR, ~0UL);
Fx3WriteReg32(FX3_PROT_INTR_MASK,
FX3_PROT_INTR_MASK_STATUS_STAGE |
FX3_PROT_INTR_MASK_SUTOK_EN |
FX3_PROT_INTR_MASK_TIMEOUT_PORT_CFG_EN |
FX3_PROT_INTR_MASK_TIMEOUT_PORT_CAP_EN |
FX3_PROT_INTR_MASK_LMP_PORT_CFG_EN |
FX3_PROT_INTR_MASK_LMP_PORT_CAP_EN |
FX3_PROT_INTR_MASK_LMP_RCV_EN);
Fx3WriteReg32(FX3_DEV_CTRL_INTR, ~0UL);
Fx3WriteReg32(FX3_DEV_CTRL_INTR_MASK,
FX3_DEV_CTRL_INTR_MASK_URESUME |
FX3_DEV_CTRL_INTR_MASK_SUDAV |
FX3_DEV_CTRL_INTR_MASK_HSGRANT |
FX3_DEV_CTRL_INTR_MASK_URESET |
FX3_DEV_CTRL_INTR_MASK_SUSP);
Fx3WriteReg32(FX3_DEV_EP_INTR, ~0UL);
Fx3WriteReg32(FX3_DEV_EP_INTR_MASK, 0);
Fx3WriteReg32(FX3_UIB_INTR_MASK,
FX3_UIB_INTR_MASK_PROT_INT |
FX3_UIB_INTR_MASK_LNK_INT |
FX3_UIB_INTR_MASK_DEV_CTL_INT);
Fx3WriteReg32(FX3_VIC_INT_ENABLE, (1UL << FX3_IRQ_USB_CORE));
Fx3SetReg32(FX3_GCTL_CONTROL, FX3_GCTL_CONTROL_USB_POWER_EN);
/* Setup LNK for superspeed */
Fx3WriteReg32(FX3_LNK_DEVICE_POWER_CONTROL,
FX3_LNK_DEVICE_POWER_CONTROL_AUTO_U2 |
FX3_LNK_DEVICE_POWER_CONTROL_AUTO_U1);
Fx3WriteReg32(0xe003309c, 10000);
Fx3WriteReg32(0xe0033080, 10000);
Fx3WriteReg32(0xe0033084, 0x00fa004b);
Fx3WriteReg32(0xe00330c4, 0x00000177);
Fx3WriteReg32(0xe0033078, 0x58);
Fx3WriteReg32(FX3_PROT_LMP_PORT_CAPABILITY_TIMER, 2312);
Fx3WriteReg32(FX3_PROT_LMP_PORT_CONFIGURATION_TIMER, 2312);
Fx3SetReg32(FX3_LNK_COMPLIANCE_PATTERN_8,
FX3_LNK_COMPLIANCE_PATTERN_8_LFPS);
Fx3WriteReg32(FX3_LNK_PHY_CONF,
FX3_LNK_PHY_CONF_RX_TERMINATION_OVR |
(1UL << FX3_LNK_PHY_CONF_PHY_MODE_SHIFT));
uint32_t old_int_enable = Fx3ReadReg32(FX3_VIC_INT_ENABLE);
Fx3WriteReg32(FX3_VIC_INT_CLEAR, ~0UL);
Fx3ClearReg32(FX3_GCTL_UIB_CORE_CLK, FX3_GCTL_UIB_CORE_CLK_CLK_EN);
Fx3UtilDelayUs(5);
Fx3WriteReg32(FX3_GCTL_UIB_CORE_CLK,
(2UL << FX3_GCTL_UIB_CORE_CLK_PCLK_SRC_SHIFT) |
(2UL << FX3_GCTL_UIB_CORE_CLK_EPMCLK_SRC_SHIFT));
Fx3SetReg32(FX3_GCTL_UIB_CORE_CLK, FX3_GCTL_UIB_CORE_CLK_CLK_EN);
Fx3UtilDelayUs(5);
Fx3WriteReg32(FX3_LNK_LTSSM_STATE,
(0UL << FX3_LNK_LTSSM_STATE_LTSSM_OVERRIDE_VALUE_SHIFT) |
FX3_LNK_LTSSM_STATE_LTSSM_OVERRIDE_EN);
Fx3SetReg32(FX3_OTG_CTRL, FX3_OTG_CTRL_SSDEV_ENABLE);
Fx3UtilDelayUs(100);
Fx3SetField32(FX3_LNK_CONF, EPM_FIRST_DELAY, 15UL);
Fx3SetReg32(FX3_LNK_CONF, FX3_LNK_CONF_LDN_DETECTION);
Fx3WriteReg32(FX3_LNK_PHY_MPLL_STATUS,
FX3_LNK_PHY_MPLL_STATUS_REF_SSP_EN |
(136UL << FX3_LNK_PHY_MPLL_STATUS_SSC_REF_CLK_SEL_SHIFT) |
(0UL << FX3_LNK_PHY_MPLL_STATUS_SSC_RANGE_SHIFT) |
FX3_LNK_PHY_MPLL_STATUS_SSC_EN |
(3UL << FX3_LNK_PHY_MPLL_STATUS_MPLL_MULTIPLIER_SHIFT));
Fx3UsbWritePhyReg(0x30, 0xc0);
Fx3ClearReg32(FX3_LNK_LTSSM_STATE, FX3_LNK_LTSSM_STATE_LTSSM_OVERRIDE_EN);
Fx3WriteReg32(FX3_LNK_PHY_CONF,
FX3_LNK_PHY_CONF_RX_TERMINATION_ENABLE |
FX3_LNK_PHY_CONF_RX_TERMINATION_OVR_VAL |
FX3_LNK_PHY_CONF_RX_TERMINATION_OVR |
(1UL << FX3_LNK_PHY_CONF_PHY_MODE_SHIFT));
Fx3UtilDelayUs(100);
Fx3WriteReg32(FX3_GCTL_UIB_CORE_CLK,
FX3_GCTL_UIB_CORE_CLK_CLK_EN |
(1UL << FX3_GCTL_UIB_CORE_CLK_PCLK_SRC_SHIFT) |
(1UL << FX3_GCTL_UIB_CORE_CLK_EPMCLK_SRC_SHIFT));
Fx3WriteReg32(FX3_VIC_INT_ENABLE, old_int_enable);
}
void Fx3UsbConnect(void)
{
Fx3WriteReg32(FX3_GCTL_IOPOWER_INTR, ~0UL);
Fx3WriteReg32(FX3_GCTL_IOPOWER_INTR_MASK, FX3_GCTL_IOPOWER_INTR_MASK_VBUS);
Fx3WriteReg32(FX3_VIC_INT_ENABLE, (1UL << FX3_IRQ_GCTL_POWER));
if (Fx3ReadReg32(FX3_GCTL_IOPOWER) & FX3_GCTL_IOPOWER_VBUS) {
Fx3UartTxString("VBUS POWER!\n");
Fx3UsbEnablePhy();
}
}
void Fx3UsbStallEp0(Fx3UsbSpeed_t s)
{
Fx3UartTxString("STALL EP0!\n");
if (s == FX3_USB_SUPER_SPEED){
Fx3SetReg32(FX3_PROT_EPI_CS1+0, FX3_PROT_EPI_CS1_STALL);
Fx3SetReg32(FX3_PROT_EPO_CS1+0, FX3_PROT_EPO_CS1_STALL);
Fx3UtilDelayUs(1);
Fx3SetReg32(FX3_PROT_CS, FX3_PROT_CS_SETUP_CLR_BUSY);
} else {
Fx3SetReg32(FX3_DEV_EPI_CS+0, FX3_DEV_EPI_CS_STALL);
Fx3SetReg32(FX3_DEV_EPO_CS+0, FX3_DEV_EPO_CS_STALL);
Fx3UtilDelayUs(1);
Fx3SetReg32(FX3_DEV_CS, FX3_DEV_CS_SETUP_CLR_BUSY);
}
}
void Fx3UsbUnstallEp0(Fx3UsbSpeed_t s)
{
if (s == FX3_USB_SUPER_SPEED){
Fx3ClearReg32(FX3_PROT_EPI_CS1+0, FX3_PROT_EPI_CS1_STALL);
Fx3ClearReg32(FX3_PROT_EPO_CS1+0, FX3_PROT_EPO_CS1_STALL);
Fx3UtilDelayUs(1);
Fx3SetReg32(FX3_PROT_CS, FX3_PROT_CS_SETUP_CLR_BUSY);
} else {
Fx3ClearReg32(FX3_DEV_EPI_CS+0,FX3_DEV_EPI_CS_STALL);
Fx3ClearReg32(FX3_DEV_EPO_CS+0,FX3_DEV_EPO_CS_STALL);
Fx3UtilDelayUs(1);
Fx3SetReg32(FX3_DEV_CS, FX3_DEV_CS_SETUP_CLR_BUSY);
}
}
void Fx3UsbDmaDataOut(uint8_t ep, volatile void *buffer, uint16_t length)
{
uint16_t d = Fx3DmaAllocateDescriptor();
Fx3DmaSimpleTransferWrite(FX3_UIBIN_DMA_SCK(ep), d, buffer, length);
Fx3DmaFreeDescriptor(d);
}
void Fx3UsbDmaDataIn(uint8_t ep, const volatile void *buffer, uint16_t length)
{
uint16_t d = Fx3DmaAllocateDescriptor();
Fx3DmaSimpleTransferRead(FX3_UIB_DMA_SCK(ep), d, buffer, length);
Fx3DmaFreeDescriptor(d);
}
static void Fx3UsbUsbCoreIsr(void)
{
uint32_t req = Fx3ReadReg32(FX3_UIB_INTR) & Fx3ReadReg32(FX3_UIB_INTR_MASK);
Fx3WriteReg32(FX3_UIB_INTR, req);
Fx3UartTxString("Fx3UsbUsbCoreIsr\n");
if (req & FX3_UIB_INTR_PROT_INT) {
Fx3UartTxString(" PROT\n");
uint32_t prot_req =
Fx3ReadReg32(FX3_PROT_INTR) & Fx3ReadReg32(FX3_PROT_INTR_MASK);
Fx3WriteReg32(FX3_PROT_INTR, prot_req);
if (prot_req & FX3_PROT_INTR_STATUS_STAGE) {
Fx3UartTxString(" STATUS_STAGE\n");
}
if (prot_req & FX3_PROT_INTR_SUTOK_EV) {
Fx3UartTxString(" SUTOK_EV\n");
Fx3WriteReg32(FX3_PROT_EPO_CS1 + 0, FX3_PROT_EPO_CS1_VALID);
Fx3WriteReg32(FX3_PROT_EPI_CS1 + 0, FX3_PROT_EPI_CS1_VALID);
Fx3DmaAbortSocket(FX3_UIB_DMA_SCK(0));
Fx3DmaAbortSocket(FX3_UIBIN_DMA_SCK(0));
Fx3SetReg32(FX3_EEPM_ENDPOINT, FX3_EEPM_ENDPOINT_SOCKET_FLUSH);
Fx3UtilDelayUs(10);
Fx3ClearReg32(FX3_EEPM_ENDPOINT, FX3_EEPM_ENDPOINT_SOCKET_FLUSH);
uint32_t sudat0 = Fx3ReadReg32(FX3_PROT_SETUP_DAT+0);
uint32_t sudat1 = Fx3ReadReg32(FX3_PROT_SETUP_DAT+4);
uint8_t req_type = sudat0 >> FX3_PROT_SETUP_DAT_SETUP_REQUEST_TYPE_SHIFT;
uint16_t length = sudat1 >> (FX3_PROT_SETUP_DAT_SETUP_LENGTH_SHIFT - 32);
if ((req_type & FX3_USB_REQTYPE_DIR_MASK) == FX3_USB_REQTYPE_IN)
/* IN transfer */
Fx3WriteReg32(FX3_DEV_EPI_XFER_CNT, length);
else
/* OUT transfer */
Fx3WriteReg32(FX3_DEV_EPO_XFER_CNT, length);
(*Fx3UsbUserCallbacks->sutok)
(req_type, sudat0 >> FX3_PROT_SETUP_DAT_SETUP_REQUEST_SHIFT,
sudat0 >> FX3_PROT_SETUP_DAT_SETUP_VALUE_SHIFT,
sudat1 >> (FX3_PROT_SETUP_DAT_SETUP_INDEX_SHIFT - 32),
length, FX3_USB_SUPER_SPEED);
}
if (prot_req & FX3_PROT_INTR_TIMEOUT_PORT_CFG_EV) {
Fx3UartTxString(" TIMEOUT_PORT_CFG_EV\n");
}
if (prot_req & FX3_PROT_INTR_TIMEOUT_PORT_CAP_EV) {
Fx3UartTxString(" TIMEOUT_PORT_CAP_EV\n");
}
if (prot_req & FX3_PROT_INTR_LMP_PORT_CFG_EV) {
Fx3UartTxString(" LMP_PORT_CFG_EV\n");
/* Disable timeout */
Fx3WriteReg32(FX3_PROT_LMP_PORT_CONFIGURATION_TIMER, 0x80008000UL);
Fx3WriteReg32(FX3_PROT_INTR, FX3_PROT_INTR_TIMEOUT_PORT_CFG_EV);
}
if (prot_req & FX3_PROT_INTR_LMP_PORT_CAP_EV) {
Fx3UartTxString(" LMP_PORT_CAP_EV\n");
/* Disable timeout */
Fx3WriteReg32(FX3_PROT_LMP_PORT_CAPABILITY_TIMER, 0x80008000UL);
Fx3WriteReg32(FX3_PROT_INTR, FX3_PROT_INTR_TIMEOUT_PORT_CAP_EV);
}
if (prot_req & FX3_PROT_INTR_LMP_RCV_EV) {
Fx3UartTxString(" LMP_RCV_EV\n");
}
}
if (req & FX3_UIB_INTR_LNK_INT) {
Fx3UartTxString(" LNK\n");
uint32_t lnk_req =
Fx3ReadReg32(FX3_LNK_INTR) & Fx3ReadReg32(FX3_LNK_INTR_MASK);
Fx3WriteReg32(FX3_LNK_INTR, lnk_req);
if (lnk_req & FX3_LNK_INTR_LTSSM_RESET) {
Fx3UartTxString(" LTSSM_RESET\n");
}
if (lnk_req & FX3_LNK_INTR_LTSSM_DISCONNECT) {
Fx3UartTxString(" LTSSM_DISCONNECT\n");
Fx3UsbConnectHighSpeed();
}
if (lnk_req & FX3_LNK_INTR_LTSSM_CONNECT) {
Fx3UartTxString(" LTSSM_CONNECT\n");
Fx3UsbConnectSuperSpeed();
}
if (lnk_req & FX3_LNK_INTR_LGO_U3) {
Fx3UartTxString(" LGO_U3\n");
}
if (lnk_req & FX3_LNK_INTR_LTSSM_STATE_CHG) {
Fx3UartTxString(" LTSSM_STATE_CHG %u\n");
}
}
if (req & FX3_UIB_INTR_DEV_CTL_INT) {
Fx3UartTxString(" DEV_CTL\n");
uint32_t dev_ctrl_req;
dev_ctrl_req = Fx3ReadReg32(FX3_DEV_CTRL_INTR) & Fx3ReadReg32(FX3_DEV_CTRL_INTR_MASK);
Fx3WriteReg32(FX3_DEV_CTRL_INTR, dev_ctrl_req);
if (dev_ctrl_req & (1UL << 8))
{
Fx3WriteReg32(FX3_DEV_CTRL_INTR, (1UL << 8));
Fx3UartTxString(" resume\n");
Fx3SetReg32(FX3_DEV_CTRL_INTR_MASK, (1UL << 8));
}
if (dev_ctrl_req & (1UL << 2))
{
Fx3WriteReg32(FX3_DEV_CTRL_INTR, (1UL << 2));
Fx3UartTxString(" suspend\n");
Fx3SetReg32(FX3_DEV_CTRL_INTR_MASK, (1UL << 2));
}
if (dev_ctrl_req & (1UL << 3))
{
Fx3WriteReg32(FX3_DEV_CTRL_INTR, (1UL << 3));
Fx3UartTxString(" reset\n");
Fx3SetReg32(FX3_DEV_CTRL_INTR_MASK, (1UL << 3));
}
if (dev_ctrl_req & (1UL << 4))
{
Fx3WriteReg32(FX3_DEV_CTRL_INTR, (1UL << 4));
Fx3UartTxString(" hsgrant\n");
Fx3SetReg32(FX3_DEV_CTRL_INTR_MASK, (1UL << 4));
}
if (dev_ctrl_req & (1UL << 11))
{
Fx3WriteReg32(FX3_DEV_CTRL_INTR, (1UL << 11));
Fx3UartTxString(" status\n");
Fx3SetReg32(FX3_DEV_CTRL_INTR_MASK, (1UL << 11));
}
if (dev_ctrl_req & (1UL << 6))
{
Fx3WriteReg32(FX3_DEV_CTRL_INTR, (1UL << 6));
Fx3UartTxString(" sudav\n");
Fx3WriteReg32(FX3_DEV_EPO_CS + 0, FX3_DEV_EPO_CS_VALID);
Fx3WriteReg32(FX3_DEV_EPI_CS + 0, FX3_DEV_EPI_CS_VALID);
Fx3DmaAbortSocket(FX3_UIB_DMA_SCK(0));
Fx3DmaAbortSocket(FX3_UIBIN_DMA_SCK(0));
Fx3SetReg32(FX3_EEPM_ENDPOINT, FX3_EEPM_ENDPOINT_SOCKET_FLUSH);
Fx3UtilDelayUs(10);
Fx3ClearReg32(FX3_EEPM_ENDPOINT, FX3_EEPM_ENDPOINT_SOCKET_FLUSH);
uint32_t setupdat0;
uint32_t setupdat1;
setupdat0 = Fx3ReadReg32(FX3_DEV_SETUPDAT+0);
setupdat1 = Fx3ReadReg32(FX3_DEV_SETUPDAT+4);
uint8_t req_type = setupdat0 >> 0;
uint16_t length = setupdat1 >> (48 - 32);
if ((req_type & FX3_USB_REQTYPE_DIR_MASK) == FX3_USB_REQTYPE_IN)
/* IN transfer */
Fx3WriteReg32(FX3_DEV_EPI_XFER_CNT, length);
else
/* OUT transfer */
Fx3WriteReg32(FX3_DEV_EPO_XFER_CNT, length);
(*Fx3UsbUserCallbacks->sutok)
(req_type, setupdat0 >> FX3_PROT_SETUP_DAT_SETUP_REQUEST_SHIFT,
setupdat0 >> FX3_PROT_SETUP_DAT_SETUP_VALUE_SHIFT,
setupdat1 >> (FX3_PROT_SETUP_DAT_SETUP_INDEX_SHIFT - 32),
length, FX3_USB_HIGH_SPEED);
}
if (dev_ctrl_req & (1UL << 7))
{
Fx3WriteReg32(FX3_DEV_CTRL_INTR, (1UL << 7));
Fx3SetReg32(FX3_DEV_CTRL_INTR_MASK, (1UL << 7));
}
}
Fx3WriteReg32(FX3_VIC_ADDRESS, 0);
}
static void Fx3UsbGctlCoreIsr(void)
{
uint32_t req = Fx3ReadReg32(FX3_GCTL_WAKEUP_EVENT) & Fx3ReadReg32(FX3_GCTL_WAKEUP_EN);
Fx3WriteReg32(FX3_GCTL_WAKEUP_EVENT, req);
Fx3UartTxString("Fx3UsbGctlCoreIsr\n");
Fx3WriteReg32(FX3_VIC_ADDRESS, 0);
}
static void Fx3UsbGctlPowerIsr(void)
{
uint32_t req = Fx3ReadReg32(FX3_GCTL_IOPOWER_INTR) & Fx3ReadReg32(FX3_GCTL_IOPOWER_INTR_MASK);
Fx3WriteReg32(FX3_GCTL_IOPOWER_INTR, req);
Fx3UartTxString("Fx3UsbGctlPowerIsr\n");
if (req & FX3_GCTL_IOPOWER_INTR_VBUS) {
Fx3UartTxString(" VBUS\n");
}
Fx3WriteReg32(FX3_VIC_ADDRESS, 0);
}
void Fx3UsbInit(const struct Fx3UsbCallbacks *callbacks)
{
Fx3UsbUserCallbacks = callbacks;
/* Select bus clock */
Fx3ClearReg32(FX3_GCTL_UIB_CORE_CLK, FX3_GCTL_UIB_CORE_CLK_CLK_EN);
Fx3UtilDelayUs(5);
Fx3WriteReg32(FX3_GCTL_UIB_CORE_CLK,
(2UL << FX3_GCTL_UIB_CORE_CLK_PCLK_SRC_SHIFT) |
(2UL << FX3_GCTL_UIB_CORE_CLK_EPMCLK_SRC_SHIFT));
Fx3SetReg32(FX3_GCTL_UIB_CORE_CLK, FX3_GCTL_UIB_CORE_CLK_CLK_EN);
Fx3UtilDelayUs(5);
Fx3WriteReg32(FX3_GCTL_CONTROL,
FX3_GCTL_CONTROL_HARD_RESET_N |
FX3_GCTL_CONTROL_CPU_RESET_N |
FX3_GCTL_CONTROL_BOOTROM_EN |
(1UL<<27) |
FX3_GCTL_CONTROL_MAIN_POWER_EN |
FX3_GCTL_CONTROL_MAIN_CLOCK_EN |
FX3_GCTL_CONTROL_WAKEUP_CPU_INT |
FX3_GCTL_CONTROL_WAKEUP_CLK |
FX3_GCTL_CONTROL_POR);
/* Reset USB */
Fx3ClearReg32(FX3_UIB_POWER, FX3_UIB_POWER_RESETN);
Fx3UtilDelayUs(50);
Fx3SetReg32(FX3_UIB_POWER, FX3_UIB_POWER_RESETN);
Fx3UtilDelayUs(100);
while((Fx3ReadReg32(FX3_UIB_POWER) & FX3_UIB_POWER_ACTIVE) == 0)
;
Fx3WriteReg32(FX3_OTG_CTRL, 0);
Fx3WriteReg32(FX3_PHY_CLK_AND_TEST,
(1UL<<31) |
FX3_PHY_CLK_AND_TEST_SUSPEND_N |
FX3_PHY_CLK_AND_TEST_VLOAD |
FX3_PHY_CLK_AND_TEST_DATABUS16_8);
Fx3SetReg32(FX3_DEV_PWR_CS, FX3_DEV_PWR_CS_DISCON);
Fx3WriteReg32(FX3_GCTL_WAKEUP_EN, 0);
Fx3WriteReg32(FX3_GCTL_WAKEUP_POLARITY, 0);
Fx3WriteReg32(FX3_LNK_PHY_CONF,
FX3_LNK_PHY_CONF_RX_TERMINATION_ENABLE |
FX3_LNK_PHY_CONF_RX_TERMINATION_OVR_VAL |
FX3_LNK_PHY_CONF_RX_TERMINATION_OVR |
(1UL << FX3_LNK_PHY_CONF_PHY_MODE_SHIFT));
Fx3WriteReg32(FX3_LNK_ERROR_CONF, ~0UL);
Fx3WriteReg32(FX3_LNK_INTR, ~0UL);
Fx3WriteReg32(FX3_LNK_INTR_MASK,
FX3_LNK_INTR_MASK_LTSSM_RESET |
FX3_LNK_INTR_MASK_LTSSM_DISCONNECT |
FX3_LNK_INTR_MASK_LTSSM_CONNECT |
FX3_LNK_INTR_MASK_LGO_U3 |
FX3_LNK_INTR_MASK_LTSSM_STATE_CHG);
Fx3WriteReg32(FX3_PROT_EP_INTR_MASK, 0);
Fx3WriteReg32(FX3_PROT_INTR, ~0UL);
Fx3WriteReg32(FX3_PROT_INTR_MASK,
FX3_PROT_INTR_MASK_STATUS_STAGE |
FX3_PROT_INTR_MASK_SUTOK_EN |
FX3_PROT_INTR_MASK_TIMEOUT_PORT_CFG_EN |
FX3_PROT_INTR_MASK_TIMEOUT_PORT_CAP_EN |
FX3_PROT_INTR_MASK_LMP_PORT_CFG_EN |
FX3_PROT_INTR_MASK_LMP_PORT_CAP_EN |
FX3_PROT_INTR_MASK_LMP_RCV_EN);
Fx3WriteReg32(FX3_PHY_CONF,
FX3_PHY_CONF_PREEMDEPTH |
FX3_PHY_CONF_ENPRE |
(1UL << FX3_PHY_CONF_FSRFTSEL_SHIFT) |
(1UL << FX3_PHY_CONF_LSRFTSEL_SHIFT) |
(2UL << FX3_PHY_CONF_HSTEDVSEL_SHIFT) |
(4UL << FX3_PHY_CONF_FSTUNEVSEL_SHIFT) |
(2UL << FX3_PHY_CONF_HSDEDVSEL_SHIFT) |
(4UL << FX3_PHY_CONF_HSDRVSLOPE_SHIFT));
Fx3WriteReg32(FX3_DEV_CTRL_INTR, ~0UL);
Fx3WriteReg32(FX3_DEV_CTRL_INTR_MASK,
FX3_DEV_CTRL_INTR_MASK_URESUME |
FX3_DEV_CTRL_INTR_MASK_SUDAV |
FX3_DEV_CTRL_INTR_MASK_HSGRANT |
FX3_DEV_CTRL_INTR_MASK_URESET |
FX3_DEV_CTRL_INTR_MASK_SUSP);
Fx3WriteReg32(FX3_DEV_EP_INTR, ~0UL);
Fx3WriteReg32(FX3_DEV_EP_INTR_MASK, 0);
/* USB3 EP0 valid as control */
Fx3WriteReg32(FX3_PROT_EPO_CS1+0, FX3_PROT_EPO_CS1_VALID);
Fx3WriteReg32(FX3_PROT_EPI_CS1+0, FX3_PROT_EPI_CS1_VALID);
Fx3WriteReg32(FX3_PROT_EPO_CS2+0,
(16UL << FX3_PROT_EPO_CS2_ISOINPKS_SHIFT) |
(3UL << FX3_PROT_EPO_CS2_TYPE_SHIFT));
Fx3WriteReg32(FX3_PROT_EPI_CS2+0,
(16UL << FX3_PROT_EPI_CS2_ISOINPKS_SHIFT) |
(3UL << FX3_PROT_EPI_CS2_TYPE_SHIFT));
/* USB2 EP0 valid as control */
Fx3WriteReg32(FX3_DEV_EPI_CS+0,
FX3_DEV_EPI_CS_VALID |
(0UL << FX3_DEV_EPI_CS_TYPE_SHIFT) |
(64UL << FX3_DEV_EPI_CS_PAYLOAD_SHIFT));
Fx3WriteReg32(FX3_DEV_EPO_CS+0,
FX3_DEV_EPO_CS_VALID |
(0UL << FX3_DEV_EPO_CS_TYPE_SHIFT) |
(64UL << FX3_DEV_EPO_CS_PAYLOAD_SHIFT));
/* Endpoint manager settings for EP0 */
Fx3WriteReg32(FX3_EEPM_ENDPOINT+0,
(64UL << FX3_EEPM_ENDPOINT_PACKET_SIZE_SHIFT));
Fx3WriteReg32(FX3_IEPM_ENDPOINT+0,
(64UL << FX3_IEPM_ENDPOINT_PACKET_SIZE_SHIFT));
/* Invalidate all other EPs */
unsigned i;
for (i=1; i<16; i++) {
Fx3ClearReg32(FX3_DEV_EPO_CS + (i<<2), FX3_DEV_EPO_CS_VALID);
Fx3WriteReg32(FX3_PROT_EPO_CS1 + (i<<2), 0);
Fx3ClearReg32(FX3_DEV_EPI_CS + (i<<2), FX3_DEV_EPI_CS_VALID);
Fx3WriteReg32(FX3_PROT_EPI_CS1 + (i<<2), 0);
}
Fx3WriteReg32(FX3_UIB_INTR_MASK, 0);
/* Configure vectored interrupt controller */
Fx3WriteReg32(FX3_VIC_VEC_ADDRESS + (FX3_IRQ_GCTL_CORE<<2), Fx3UsbGctlCoreIsr);
Fx3WriteReg32(FX3_VIC_VEC_ADDRESS + (FX3_IRQ_USB_CORE<<2), Fx3UsbUsbCoreIsr);
Fx3WriteReg32(FX3_VIC_VEC_ADDRESS + (FX3_IRQ_GCTL_POWER<<2), Fx3UsbGctlPowerIsr);
Fx3WriteReg32(FX3_VIC_INT_CLEAR,
(1UL << FX3_IRQ_GCTL_POWER) | (1UL << FX3_IRQ_USB_CORE) | (1UL << FX3_IRQ_GCTL_CORE));
}
void Fx3UsbEnableInEndpoint(uint8_t ep, Fx3UsbEndpointType_t type, uint16_t pktsize)
{
static const uint8_t usb2_type_map[] = {
[FX3_USB_EP_ISOCHRONOUS] = 1,
[FX3_USB_EP_INTERRUPT] = 3,
[FX3_USB_EP_BULK] = 2,
[FX3_USB_EP_CONTROL] = 0,
};
/* USB3 EP valid */
Fx3WriteReg32(FX3_PROT_EPI_CS1+(ep<<2), FX3_PROT_EPI_CS1_VALID);
Fx3WriteReg32(FX3_PROT_EPI_CS2+(ep<<2),
(16UL << FX3_PROT_EPI_CS2_ISOINPKS_SHIFT) |
((type << FX3_PROT_EPI_CS2_TYPE_SHIFT) & FX3_PROT_EPI_CS2_TYPE_MASK));
/* USB2 EP valid */
Fx3WriteReg32(FX3_DEV_EPI_CS+(ep<<2),
FX3_DEV_EPI_CS_VALID |
(usb2_type_map[type&3] << FX3_DEV_EPI_CS_TYPE_SHIFT) |
((pktsize << FX3_DEV_EPI_CS_PAYLOAD_SHIFT) & FX3_DEV_EPI_CS_PAYLOAD_MASK));
/* Endpoint manager settings for EP */
Fx3WriteReg32(FX3_EEPM_ENDPOINT+(ep<<2),
(pktsize << FX3_EEPM_ENDPOINT_PACKET_SIZE_SHIFT)
& FX3_EEPM_ENDPOINT_PACKET_SIZE_MASK);
}
void Fx3UsbFlushInEndpoint(uint8_t ep)
{
Fx3SetReg32(FX3_EEPM_ENDPOINT+(ep<<2), FX3_EEPM_ENDPOINT_SOCKET_FLUSH);
Fx3UtilDelayUs(5);
Fx3ClearReg32(FX3_EEPM_ENDPOINT+(ep<<2), FX3_EEPM_ENDPOINT_SOCKET_FLUSH);
}

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/*
* Copyright (C) 2018 Marcus Comstedt
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef BSP_USB_H_
#define BSP_USB_H_
#include <stdint.h>
#define FX3_USB_REQTYPE_DIR_MASK 0x80
#define FX3_USB_REQTYPE_OUT 0x00
#define FX3_USB_REQTYPE_IN 0x80
#define FX3_USB_REQTYPE_TYPE_MASK 0x60
#define FX3_USB_REQTYPE_TYPE_STD 0x00
#define FX3_USB_REQTYPE_TYPE_CLASS 0x20
#define FX3_USB_REQTYPE_TYPE_VENDOR 0x40
#define FX3_USB_REQTYPE_TGT_MASK 0x1F
#define FX3_USB_REQTYPE_TGT_DEVICE 0x00
#define FX3_USB_REQTYPE_TGT_INTERFC 0x01
#define FX3_USB_REQTYPE_TGT_EP 0x02
#define FX3_USB_REQTYPE_TGT_OTHER 0x03
#define FX3_USB_STD_REQUEST_GET_STATUS 0x00
#define FX3_USB_STD_REQUEST_CLEAR_FEATURE 0x01
#define FX3_USB_STD_REQUEST_SET_FEATURE 0x03
#define FX3_USB_STD_REQUEST_SET_ADDRESS 0x05
#define FX3_USB_STD_REQUEST_GET_DESCRIPTOR 0x06
#define FX3_USB_STD_REQUEST_SET_DESCRIPTOR 0x07
#define FX3_USB_STD_REQUEST_GET_CONFIGURATION 0x08
#define FX3_USB_STD_REQUEST_SET_CONFIGURATION 0x09
#define FX3_USB_STD_REQUEST_GET_INTERFACE 0x0A
#define FX3_USB_STD_REQUEST_SET_INTERFACE 0x0B
#define FX3_USB_STD_REQUEST_SYNCH_FRAME 0x0C
#define FX3_USB_DESCRIPTOR_DEVICE 0x01
#define FX3_USB_DESCRIPTOR_CONFIGURATION 0x02
#define FX3_USB_DESCRIPTOR_STRING 0x03
#define FX3_USB_DESCRIPTOR_INTERFACE 0x04
#define FX3_USB_DESCRIPTOR_ENDPOINT 0x05
#define FX3_USB_DESCRIPTOR_DEVICE_QUALIFIER 0x06
#define FX3_USB_DESCRIPTOR_OTHER_SPEED_CONFIG 0x07
#define FX3_USB_DESCRIPTOR_INTERFACE_POWER 0x08
#define FX3_USB_DESCRIPTOR_OTG 0x09
#define FX3_USB_DESCRIPTOR_DEBUG 0x0A
#define FX3_USB_DESCRIPTOR_INTERFACE_ASSOC 0x0B
#define FX3_USB_DESCRIPTOR_BOS 0x0F
#define FX3_USB_DESCRIPTOR_DEV_CAPABILITY 0x10
#define FX3_USB_DESCRIPTOR_SS_EP_COMPANION 0x30
typedef enum {
FX3_USB_EP_ISOCHRONOUS = 0,
FX3_USB_EP_INTERRUPT,
FX3_USB_EP_BULK,
FX3_USB_EP_CONTROL,
} Fx3UsbEndpointType_t;
typedef enum {
FX3_USB_HIGH_SPEED = 0,
FX3_USB_SUPER_SPEED,
} Fx3UsbSpeed_t;
struct Fx3UsbCallbacks {
void (*sutok)(uint8_t request_type, uint8_t request, uint16_t value,
uint16_t index, uint16_t length, Fx3UsbSpeed_t s);
};
extern void Fx3UsbInit(const struct Fx3UsbCallbacks *callbacks);
extern void Fx3UsbConnect(void);
extern void Fx3UsbStallEp0(Fx3UsbSpeed_t s);
extern void Fx3UsbUnstallEp0(Fx3UsbSpeed_t s);
extern void Fx3UsbDmaDataOut(uint8_t ep, volatile void *buffer,
uint16_t length);
extern void Fx3UsbDmaDataIn(uint8_t ep, const volatile void *buffer,
uint16_t length);
extern void Fx3UsbEnableInEndpoint(uint8_t ep, Fx3UsbEndpointType_t type,
uint16_t pktsize);
extern void Fx3UsbFlushInEndpoint(uint8_t ep);
#endif /* BSP_USB_H_ */

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/*
* Copyright (C) 2018 Marcus Comstedt
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include <bsp/util.h>
#include <bsp/gctl.h>
#include <errno.h>
void Fx3UtilDelayUs(uint32_t delay_us)
{
/* Each loop is 4 instruction cycles */
uint32_t cnt = delay_us * (CPU_CLK / 4 / 1000000);
__asm__ __volatile__("1: subs %0,%0,#1; bcs 1b" : "=r"(cnt) : "0"(cnt) : "cc");
}
void exit(int status)
{
(void)status;
Fx3GctlHardReset();
for(;;)
;
}
void *_sbrk(intptr_t increment)
{
extern char _end[];
extern char __heap_end[];
static void *current_brk = _end;
if (increment > __heap_end - (char *)current_brk) {
errno = ENOMEM;
return (void *)-1;
}
void *ret = current_brk;
current_brk = increment + (char *)current_brk;
return ret;
}

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/*
* Copyright (C) 2018 Marcus Comstedt
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef BSP_UTIL_H_
#define BSP_UTIL_H_
#include <stdint.h>
extern void Fx3UtilDelayUs(uint32_t delay_us);
#endif /* BSP_UTIL_H_ */

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/*
* Copyright (C) 2018 Marcus Comstedt
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#define DTCM_BASE 0x10000000
#define DTCM_SIZE 4 /* 512 << 4 = 8K */
#define ITCM_BASE 0x00000000
#define ITCM_SIZE 5 /* 512 << 5 = 16K */
.text
.globl Fx3IrqInstallVectors, _start
Fx3IrqVectors:
_start:
1: ldr pc, ._reset /* Reset */
1: b 1b /* Undefined */
1: b 1b /* Swi */
1: b 1b /* Prefetch */
1: b 1b /* Abort */
1: b 1b /* Reserved */
ldr pc, Fx3IrqVectors - 0x100 /* IRQ - use vectored address */
1: b 1b /* FIQ */
._reset:
.word Reset
Fx3IrqInstallVectors:
mov a1, #0
adr a2, Fx3IrqVectors
adr a3, Fx3IrqInstallVectors
sub a3, a3, a2
b memcpy
Reset:
msr CPSR_c, #0xD1 /* FIRQ mode, interrupts disabled */
/* Enable TCM */
mov r0, #DTCM_BASE
orr r0, r0, #((DTCM_SIZE << 2) | 1)
mcr p15, 0, r0, c9, c1, 0
mov r0, #ITCM_BASE
orr r0, r0, #((ITCM_SIZE << 2) | 1)
mcr p15, 0, r0, c9, c1, 1
ldr sp, =__stack_firq-8
msr CPSR_c, #0xD7 /* Abort mode, interrupts disabled */
ldr sp, =__stack_abort-8
msr CPSR_c, #0xDB /* Undefined mode, interrupts disabled */
ldr sp, =__stack_undef-8
msr CPSR_c, #0xD2 /* IRQ mode, interrupts disabled */
ldr sp, =__stack_irq-8
msr CPSR_c, #0xD3 /* Supervisory mode, interrupts disabled */
ldr sp, =__stack_super-8
msr CPSR_c, #0xDF /* System mode, interrupts disabled */
ldr sp, =__stack_sys-8
/* Zero the memory in the .bss section. */
movs a2, #0 /* Second arg: fill value */
mov fp, a2 /* Null frame pointer */
mov r7, a2 /* Null frame pointer for Thumb */
ldr a1, =__bss_start__ /* First arg: start of memory block */
ldr a3, =__bss_end__
subs a3, a3, a1 /* Third arg: length of block */
bl memset
mov r0, #0
mov r1, #0
bl main
b exit
.end

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#!/usr/bin/env python3
# Copyright (C) 2018 Marcus Comstedt
#
# Permission is hereby granted, free of charge, to any person obtaining
# a copy of this software and associated documentation files (the
# "Software"), to deal in the Software without restriction, including
# without limitation the rights to use, copy, modify, merge, publish,
# distribute, sublicense, and/or sell copies of the Software, and to
# permit persons to whom the Software is furnished to do so, subject to
# the following conditions:
#
# The above copyright notice and this permission notice shall be
# included in all copies or substantial portions of the Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
# IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
# CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
# TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
# SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
import sys
import struct
class elf:
def read_struct(this, struct_fmt, struct_fields):
fmt = this.elf_endianprefix+str.translate(struct_fmt, this.elf_format);
fields = struct.unpack(fmt, this.file.read(struct.calcsize(fmt)))
return dict(zip(struct_fields, fields))
def read_ehdr(this):
return this.read_struct('16sHHWNNNWHHHHHH',
('e_ident', 'e_type', 'e_machine', 'e_version',
'e_entry', 'e_phoff', 'e_shoff', 'e_flags',
'e_ehsize', 'e_phentsize', 'e_phnum',
'e_shentsize', 'e_shnum', 'e_shstrndx'))
def read_phdr(this):
if this.elf_wordsize == 64:
return this.read_struct('WWNNNXXX',
('p_type', 'p_flags', 'p_offset', 'p_vaddr',
'p_paddr', 'p_filesz', 'p_memsz', 'p_align'))
else:
return this.read_struct('WNNNWWWW',
('p_type', 'p_offset', 'p_vaddr', 'p_paddr',
'p_filesz', 'p_memsz', 'p_flags', 'p_align'))
def __init__(this, filename):
this.file = open(filename, 'rb')
magic = this.file.read(16)
if magic[:4] != b'\x7fELF':
raise Exception("ELF signature not found")
if magic[4] == 1:
this.elf_wordsize = 32
nativeint = 'Ii'
elif magic[4] == 2:
this.elf_wordsize = 64
nativeint = 'Qq'
else:
raise Exception("Invalid ELF file class")
if magic[5] == 1:
this.elf_endianprefix = '<'
elif magic[5] == 2:
this.elf_endianprefix = '>'
else:
raise Exception("Invalid ELF data encoding")
this.elf_format = str.maketrans('HWwXxNn', 'HIiQq'+nativeint)
this.file.seek(0)
this.ehdr = this.read_ehdr()
this.file.seek(this.ehdr['e_phoff'])
this.phdrs = [this.read_phdr() for i in range(this.ehdr['e_phnum'])]
def copy_segment(phdr, infile, outfile):
checksum = 0
infile.seek(phdr['p_offset'])
filesz = phdr['p_filesz']
memsz = phdr['p_memsz']
if (filesz > memsz):
print("Warning: File size larger than mem size, fixing...")
memsz = filesz
if (memsz & 3) != 0:
print("Warning: Unaligned memsize of segment, padding...")
memsz = (memsz + 3) & ~3
vaddr = phdr['p_vaddr']
while (memsz > 0):
chunksz = 65536 if memsz > 65536 else memsz
outfile.write(struct.pack('<2I', chunksz >> 2, vaddr))
vaddr += chunksz
memsz -= chunksz
while chunksz > 0:
slicesz = 8192 if chunksz > 8192 else chunksz
if filesz > 0:
readsz = slicesz if filesz > slicesz else filesz
block = infile.read(readsz)
if len(block) == 0:
print("Warning: EOF on reading input ELF")
filesz = 0
else:
filesz -= len(block)
else:
block = b''
if filesz == 0 and len(block) < slicesz:
block += b'\0' * (slicesz - len(block))
checksum += sum(struct.unpack('<%dI'%(len(block) >> 2), block))
outfile.write(block)
chunksz -= len(block)
return checksum
def usage():
print("elf2img.py <elffile> <imgfile>")
sys.exit(1)
#
# main
#
if len(sys.argv) != 3:
usage()
elf_filename = sys.argv[1]
img_filename = sys.argv[2]
# TODO: add flags and ELF NOTE parsing for these -sys64738
i2c_config = 0x1c
image_type = 0xb0
checksum = 0
e = elf(elf_filename)
i = open(img_filename, 'wb')
i.write(struct.pack('<4B', ord(b'C'), ord(b'Y'), i2c_config, image_type))
for p in e.phdrs:
if p['p_type'] == 1:
checksum += copy_segment(p, e.file, i)
i.write(struct.pack('<3I', 0, e.ehdr['e_entry'], checksum & 0xffffffff))
i.close()

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#include <bsp/gctl.h>
#include <bsp/gpio.h>
#include <bsp/uart.h>
#include <bsp/usb.h>
#include <bsp/irq.h>
#include <bsp/cache.h>
#include <bsp/util.h>
#include <stddef.h>
#include <stdint.h>
#include <stdbool.h>
#include <stdio.h>
#include <string.h>
static uint8_t bytecode[] = {
0x05, // iconst_2
0x05, // iconst_2
0x60, // iadd
0xAC, // ireturn
};
__attribute__((__aligned__(1024)))
static struct {
void* handlers[512];
uint8_t stack[256];
uint8_t locals[256];
} jazelle_block;
static void handler_ireturn(void) {
int32_t result;
asm volatile(
"ldr %[res], [r6, #-4]!\n"
"bkpt #1\n"
:[res]"=r"(result)
);
while (true); // a
}
static void jazelle_exec(const uint8_t* bytecode) {
jazelle_block.handlers[0xAC] = handler_ireturn;
const void* block = &jazelle_block;
asm volatile(
"push {lr}\n"
// set configuration valid & jazelle enable bits
"mov r0, #2\n"
"mcr p14, 7, r0, c1, c0, 0\n"
"mov r0, #1\n"
"mcr p14, 7, r0, c2, c0, 0\n"
"mov lr, %[bc]\n"
// init handler table pointer and stack pointer
"mov r5, %[blk]\n"
"add r6, r5, #0x800\n"
"add r7, r5, #0x900\n"
// switch to jazelle mode
"adr r12, .Lno_jazelle\n"
"bxj r12\n"
"bkpt #0\n"
"b .Lend\n"
".Lno_jazelle:\n"
"mov r0, #0\n"
"mcr p14, 7, r0, c1, c0, 0\n"
"mcr p14, 7, r0, c2, c0, 0\n"
"bkpt #2\n"
".Lend:\n"
"pop {lr}\n"
:
:[bc]"r"(bytecode),[blk]"r"(block)
:"r0","r12","r5","r6","r7","memory");
}
int main(void)
{
Fx3CacheEnableCaches();
Fx3IrqInit();
Fx3GctlInitClock();
*(volatile uint32_t *)(void *)0x400020e8 = 0;
Fx3GctlInitIoMatrix(FX3_GCTL_ALTFUNC_GPIF32BIT_UART_I2S);
/*Fx3UartInit(115200, FX3_UART_NO_PARITY, FX3_UART_1_STOP_BIT);
Fx3UartTxString("\nhello world\n");
Fx3UartTxFlush();
Fx3GpioInitClock();
Fx3GpioSetupSimple(45,
FX3_GPIO_SIMPLE_ENABLE |
FX3_GPIO_SIMPLE_INPUT_EN);
Fx3GpioSetupSimple(54,
FX3_GPIO_SIMPLE_ENABLE |
FX3_GPIO_SIMPLE_DRIVE_HI_EN |
FX3_GPIO_SIMPLE_DRIVE_LO_EN);
Fx3GpioSetupComplex(50,
FX3_PIN_STATUS_ENABLE |
(FX3_GPIO_TIMER_MODE_SLOW_CLK << FX3_PIN_STATUS_TIMER_MODE_SHIFT) |
(FX3_GPIO_PIN_MODE_PWM << FX3_PIN_STATUS_MODE_SHIFT) |
FX3_PIN_STATUS_DRIVE_HI_EN |
FX3_PIN_STATUS_DRIVE_LO_EN,
0, GPIO_SLOW_CLK/1000-1, GPIO_SLOW_CLK/2000);
Fx3IrqEnableInterrupts();*/
jazelle_exec(bytecode);
while (true) ; // a
}
/* Newlib's assert() calls this function if the assertion fails */
void
__assert_func (const char *file,
int line,
const char *func,
const char *failedexpr)
{
if (file != NULL) {
char linestrbuf[16], *linestr = &linestrbuf[sizeof(linestrbuf)];
Fx3UartTxString(file);
Fx3UartTxChar(':');
/* Avoid using newlib functions like itoa so as not to trigger
a recursive assert... */
*--linestr = '\0';
while (line >= 10 && linestr != &linestrbuf[1]) {
*--linestr = '0' + (line % 10);
line /= 10;
}
*--linestr = '0' + line;
Fx3UartTxString(linestr);
Fx3UartTxString(": ");
}
if (func != NULL) {
Fx3UartTxString(func);
Fx3UartTxString(": ");
}
Fx3UartTxString("Assertion ");
if (failedexpr != NULL) {
Fx3UartTxChar('`');
Fx3UartTxString(failedexpr);
Fx3UartTxString("' ");
}
Fx3UartTxString("failed.\n");
for(;;)
;
}

354
rdb/dma.h Normal file
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@ -0,0 +1,354 @@
/*
* Copyright (C) 2018 Marcus Comstedt
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef RDB_DMA_H_
#define RDB_DMA_H_
#define FX3_SCK_DSCR 0x00 /* Descriptor Chain Pointer */
#define FX3_SCK_SIZE 0x04 /* Transfer Size Register */
#define FX3_SCK_COUNT 0x08 /* Transfer Count Register */
#define FX3_SCK_STATUS 0x0C /* Socket Status Register */
#define FX3_SCK_INTR 0x10 /* Socket Interrupt Request Register */
#define FX3_SCK_INTR_MASK 0x14 /* Socket Interrupt Mask Register */
#define FX3_DSCR_BUFFER 0x20 /* Descriptor Buffer Base Address Register */
#define FX3_DSCR_SYNC 0x24 /* Descriptor Synchronization Pointers Register */
#define FX3_DSCR_CHAIN 0x28 /* Descriptor Chain Pointers Register */
#define FX3_DSCR_SIZE 0x02C /* Descriptor Size Register */
#define FX3_EVENT 0x7C /* Event Communication Register */
#define FX3_SCK_INTR0 0x00 /* Socket Interrupt Request Register */
#define FX3_ADAPTER_STATUS 0xFC /* Adapter Global Status Fields */
#define FX3_SIB_ID 0xE0027F00 /* Storage Interface Block ID register */
#define FX3_SIB_POWER 0xE0027F04 /* SIB Power Control */
#define FX3_SDMMC_CMD_IDX 0xE0020000 /* SDMMC Command Index */
#define FX3_SDMMC_CMD_ARG0 0xE0020004 /* SDMMC Command Argument 0 */
#define FX3_SDMMC_CMD_ARG1 0xE0020008 /* SDMMC Command Argument 1 */
#define FX3_SDMMC_RESP_IDX 0xE002000C /* SDMMC Response Index */
#define FX3_SDMMC_RESP_REG0 0xE0020010 /* SDMMC Command Response 0 */
#define FX3_SDMMC_RESP_REG1 0xE0020014 /* SDMMC Command Response 1 */
#define FX3_SDMMC_RESP_REG2 0xE0020018 /* SDMMC Command Response 2 */
#define FX3_SDMMC_RESP_REG3 0xE002001C /* SDMMC Command Response 3 */
#define FX3_SDMMC_RESP_REG4 0xE0020020 /* SDMMC Command Response 4 */
#define FX3_SDMMC_CMD_RESP_FMT 0xE0020024 /* SDMMC Command Response Format */
#define FX3_SDMMC_BLOCK_COUNT 0xE0020028 /* SDMMC Block Count */
#define FX3_SDMMC_BLOCK_LEN 0xE002002C /* SDMMC Block Length */
#define FX3_SDMMC_MODE_CFG 0xE0020030 /* SDMMC Mode Configuration */
#define FX3_SDMMC_DATA_CFG 0xE0020034 /* SDMMC Data Configuration */
#define FX3_SDMMC_CS 0xE0020038 /* SDMMC Command and Status */
#define FX3_SDMMC_STATUS 0xE002003C /* SDMMC Status */
#define FX3_SDMMC_INTR 0xE0020040 /* SDMMC Interrupt Status */
#define FX3_SDMMC_INTR_MASK 0xE0020044 /* SDMMC Interrupt Mask */
#define FX3_SDMMC_NCR 0xE0020048 /* SDMMC Command Response Timing Register #1 */
#define FX3_SDMMC_NCC_NWR 0xE002004C /* SDMMC Command Response Timing Register #2 */
#define FX3_SDMMC_NAC 0xE0020050 /* SDMMC Read Timeout Register */
#define FX3_SDMMC_HW_CTRL 0xE0020054 /* SDMMC Hardware Control Register */
#define FX3_SDMMC_DLL_CTRL 0xE0020058 /* SDMMC DLL Control */
#define FX3_SCK_DSCR_DSCR_LOW_SHIFT 24
#define FX3_SCK_DSCR_DSCR_LOW_BITS 8
#define FX3_SCK_DSCR_DSCR_LOW_MASK (0xffUL << 24)
#define FX3_SCK_DSCR_DSCR_COUNT_SHIFT 16
#define FX3_SCK_DSCR_DSCR_COUNT_BITS 8
#define FX3_SCK_DSCR_DSCR_COUNT_MASK (0xffUL << 16)
#define FX3_SCK_DSCR_DSCR_NUMBER_SHIFT 0
#define FX3_SCK_DSCR_DSCR_NUMBER_BITS 16
#define FX3_SCK_DSCR_DSCR_NUMBER_MASK (0xffffUL << 0)
#define FX3_SCK_STATUS_GO_ENABLE (1UL << 31)
#define FX3_SCK_STATUS_GO_SUSPEND (1UL << 30)
#define FX3_SCK_STATUS_UNIT (1UL << 29)
#define FX3_SCK_STATUS_WRAPUP (1UL << 28)
#define FX3_SCK_STATUS_SUSP_EOP (1UL << 27)
#define FX3_SCK_STATUS_SUSP_TRANS (1UL << 26)
#define FX3_SCK_STATUS_SUSP_LAST (1UL << 25)
#define FX3_SCK_STATUS_SUSP_PARTIAL (1UL << 24)
#define FX3_SCK_STATUS_EN_CONS_EVENTS (1UL << 23)
#define FX3_SCK_STATUS_EN_PROD_EVENTS (1UL << 22)
#define FX3_SCK_STATUS_TRUNCATE (1UL << 21)
#define FX3_SCK_STATUS_ENABLED (1UL << 20)
#define FX3_SCK_STATUS_SUSPENDED (1UL << 19)
#define FX3_SCK_STATUS_ZLP_RCVD (1UL << 18)
#define FX3_SCK_STATUS_STATE_SHIFT 15
#define FX3_SCK_STATUS_STATE_BITS 3
#define FX3_SCK_STATUS_STATE_MASK (0x7UL << 15)
#define FX3_SCK_STATUS_AVL_ENABLE (1UL << 10)
#define FX3_SCK_STATUS_AVL_MIN_SHIFT 5
#define FX3_SCK_STATUS_AVL_MIN_BITS 5
#define FX3_SCK_STATUS_AVL_MIN_MASK (0x1fUL << 5)
#define FX3_SCK_STATUS_AVL_COUNT_SHIFT 0
#define FX3_SCK_STATUS_AVL_COUNT_BITS 5
#define FX3_SCK_STATUS_AVL_COUNT_MASK (0x1fUL << 0)
#define FX3_SCK_INTR_LAST_BUF (1UL << 9)
#define FX3_SCK_INTR_PARTIAL_BUF (1UL << 8)
#define FX3_SCK_INTR_TRANS_DONE (1UL << 7)
#define FX3_SCK_INTR_ERROR (1UL << 6)
#define FX3_SCK_INTR_SUSPEND (1UL << 5)
#define FX3_SCK_INTR_STALL (1UL << 4)
#define FX3_SCK_INTR_DSCR_NOT_AVL (1UL << 3)
#define FX3_SCK_INTR_DSCR_IS_LOW (1UL << 2)
#define FX3_SCK_INTR_CONSUME_EVENT (1UL << 1)
#define FX3_SCK_INTR_PRODUCE_EVENT (1UL << 0)
#define FX3_SCK_INTR_MASK_LAST_BUF (1UL << 9)
#define FX3_SCK_INTR_MASK_PARTIAL_BUF (1UL << 8)
#define FX3_SCK_INTR_MASK_TRANS_DONE (1UL << 7)
#define FX3_SCK_INTR_MASK_ERROR (1UL << 6)
#define FX3_SCK_INTR_MASK_SUSPEND (1UL << 5)
#define FX3_SCK_INTR_MASK_STALL (1UL << 4)
#define FX3_SCK_INTR_MASK_DSCR_NOT_AVL (1UL << 3)
#define FX3_SCK_INTR_MASK_DSCR_IS_LOW (1UL << 2)
#define FX3_SCK_INTR_MASK_CONSUME_EVENT (1UL << 1)
#define FX3_SCK_INTR_MASK_PRODUCE_EVENT (1UL << 0)
#define FX3_DSCR_SYNC_EN_PROD_INT (1UL << 31)
#define FX3_DSCR_SYNC_EN_PROD_EVENT (1UL << 30)
#define FX3_DSCR_SYNC_PROD_IP_SHIFT 24
#define FX3_DSCR_SYNC_PROD_IP_BITS 6
#define FX3_DSCR_SYNC_PROD_IP_MASK (0x3fUL << 24)
#define FX3_DSCR_SYNC_PROD_SCK_SHIFT 16
#define FX3_DSCR_SYNC_PROD_SCK_BITS 8
#define FX3_DSCR_SYNC_PROD_SCK_MASK (0xffUL << 16)
#define FX3_DSCR_SYNC_EN_CONS_INT (1UL << 15)
#define FX3_DSCR_SYNC_EN_CONS_EVENT (1UL << 14)
#define FX3_DSCR_SYNC_CONS_IP_SHIFT 8
#define FX3_DSCR_SYNC_CONS_IP_BITS 6
#define FX3_DSCR_SYNC_CONS_IP_MASK (0x3fUL << 8)
#define FX3_DSCR_SYNC_CONS_SCK_SHIFT 0
#define FX3_DSCR_SYNC_CONS_SCK_BITS 8
#define FX3_DSCR_SYNC_CONS_SCK_MASK (0xffUL << 0)
#define FX3_DSCR_CHAIN_WR_NEXT_DSCR_SHIFT 16
#define FX3_DSCR_CHAIN_WR_NEXT_DSCR_BITS 16
#define FX3_DSCR_CHAIN_WR_NEXT_DSCR_MASK (0xffffUL << 16)
#define FX3_DSCR_CHAIN_RD_NEXT_DSCR_SHIFT 0
#define FX3_DSCR_CHAIN_RD_NEXT_DSCR_BITS 16
#define FX3_DSCR_CHAIN_RD_NEXT_DSCR_MASK (0xffffUL << 0)
#define FX3_DSCR_SIZE_BYTE_COUNT_SHIFT 16
#define FX3_DSCR_SIZE_BYTE_COUNT_BITS 16
#define FX3_DSCR_SIZE_BYTE_COUNT_MASK (0xffffUL << 16)
#define FX3_DSCR_SIZE_BUFFER_SIZE_SHIFT 4
#define FX3_DSCR_SIZE_BUFFER_SIZE_BITS 12
#define FX3_DSCR_SIZE_BUFFER_SIZE_MASK (0xfffUL << 4)
#define FX3_DSCR_SIZE_BUFFER_OCCUPIED (1UL << 3)
#define FX3_DSCR_SIZE_BUFFER_ERROR (1UL << 2)
#define FX3_DSCR_SIZE_EOP (1UL << 1)
#define FX3_DSCR_SIZE_MARKER (1UL << 0)
#define FX3_EVENT_EVENT_TYPE (1UL << 16)
#define FX3_EVENT_ACTIVE_DSCR_SHIFT 0
#define FX3_EVENT_ACTIVE_DSCR_BITS 16
#define FX3_EVENT_ACTIVE_DSCR_MASK (0xffffUL << 0)
#define FX3_SCK_INTR0_SCKINTR_SHIFT 0
#define FX3_SCK_INTR0_SCKINTR_BITS 256
#define FX3_SCK_INTR0_SCKINTR_MASK (0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffUL << 0)
#define FX3_ADAPTER_STATUS_WORD_SIZE_SHIFT 22
#define FX3_ADAPTER_STATUS_WORD_SIZE_BITS 2
#define FX3_ADAPTER_STATUS_WORD_SIZE_MASK (0x3UL << 22)
#define FX3_ADAPTER_STATUS_FQ_SIZE_SHIFT 16
#define FX3_ADAPTER_STATUS_FQ_SIZE_BITS 6
#define FX3_ADAPTER_STATUS_FQ_SIZE_MASK (0x3fUL << 16)
#define FX3_ADAPTER_STATUS_IG_ONLY_SHIFT 8
#define FX3_ADAPTER_STATUS_IG_ONLY_BITS 8
#define FX3_ADAPTER_STATUS_IG_ONLY_MASK (0xffUL << 8)
#define FX3_ADAPTER_STATUS_TTL_SOCKETS_SHIFT 0
#define FX3_ADAPTER_STATUS_TTL_SOCKETS_BITS 8
#define FX3_ADAPTER_STATUS_TTL_SOCKETS_MASK (0xffUL << 0)
#define FX3_SIB_ID_BLOCK_VERSION_SHIFT 16
#define FX3_SIB_ID_BLOCK_VERSION_BITS 16
#define FX3_SIB_ID_BLOCK_VERSION_MASK (0xffffUL << 16)
#define FX3_SIB_ID_BLOCK_ID_SHIFT 0
#define FX3_SIB_ID_BLOCK_ID_BITS 16
#define FX3_SIB_ID_BLOCK_ID_MASK (0xffffUL << 0)
#define FX3_SIB_POWER_RESETN (1UL << 31)
#define FX3_SIB_POWER_ACTIVE (1UL << 0)
#define FX3_SDMMC_CMD_IDX_CMD_SHIFT 0
#define FX3_SDMMC_CMD_IDX_CMD_BITS 6
#define FX3_SDMMC_CMD_IDX_CMD_MASK (0x3fUL << 0)
#define FX3_SDMMC_RESP_IDX_ST_BIT (1UL << 7)
#define FX3_SDMMC_RESP_IDX_TR_BIT (1UL << 6)
#define FX3_SDMMC_RESP_IDX_CMD_SHIFT 0
#define FX3_SDMMC_RESP_IDX_CMD_BITS 6
#define FX3_SDMMC_RESP_IDX_CMD_MASK (0x3fUL << 0)
#define FX3_SDMMC_CMD_RESP_FMT_RESPCRC_START (1UL << 31)
#define FX3_SDMMC_CMD_RESP_FMT_CORCRC_ODD (1UL << 30)
#define FX3_SDMMC_CMD_RESP_FMT_R_CRC_EN (1UL << 28)
#define FX3_SDMMC_CMD_RESP_FMT_CORCRC (1UL << 27)
#define FX3_SDMMC_CMD_RESP_FMT_RESPCONF_SHIFT 16
#define FX3_SDMMC_CMD_RESP_FMT_RESPCONF_BITS 11
#define FX3_SDMMC_CMD_RESP_FMT_RESPCONF_MASK (0x7ffUL << 16)
#define FX3_SDMMC_CMD_RESP_FMT_CMDFRMT_SHIFT 0
#define FX3_SDMMC_CMD_RESP_FMT_CMDFRMT_BITS 6
#define FX3_SDMMC_CMD_RESP_FMT_CMDFRMT_MASK (0x3fUL << 0)
#define FX3_SDMMC_MODE_CFG_IDLE_STOP_CLK_EN (1UL << 31)
#define FX3_SDMMC_MODE_CFG_IDLE_STOP_CLK_DELAY_SHIFT 24
#define FX3_SDMMC_MODE_CFG_IDLE_STOP_CLK_DELAY_BITS 7
#define FX3_SDMMC_MODE_CFG_IDLE_STOP_CLK_DELAY_MASK (0x7fUL << 24)
#define FX3_SDMMC_MODE_CFG_EXP_BOOT_ACK (1UL << 22)
#define FX3_SDMMC_MODE_CFG_BLK_END_STOP_CLK (1UL << 21)
#define FX3_SDMMC_MODE_CFG_RD_END_STOP_CLK_EN (1UL << 19)
#define FX3_SDMMC_MODE_CFG_CARD_DETECT_POLARITY (1UL << 18)
#define FX3_SDMMC_MODE_CFG_WR_STOP_CLK_EN (1UL << 16)
#define FX3_SDMMC_MODE_CFG_RD_STOP_CLK_EN (1UL << 15)
#define FX3_SDMMC_MODE_CFG_EN_CMD_COMP (1UL << 14)
#define FX3_SDMMC_MODE_CFG_DATABUSWIDTH_SHIFT 12
#define FX3_SDMMC_MODE_CFG_DATABUSWIDTH_BITS 2
#define FX3_SDMMC_MODE_CFG_DATABUSWIDTH_MASK (0x3UL << 12)
#define FX3_SDMMC_MODE_CFG_MODE_SHIFT 10
#define FX3_SDMMC_MODE_CFG_MODE_BITS 2
#define FX3_SDMMC_MODE_CFG_MODE_MASK (0x3UL << 10)
#define FX3_SDMMC_MODE_CFG_SIGNALING_SHIFT 6
#define FX3_SDMMC_MODE_CFG_SIGNALING_BITS 4
#define FX3_SDMMC_MODE_CFG_SIGNALING_MASK (0xfUL << 6)
#define FX3_SDMMC_MODE_CFG_DLL_BYPASS_EN (1UL << 5)
#define FX3_SDMMC_DATA_CFG_EXPBUSY (1UL << 3)
#define FX3_SDMMC_DATA_CFG_EXPCRCR (1UL << 2)
#define FX3_SDMMC_DATA_CFG_CARD_BUSY_DET (1UL << 1)
#define FX3_SDMMC_DATA_CFG_RD_CRC_EN (1UL << 0)
#define FX3_SDMMC_CS_EOP_EOT (1UL << 31)
#define FX3_SDMMC_CS_SOCKET_SHIFT 24
#define FX3_SDMMC_CS_SOCKET_BITS 5
#define FX3_SDMMC_CS_SOCKET_MASK (0x1fUL << 24)
#define FX3_SDMMC_CS_SDIO_READ_WAIT_EN (1UL << 15)
#define FX3_SDMMC_CS_SDMMC_CLK_DIS (1UL << 14)
#define FX3_SDMMC_CS_CLR_BOOTCMD (1UL << 11)
#define FX3_SDMMC_CS_CLR_RDDCARD (1UL << 10)
#define FX3_SDMMC_CS_CLR_WRDCARD (1UL << 9)
#define FX3_SDMMC_CS_CLR_SNDCMD (1UL << 8)
#define FX3_SDMMC_CS_CMDCOMP_DIS (1UL << 7)
#define FX3_SDMMC_CS_BOOTCMD (1UL << 6)
#define FX3_SDMMC_CS_RSTCONT (1UL << 5)
#define FX3_SDMMC_CS_RDDCARD (1UL << 2)
#define FX3_SDMMC_CS_WRDCARD (1UL << 1)
#define FX3_SDMMC_CS_SNDCMD (1UL << 0)
#define FX3_SDMMC_STATUS_CRC16_EVEN_ERROR (1UL << 31)
#define FX3_SDMMC_STATUS_CRC16_ODD_ERROR (1UL << 30)
#define FX3_SDMMC_STATUS_DATA_SM_BUSY (1UL << 28)
#define FX3_SDMMC_STATUS_COMMAND_SM_BUSY (1UL << 27)
#define FX3_SDMMC_STATUS_CRCFC_SHIFT 24
#define FX3_SDMMC_STATUS_CRCFC_BITS 3
#define FX3_SDMMC_STATUS_CRCFC_MASK (0x7UL << 24)
#define FX3_SDMMC_STATUS_RD_END_DATA_ERROR (1UL << 18)
#define FX3_SDMMC_STATUS_DAT0_STAT (1UL << 17)
#define FX3_SDMMC_STATUS_DLL_LOCKED (1UL << 16)
#define FX3_SDMMC_STATUS_DLL_LOST_LOCK (1UL << 15)
#define FX3_SDMMC_STATUS_BOOT_ACK (1UL << 14)
#define FX3_SDMMC_STATUS_CMD_COMP (1UL << 13)
#define FX3_SDMMC_STATUS_FIFO_U_DET (1UL << 12)
#define FX3_SDMMC_STATUS_FIFO_O_DET (1UL << 11)
#define FX3_SDMMC_STATUS_DAT3_STAT (1UL << 10)
#define FX3_SDMMC_STATUS_CARD_DETECT (1UL << 9)
#define FX3_SDMMC_STATUS_SDIO_INTR (1UL << 8)
#define FX3_SDMMC_STATUS_CRC16_ERROR (1UL << 7)
#define FX3_SDMMC_STATUS_RD_DATA_TIMEOUT (1UL << 6)
#define FX3_SDMMC_STATUS_BLOCKS_RECEIVED (1UL << 5)
#define FX3_SDMMC_STATUS_BLOCK_COMP (1UL << 4)
#define FX3_SDMMC_STATUS_CRC7_ERROR (1UL << 3)
#define FX3_SDMMC_STATUS_RESPTIMEOUT (1UL << 2)
#define FX3_SDMMC_STATUS_RCVDRES (1UL << 1)
#define FX3_SDMMC_STATUS_CMDSENT (1UL << 0)
#define FX3_SDMMC_INTR_RD_END_DATA_ERROR (1UL << 18)
#define FX3_SDMMC_INTR_DAT0_OUTOF_BUSY (1UL << 17)
#define FX3_SDMMC_INTR_DLL_LOCKED (1UL << 16)
#define FX3_SDMMC_INTR_DLL_LOST_LOCK (1UL << 15)
#define FX3_SDMMC_INTR_BOOT_ACK (1UL << 14)
#define FX3_SDMMC_INTR_CMD_COMP (1UL << 13)
#define FX3_SDMMC_INTR_FIFO_U_DET (1UL << 12)
#define FX3_SDMMC_INTR_FIFO_O_DET (1UL << 11)
#define FX3_SDMMC_INTR_DAT3_CHANGE (1UL << 10)
#define FX3_SDMMC_INTR_CARD_DETECT (1UL << 9)
#define FX3_SDMMC_INTR_SDIO_INTR (1UL << 8)
#define FX3_SDMMC_INTR_CRC16_ERROR (1UL << 7)
#define FX3_SDMMC_INTR_RD_DATA_TIMEOUT (1UL << 6)
#define FX3_SDMMC_INTR_BLOCKS_RECEIVED (1UL << 5)
#define FX3_SDMMC_INTR_BLOCK_COMP (1UL << 4)
#define FX3_SDMMC_INTR_CRC7_ERROR (1UL << 3)
#define FX3_SDMMC_INTR_RESPTIMEOUT (1UL << 2)
#define FX3_SDMMC_INTR_RCVDRES (1UL << 1)
#define FX3_SDMMC_INTR_CMDSENT (1UL << 0)
#define FX3_SDMMC_INTR_MASK_RD_END_DATA_ERROR (1UL << 18)
#define FX3_SDMMC_INTR_MASK_DAT0_OUTOF_BUSY (1UL << 17)
#define FX3_SDMMC_INTR_MASK_DLL_LOCKED (1UL << 16)
#define FX3_SDMMC_INTR_MASK_DLL_LOST_LOCK (1UL << 15)
#define FX3_SDMMC_INTR_MASK_BOOT_ACK (1UL << 14)
#define FX3_SDMMC_INTR_MASK_CMD_COMP (1UL << 13)
#define FX3_SDMMC_INTR_MASK_FIFO_U_DET (1UL << 12)
#define FX3_SDMMC_INTR_MASK_FIFO_O_DET (1UL << 11)
#define FX3_SDMMC_INTR_MASK_DAT3_CHANGE (1UL << 10)
#define FX3_SDMMC_INTR_MASK_CARD_DETECT (1UL << 9)
#define FX3_SDMMC_INTR_MASK_SDIO_INTR (1UL << 8)
#define FX3_SDMMC_INTR_MASK_CRC16_ERROR (1UL << 7)
#define FX3_SDMMC_INTR_MASK_RD_DATA_TIMEOUT (1UL << 6)
#define FX3_SDMMC_INTR_MASK_BLOCKS_RECEIVED (1UL << 5)
#define FX3_SDMMC_INTR_MASK_BLOCK_COMP (1UL << 4)
#define FX3_SDMMC_INTR_MASK_CRC7_ERROR (1UL << 3)
#define FX3_SDMMC_INTR_MASK_RESPTIMEOUT (1UL << 2)
#define FX3_SDMMC_INTR_MASK_RCVDRES (1UL << 1)
#define FX3_SDMMC_INTR_MASK_CMDSENT (1UL << 0)
#define FX3_SDMMC_NCR_NRC_MIN_SHIFT 8
#define FX3_SDMMC_NCR_NRC_MIN_BITS 8
#define FX3_SDMMC_NCR_NRC_MIN_MASK (0xffUL << 8)
#define FX3_SDMMC_NCR_NCR_MAX_SHIFT 0
#define FX3_SDMMC_NCR_NCR_MAX_BITS 7
#define FX3_SDMMC_NCR_NCR_MAX_MASK (0x7fUL << 0)
#define FX3_SDMMC_NCC_NWR_NWR_MIN_SHIFT 8
#define FX3_SDMMC_NCC_NWR_NWR_MIN_BITS 8
#define FX3_SDMMC_NCC_NWR_NWR_MIN_MASK (0xffUL << 8)
#define FX3_SDMMC_NCC_NWR_NCC_MIN_SHIFT 0
#define FX3_SDMMC_NCC_NWR_NCC_MIN_BITS 4
#define FX3_SDMMC_NCC_NWR_NCC_MIN_MASK (0xfUL << 0)
#define FX3_SDMMC_NAC_RDTMOUT_SHIFT 2
#define FX3_SDMMC_NAC_RDTMOUT_BITS 30
#define FX3_SDMMC_NAC_RDTMOUT_MASK (0x3fffffffUL << 2)
#define FX3_SDMMC_HW_CTRL_HW_RESET_EMMC (1UL << 0)
#define FX3_SDMMC_DLL_CTRL_DLL_RESET_N (1UL << 18)
#define FX3_SDMMC_DLL_CTRL_PIN_CLOCK_PHASE_SEL_SHIFT 11
#define FX3_SDMMC_DLL_CTRL_PIN_CLOCK_PHASE_SEL_BITS 4
#define FX3_SDMMC_DLL_CTRL_PIN_CLOCK_PHASE_SEL_MASK (0xfUL << 11)
#define FX3_SDMMC_DLL_CTRL_SAMPLE_CMD_PHASE_SEL_SHIFT 7
#define FX3_SDMMC_DLL_CTRL_SAMPLE_CMD_PHASE_SEL_BITS 4
#define FX3_SDMMC_DLL_CTRL_SAMPLE_CMD_PHASE_SEL_MASK (0xfUL << 7)
#define FX3_SDMMC_DLL_CTRL_SAMPLE_DATA_PHASE_SEL_SHIFT 3
#define FX3_SDMMC_DLL_CTRL_SAMPLE_DATA_PHASE_SEL_BITS 4
#define FX3_SDMMC_DLL_CTRL_SAMPLE_DATA_PHASE_SEL_MASK (0xfUL << 3)
#define FX3_SDMMC_DLL_CTRL_DLL_STAT (1UL << 2)
#define FX3_SDMMC_DLL_CTRL_HIGH_FREQ (1UL << 1)
#define FX3_SDMMC_DLL_CTRL_ENABLE (1UL << 0)
#endif /* RDB_DMA_H_ */

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/*
* Copyright (C) 2018 Marcus Comstedt
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef RDB_GCTL_H_
#define RDB_GCTL_H_
#define FX3_GCTL_CONTROL 0xE0050000 /* Global control */
#define FX3_GCTL_WAKEUP_EN 0xE0050004 /* Wakeup Enable Register */
#define FX3_GCTL_WAKEUP_POLARITY 0xE0050008 /* Wakeup Signal Polarity Register */
#define FX3_GCTL_WAKEUP_EVENT 0xE005000C /* Wakeup Event Register */
#define FX3_GCTL_FREEZE 0xE0050010 /* I/O Freeze Control Register */
#define FX3_GCTL_WATCHDOG_CS 0xE0050014 /* Watchdog Timers Command and Control Register */
#define FX3_GCTL_WATCHDOG_TIMER0 0xE0050018 /* Watchdog Timer Value 0 Register */
#define FX3_GCTL_WATCHDOG_TIMER1 0xE005001C /* Watchdog Timer Value 1 Register */
#define FX3_GCTL_IOMATRIX 0xE0051008 /* I/O Matrix Configuration Register */
#define FX3_GCTL_GPIO_SIMPLE 0xE005100C /* GPIO Override Configuration Register */
#define FX3_GCTL_GPIO_COMPLEX 0xE0051014 /* GPIO Override Configuration Register */
#define FX3_GCTL_DS 0xE005101C /* I/O Drive Strength Configuration Register */
#define FX3_GCTL_WPU_CFG 0xE0051020 /* I/O Pull-Up Configuration Register */
#define FX3_GCTL_WPD_CFG 0xE0051028 /* I/O Pull-Down Configuration Register */
#define FX3_GCTL_IOPOWER 0xE0051030 /* I/O Power Observability Register */
#define FX3_GCTL_IOPOWER_INTR 0xE0051034 /* I/O Power Change Interrupt Register */
#define FX3_GCTL_IOPOWER_INTR_MASK 0xE0051038 /* I/O Power Change Interrupt Mask Register */
#define FX3_GCTL_SW_INT 0xE005104C /* Software Interrupt Register */
#define FX3_GCTL_PLL_CFG 0xE0052000 /* PLL Configuration Register */
#define FX3_GCTL_CPU_CLK_CFG 0xE0052004 /* CPU and Bus Clock Configuration Register */
#define FX3_GCTL_UIB_CORE_CLK 0xE0052008 /* UIB Clock Configuration Register */
#define FX3_GCTL_PIB_CORE_CLK 0xE005200C /* PIB Clock Configuration Register */
#define FX3_GCTL_GPIO_FAST_CLK 0xE0052018 /* GPIO Fast Clock Configuration Register */
#define FX3_GCTL_GPIO_SLOW_CLK 0xE005201C /* GPIO Slow Clock Configuration Register */
#define FX3_GCTL_I2C_CORE_CLK 0xE0052020 /* I²C Core Clock Configuration Register */
#define FX3_GCTL_UART_CORE_CLK 0xE0052024 /* UART Core Clock Configuration Register */
#define FX3_GCTL_SPI_CORE_CLK 0xE005202C /* SPI Core Clock Configuration Register */
#define FX3_GCTL_I2S_CORE_CLK 0xE0052034 /* I2S Core Clock Configuration Register */
#define FX3_GCTL_CONTROL_HARD_RESET_N (1UL << 31)
#define FX3_GCTL_CONTROL_CPU_RESET_N (1UL << 30)
#define FX3_GCTL_CONTROL_WARM_BOOT (1UL << 29)
#define FX3_GCTL_CONTROL_BOOTROM_EN (1UL << 28)
#define FX3_GCTL_CONTROL_MAIN_POWER_EN (1UL << 26)
#define FX3_GCTL_CONTROL_MAIN_CLOCK_EN (1UL << 25)
#define FX3_GCTL_CONTROL_FREEZE_IO (1UL << 24)
#define FX3_GCTL_CONTROL_USB_VBAT_EN (1UL << 22)
#define FX3_GCTL_CONTROL_USB_POWER_EN (1UL << 21)
#define FX3_GCTL_CONTROL_ANALOG_SWITCH (1UL << 18)
#define FX3_GCTL_CONTROL_WDT_PROTECT_SHIFT 16
#define FX3_GCTL_CONTROL_WDT_PROTECT_BITS 2
#define FX3_GCTL_CONTROL_WDT_PROTECT_MASK (0x3UL << 16)
#define FX3_GCTL_CONTROL_NO_SBYWFI (1UL << 15)
#define FX3_GCTL_CONTROL_SYSMEM_BIST_EN (1UL << 14)
#define FX3_GCTL_CONTROL_WAKEUP_CPU_INT (1UL << 12)
#define FX3_GCTL_CONTROL_WAKEUP_AP_INT (1UL << 11)
#define FX3_GCTL_CONTROL_RAM_SLEEP (1UL << 10)
#define FX3_GCTL_CONTROL_DEBUG_MODE (1UL << 9)
#define FX3_GCTL_CONTROL_BOOT_COMPLETE (1UL << 8)
#define FX3_GCTL_CONTROL_WAKEUP_CLK (1UL << 4)
#define FX3_GCTL_CONTROL_WAKEUP_PWR (1UL << 3)
#define FX3_GCTL_CONTROL_WDT_RESET (1UL << 2)
#define FX3_GCTL_CONTROL_SW_RESET (1UL << 1)
#define FX3_GCTL_CONTROL_POR (1UL << 0)
#define FX3_GCTL_WAKEUP_EN_EN_WATCHDOG2 (1UL << 13)
#define FX3_GCTL_WAKEUP_EN_EN_WATCHDOG1 (1UL << 12)
#define FX3_GCTL_WAKEUP_EN_EN_UIB_VBUS (1UL << 11)
#define FX3_GCTL_WAKEUP_EN_EN_UIB_SSRX (1UL << 10)
#define FX3_GCTL_WAKEUP_EN_EN_UIB_OTGID (1UL << 9)
#define FX3_GCTL_WAKEUP_EN_EN_UIB_DM (1UL << 8)
#define FX3_GCTL_WAKEUP_EN_EN_UIB_DP (1UL << 7)
#define FX3_GCTL_WAKEUP_EN_EN_UART_CTS (1UL << 6)
#define FX3_GCTL_WAKEUP_EN_EN_GPIO_44 (1UL << 5)
#define FX3_GCTL_WAKEUP_EN_EN_GPIO_47 (1UL << 4)
#define FX3_GCTL_WAKEUP_EN_EN_GPIO_34 (1UL << 3)
#define FX3_GCTL_WAKEUP_EN_EN_PIB_CLK (1UL << 2)
#define FX3_GCTL_WAKEUP_EN_EN_PIB_CMD (1UL << 1)
#define FX3_GCTL_WAKEUP_EN_EN_PIB_CTRL0 (1UL << 0)
#define FX3_GCTL_WAKEUP_POLARITY_POL_UIB_VBUS (1UL << 11)
#define FX3_GCTL_WAKEUP_POLARITY_POL_UIB_DM (1UL << 8)
#define FX3_GCTL_WAKEUP_POLARITY_POL_UIB_DP (1UL << 7)
#define FX3_GCTL_WAKEUP_POLARITY_POL_UART_CTS (1UL << 6)
#define FX3_GCTL_WAKEUP_POLARITY_POL_GPIO_44 (1UL << 5)
#define FX3_GCTL_WAKEUP_POLARITY_POL_GPIO_47 (1UL << 4)
#define FX3_GCTL_WAKEUP_POLARITY_POL_GPIO_34 (1UL << 3)
#define FX3_GCTL_WAKEUP_EVENT_EV_WATCHDOG2 (1UL << 13)
#define FX3_GCTL_WAKEUP_EVENT_EV_WATCHDOG1 (1UL << 12)
#define FX3_GCTL_WAKEUP_EVENT_EV_UIB_VBUS (1UL << 11)
#define FX3_GCTL_WAKEUP_EVENT_EV_UIB_SSRX (1UL << 10)
#define FX3_GCTL_WAKEUP_EVENT_EV_UIB_OTGID (1UL << 9)
#define FX3_GCTL_WAKEUP_EVENT_EV_UIB_DM (1UL << 8)
#define FX3_GCTL_WAKEUP_EVENT_EV_UIB_DP (1UL << 7)
#define FX3_GCTL_WAKEUP_EVENT_EV_UART_CTS (1UL << 6)
#define FX3_GCTL_WAKEUP_EVENT_EV_GPIO_44 (1UL << 5)
#define FX3_GCTL_WAKEUP_EVENT_EV_GPIO_47 (1UL << 4)
#define FX3_GCTL_WAKEUP_EVENT_EV_GPIO_34 (1UL << 3)
#define FX3_GCTL_WAKEUP_EVENT_EV_PIB_CLK (1UL << 2)
#define FX3_GCTL_WAKEUP_EVENT_EV_PIB_CMD (1UL << 1)
#define FX3_GCTL_WAKEUP_EVENT_EV_PIB_CTRL0 (1UL << 0)
#define FX3_GCTL_FREEZE_VIO4IO_FRZ_SHIFT 6
#define FX3_GCTL_FREEZE_VIO4IO_FRZ_BITS 2
#define FX3_GCTL_FREEZE_VIO4IO_FRZ_MASK (0x3UL << 6)
#define FX3_GCTL_FREEZE_VIO3IO_FRZ_SHIFT 4
#define FX3_GCTL_FREEZE_VIO3IO_FRZ_BITS 2
#define FX3_GCTL_FREEZE_VIO3IO_FRZ_MASK (0x3UL << 4)
#define FX3_GCTL_FREEZE_VIO2IO_FRZ_SHIFT 2
#define FX3_GCTL_FREEZE_VIO2IO_FRZ_BITS 2
#define FX3_GCTL_FREEZE_VIO2IO_FRZ_MASK (0x3UL << 2)
#define FX3_GCTL_FREEZE_VIO1IO_FRZ_SHIFT 0
#define FX3_GCTL_FREEZE_VIO1IO_FRZ_BITS 2
#define FX3_GCTL_FREEZE_VIO1IO_FRZ_MASK (0x3UL << 0)
#define FX3_GCTL_WATCHDOG_CS_BACKUP_CLK (1UL << 31)
#define FX3_GCTL_WATCHDOG_CS_BACKUP_DIVIDER_SHIFT 16
#define FX3_GCTL_WATCHDOG_CS_BACKUP_DIVIDER_BITS 15
#define FX3_GCTL_WATCHDOG_CS_BACKUP_DIVIDER_MASK (0x7fffUL << 16)
#define FX3_GCTL_WATCHDOG_CS_BITS1_SHIFT 11
#define FX3_GCTL_WATCHDOG_CS_BITS1_BITS 5
#define FX3_GCTL_WATCHDOG_CS_BITS1_MASK (0x1fUL << 11)
#define FX3_GCTL_WATCHDOG_CS_INTR1 (1UL << 10)
#define FX3_GCTL_WATCHDOG_CS_MODE1_SHIFT 8
#define FX3_GCTL_WATCHDOG_CS_MODE1_BITS 2
#define FX3_GCTL_WATCHDOG_CS_MODE1_MASK (0x3UL << 8)
#define FX3_GCTL_WATCHDOG_CS_BITS0_SHIFT 3
#define FX3_GCTL_WATCHDOG_CS_BITS0_BITS 5
#define FX3_GCTL_WATCHDOG_CS_BITS0_MASK (0x1fUL << 3)
#define FX3_GCTL_WATCHDOG_CS_INTR0 (1UL << 2)
#define FX3_GCTL_WATCHDOG_CS_MODE0_SHIFT 0
#define FX3_GCTL_WATCHDOG_CS_MODE0_BITS 2
#define FX3_GCTL_WATCHDOG_CS_MODE0_MASK (0x3UL << 0)
#define FX3_GCTL_IOMATRIX_S1CFG_SHIFT 8
#define FX3_GCTL_IOMATRIX_S1CFG_BITS 3
#define FX3_GCTL_IOMATRIX_S1CFG_MASK (0x7UL << 8)
#define FX3_GCTL_IOMATRIX_S0CFG (1UL << 4)
#define FX3_GCTL_IOMATRIX_CARKIT (1UL << 1)
#define FX3_GCTL_GPIO_SIMPLE_OVERRIDE_SHIFT 0
#define FX3_GCTL_GPIO_SIMPLE_OVERRIDE_BITS 61
#define FX3_GCTL_GPIO_SIMPLE_OVERRIDE_MASK (0x1fffffffffffffffUL << 0)
#define FX3_GCTL_GPIO_COMPLEX_OVERRIDE_SHIFT 0
#define FX3_GCTL_GPIO_COMPLEX_OVERRIDE_BITS 61
#define FX3_GCTL_GPIO_COMPLEX_OVERRIDE_MASK (0x1fffffffffffffffUL << 0)
#define FX3_GCTL_DS_I2CDS_G_SHIFT 18
#define FX3_GCTL_DS_I2CDS_G_BITS 2
#define FX3_GCTL_DS_I2CDS_G_MASK (0x3UL << 18)
#define FX3_GCTL_DS_S1LDS_G_SHIFT 16
#define FX3_GCTL_DS_S1LDS_G_BITS 2
#define FX3_GCTL_DS_S1LDS_G_MASK (0x3UL << 16)
#define FX3_GCTL_DS_S1DS_G_SHIFT 14
#define FX3_GCTL_DS_S1DS_G_BITS 2
#define FX3_GCTL_DS_S1DS_G_MASK (0x3UL << 14)
#define FX3_GCTL_DS_S0DS_G_SHIFT 12
#define FX3_GCTL_DS_S0DS_G_BITS 2
#define FX3_GCTL_DS_S0DS_G_MASK (0x3UL << 12)
#define FX3_GCTL_DS_PDS_G_SHIFT 10
#define FX3_GCTL_DS_PDS_G_BITS 2
#define FX3_GCTL_DS_PDS_G_MASK (0x3UL << 10)
#define FX3_GCTL_DS_I2CDS_SHIFT 8
#define FX3_GCTL_DS_I2CDS_BITS 2
#define FX3_GCTL_DS_I2CDS_MASK (0x3UL << 8)
#define FX3_GCTL_DS_S1LDS_SHIFT 6
#define FX3_GCTL_DS_S1LDS_BITS 2
#define FX3_GCTL_DS_S1LDS_MASK (0x3UL << 6)
#define FX3_GCTL_DS_S1DS_SHIFT 4
#define FX3_GCTL_DS_S1DS_BITS 2
#define FX3_GCTL_DS_S1DS_MASK (0x3UL << 4)
#define FX3_GCTL_DS_S0DS_SHIFT 2
#define FX3_GCTL_DS_S0DS_BITS 2
#define FX3_GCTL_DS_S0DS_MASK (0x3UL << 2)
#define FX3_GCTL_DS_PDS_SHIFT 0
#define FX3_GCTL_DS_PDS_BITS 2
#define FX3_GCTL_DS_PDS_MASK (0x3UL << 0)
#define FX3_GCTL_WPU_CFG_WPU_SHIFT 0
#define FX3_GCTL_WPU_CFG_WPU_BITS 60
#define FX3_GCTL_WPU_CFG_WPU_MASK (0xfffffffffffffffUL << 0)
#define FX3_GCTL_WPD_CFG_WPD_SHIFT 0
#define FX3_GCTL_WPD_CFG_WPD_BITS 60
#define FX3_GCTL_WPD_CFG_WPD_MASK (0xfffffffffffffffUL << 0)
#define FX3_GCTL_IOPOWER_REG_BYPASS_EN (1UL << 21)
#define FX3_GCTL_IOPOWER_REG_CARKIT_EN (1UL << 20)
#define FX3_GCTL_IOPOWER_REG_CARKIT_SEL_SHIFT 18
#define FX3_GCTL_IOPOWER_REG_CARKIT_SEL_BITS 2
#define FX3_GCTL_IOPOWER_REG_CARKIT_SEL_MASK (0x3UL << 18)
#define FX3_GCTL_IOPOWER_USB_REGULATOR_TRIM_SHIFT 16
#define FX3_GCTL_IOPOWER_USB_REGULATOR_TRIM_BITS 2
#define FX3_GCTL_IOPOWER_USB_REGULATOR_TRIM_MASK (0x3UL << 16)
#define FX3_GCTL_IOPOWER_USB_POWER_GOOD (1UL << 13)
#define FX3_GCTL_IOPOWER_VBUS_TH (1UL << 12)
#define FX3_GCTL_IOPOWER_VBAT (1UL << 11)
#define FX3_GCTL_IOPOWER_VBUS (1UL << 10)
#define FX3_GCTL_IOPOWER_USB25REG (1UL << 9)
#define FX3_GCTL_IOPOWER_USB33REG (1UL << 8)
#define FX3_GCTL_IOPOWER_VIO5 (1UL << 7)
#define FX3_GCTL_IOPOWER_CVDDQ (1UL << 6)
#define FX3_GCTL_IOPOWER_EFVDDQ (1UL << 5)
#define FX3_GCTL_IOPOWER_VIO4 (1UL << 4)
#define FX3_GCTL_IOPOWER_VIO3 (1UL << 3)
#define FX3_GCTL_IOPOWER_VIO2 (1UL << 2)
#define FX3_GCTL_IOPOWER_VIO1 (1UL << 0)
#define FX3_GCTL_IOPOWER_INTR_USB_POWER_GOOD (1UL << 13)
#define FX3_GCTL_IOPOWER_INTR_VBUS_TH (1UL << 12)
#define FX3_GCTL_IOPOWER_INTR_VBAT (1UL << 11)
#define FX3_GCTL_IOPOWER_INTR_VBUS (1UL << 10)
#define FX3_GCTL_IOPOWER_INTR_USB25REG (1UL << 9)
#define FX3_GCTL_IOPOWER_INTR_USB33REG (1UL << 8)
#define FX3_GCTL_IOPOWER_INTR_VIO5 (1UL << 7)
#define FX3_GCTL_IOPOWER_INTR_CVDDQ (1UL << 6)
#define FX3_GCTL_IOPOWER_INTR_EFVDDQ (1UL << 5)
#define FX3_GCTL_IOPOWER_INTR_VIO4 (1UL << 4)
#define FX3_GCTL_IOPOWER_INTR_VIO3 (1UL << 3)
#define FX3_GCTL_IOPOWER_INTR_VIO2 (1UL << 2)
#define FX3_GCTL_IOPOWER_INTR_VIO1 (1UL << 0)
#define FX3_GCTL_IOPOWER_INTR_MASK_USB_POWER_GOOD (1UL << 13)
#define FX3_GCTL_IOPOWER_INTR_MASK_VBUS_TH (1UL << 12)
#define FX3_GCTL_IOPOWER_INTR_MASK_VBAT (1UL << 11)
#define FX3_GCTL_IOPOWER_INTR_MASK_VBUS (1UL << 10)
#define FX3_GCTL_IOPOWER_INTR_MASK_USB25REG (1UL << 9)
#define FX3_GCTL_IOPOWER_INTR_MASK_USB33REG (1UL << 8)
#define FX3_GCTL_IOPOWER_INTR_MASK_VIO5 (1UL << 7)
#define FX3_GCTL_IOPOWER_INTR_MASK_CVDDQ (1UL << 6)
#define FX3_GCTL_IOPOWER_INTR_MASK_EFVDDQ (1UL << 5)
#define FX3_GCTL_IOPOWER_INTR_MASK_VIO4 (1UL << 4)
#define FX3_GCTL_IOPOWER_INTR_MASK_VIO3 (1UL << 3)
#define FX3_GCTL_IOPOWER_INTR_MASK_VIO2 (1UL << 2)
#define FX3_GCTL_IOPOWER_INTR_MASK_VIO1 (1UL << 0)
#define FX3_GCTL_SW_INT_SWINT (1UL << 31)
#define FX3_GCTL_SW_INT_ARGUMENT_SHIFT 0
#define FX3_GCTL_SW_INT_ARGUMENT_BITS 31
#define FX3_GCTL_SW_INT_ARGUMENT_MASK (0x7fffffffUL << 0)
#define FX3_GCTL_PLL_CFG_PLL_LOCK (1UL << 19)
#define FX3_GCTL_PLL_CFG_FSLC_SHIFT 16
#define FX3_GCTL_PLL_CFG_FSLC_BITS 3
#define FX3_GCTL_PLL_CFG_FSLC_MASK (0x7UL << 16)
#define FX3_GCTL_PLL_CFG_CP_CFG_SHIFT 12
#define FX3_GCTL_PLL_CFG_CP_CFG_BITS 2
#define FX3_GCTL_PLL_CFG_CP_CFG_MASK (0x3UL << 12)
#define FX3_GCTL_PLL_CFG_REFDIV (1UL << 8)
#define FX3_GCTL_PLL_CFG_OUTDIV_SHIFT 6
#define FX3_GCTL_PLL_CFG_OUTDIV_BITS 2
#define FX3_GCTL_PLL_CFG_OUTDIV_MASK (0x3UL << 6)
#define FX3_GCTL_PLL_CFG_FBDIV_SHIFT 0
#define FX3_GCTL_PLL_CFG_FBDIV_BITS 6
#define FX3_GCTL_PLL_CFG_FBDIV_MASK (0x3fUL << 0)
#define FX3_GCTL_CPU_CLK_CFG_MMIO_DIV_SHIFT 12
#define FX3_GCTL_CPU_CLK_CFG_MMIO_DIV_BITS 4
#define FX3_GCTL_CPU_CLK_CFG_MMIO_DIV_MASK (0xfUL << 12)
#define FX3_GCTL_CPU_CLK_CFG_DMA_DIV_SHIFT 8
#define FX3_GCTL_CPU_CLK_CFG_DMA_DIV_BITS 4
#define FX3_GCTL_CPU_CLK_CFG_DMA_DIV_MASK (0xfUL << 8)
#define FX3_GCTL_CPU_CLK_CFG_SRC_SHIFT 4
#define FX3_GCTL_CPU_CLK_CFG_SRC_BITS 2
#define FX3_GCTL_CPU_CLK_CFG_SRC_MASK (0x3UL << 4)
#define FX3_GCTL_CPU_CLK_CFG_CPU_DIV_SHIFT 0
#define FX3_GCTL_CPU_CLK_CFG_CPU_DIV_BITS 4
#define FX3_GCTL_CPU_CLK_CFG_CPU_DIV_MASK (0xfUL << 0)
#define FX3_GCTL_UIB_CORE_CLK_CLK_EN (1UL << 31)
#define FX3_GCTL_UIB_CORE_CLK_PCLK_SRC_SHIFT 2
#define FX3_GCTL_UIB_CORE_CLK_PCLK_SRC_BITS 2
#define FX3_GCTL_UIB_CORE_CLK_PCLK_SRC_MASK (0x3UL << 2)
#define FX3_GCTL_UIB_CORE_CLK_EPMCLK_SRC_SHIFT 0
#define FX3_GCTL_UIB_CORE_CLK_EPMCLK_SRC_BITS 2
#define FX3_GCTL_UIB_CORE_CLK_EPMCLK_SRC_MASK (0x3UL << 0)
#define FX3_GCTL_PIB_CORE_CLK_CLK_EN (1UL << 31)
#define FX3_GCTL_PIB_CORE_CLK_SRC_SHIFT 11
#define FX3_GCTL_PIB_CORE_CLK_SRC_BITS 2
#define FX3_GCTL_PIB_CORE_CLK_SRC_MASK (0x3UL << 11)
#define FX3_GCTL_PIB_CORE_CLK_HALFDIV (1UL << 10)
#define FX3_GCTL_PIB_CORE_CLK_DIV_SHIFT 0
#define FX3_GCTL_PIB_CORE_CLK_DIV_BITS 10
#define FX3_GCTL_PIB_CORE_CLK_DIV_MASK (0x3ffUL << 0)
#define FX3_GCTL_GPIO_FAST_CLK_CLK_EN (1UL << 31)
#define FX3_GCTL_GPIO_FAST_CLK_SIMPLE_SHIFT 7
#define FX3_GCTL_GPIO_FAST_CLK_SIMPLE_BITS 2
#define FX3_GCTL_GPIO_FAST_CLK_SIMPLE_MASK (0x3UL << 7)
#define FX3_GCTL_GPIO_FAST_CLK_SRC_SHIFT 5
#define FX3_GCTL_GPIO_FAST_CLK_SRC_BITS 2
#define FX3_GCTL_GPIO_FAST_CLK_SRC_MASK (0x3UL << 5)
#define FX3_GCTL_GPIO_FAST_CLK_HALFDIV (1UL << 4)
#define FX3_GCTL_GPIO_FAST_CLK_DIV_SHIFT 0
#define FX3_GCTL_GPIO_FAST_CLK_DIV_BITS 4
#define FX3_GCTL_GPIO_FAST_CLK_DIV_MASK (0xfUL << 0)
#define FX3_GCTL_GPIO_SLOW_CLK_CLK_EN (1UL << 31)
#define FX3_GCTL_GPIO_SLOW_CLK_DIV_SHIFT 0
#define FX3_GCTL_GPIO_SLOW_CLK_DIV_BITS 6
#define FX3_GCTL_GPIO_SLOW_CLK_DIV_MASK (0x3fUL << 0)
#define FX3_GCTL_I2C_CORE_CLK_CLK_EN (1UL << 31)
#define FX3_GCTL_I2C_CORE_CLK_SRC_SHIFT 13
#define FX3_GCTL_I2C_CORE_CLK_SRC_BITS 2
#define FX3_GCTL_I2C_CORE_CLK_SRC_MASK (0x3UL << 13)
#define FX3_GCTL_I2C_CORE_CLK_HALFDIV (1UL << 12)
#define FX3_GCTL_I2C_CORE_CLK_DIV_SHIFT 0
#define FX3_GCTL_I2C_CORE_CLK_DIV_BITS 12
#define FX3_GCTL_I2C_CORE_CLK_DIV_MASK (0xfffUL << 0)
#define FX3_GCTL_UART_CORE_CLK_CLK_EN (1UL << 31)
#define FX3_GCTL_UART_CORE_CLK_SRC_SHIFT 17
#define FX3_GCTL_UART_CORE_CLK_SRC_BITS 2
#define FX3_GCTL_UART_CORE_CLK_SRC_MASK (0x3UL << 17)
#define FX3_GCTL_UART_CORE_CLK_HALFDIV (1UL << 16)
#define FX3_GCTL_UART_CORE_CLK_DIV_SHIFT 0
#define FX3_GCTL_UART_CORE_CLK_DIV_BITS 16
#define FX3_GCTL_UART_CORE_CLK_DIV_MASK (0xffffUL << 0)
#define FX3_GCTL_SPI_CORE_CLK_CLK_EN (1UL << 31)
#define FX3_GCTL_SPI_CORE_CLK_SRC_SHIFT 17
#define FX3_GCTL_SPI_CORE_CLK_SRC_BITS 2
#define FX3_GCTL_SPI_CORE_CLK_SRC_MASK (0x3UL << 17)
#define FX3_GCTL_SPI_CORE_CLK_HALFDIV (1UL << 16)
#define FX3_GCTL_SPI_CORE_CLK_DIV_SHIFT 0
#define FX3_GCTL_SPI_CORE_CLK_DIV_BITS 16
#define FX3_GCTL_SPI_CORE_CLK_DIV_MASK (0xffffUL << 0)
#define FX3_GCTL_I2S_CORE_CLK_CLK_EN (1UL << 31)
#define FX3_GCTL_I2S_CORE_CLK_MCLK_IN (1UL << 30)
#define FX3_GCTL_I2S_CORE_CLK_SRC_SHIFT 16
#define FX3_GCTL_I2S_CORE_CLK_SRC_BITS 2
#define FX3_GCTL_I2S_CORE_CLK_SRC_MASK (0x3UL << 16)
#define FX3_GCTL_I2S_CORE_CLK_HALFDIV (1UL << 15)
#define FX3_GCTL_I2S_CORE_CLK_DIV_SHIFT 0
#define FX3_GCTL_I2S_CORE_CLK_DIV_BITS 15
#define FX3_GCTL_I2S_CORE_CLK_DIV_MASK (0x7fffUL << 0)
#endif /* RDB_GCTL_H_ */

341
rdb/generator/convert.py Executable file
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@ -0,0 +1,341 @@
#!/usr/bin/env python3
import sys
import xml.etree.ElementTree as ElementTree
boilerplate = '''\
/*
* Copyright (C) 2018 Marcus Comstedt
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
'''
ppguard_prefix = 'RDB_'
# This register definition is mysteriously absent from the TRM, even though
# it refers to it from other places...
missing = [
('gctl', 'GCTL_CONTROL', 'Global control', '0xE0050000',
[('31', 'HARD_RESET_N'), ('30', 'CPU_RESET_N'), ('29', 'WARM_BOOT'),
('28', 'BOOTROM_EN'), ('26', 'MAIN_POWER_EN'), ('25', 'MAIN_CLOCK_EN'),
('24', 'FREEZE_IO'), ('22', 'USB_VBAT_EN'), ('21', 'USB_POWER_EN'),
('18', 'ANALOG_SWITCH'), ('17:16', 'WDT_PROTECT[1:0]'),
('15', 'NO_SBYWFI'), ('14', 'SYSMEM_BIST_EN'), ('12', 'WAKEUP_CPU_INT'),
('11', 'WAKEUP_AP_INT'), ('10', 'RAM_SLEEP'), ('9', 'DEBUG_MODE'),
('8', 'BOOT_COMPLETE'), ('4', 'WAKEUP_CLK'), ('3', 'WAKEUP_PWR'),
('2', 'WDT_RESET'), ('1', 'SW_RESET'), ('0', 'POR')]),
# More missing regs...
('uib', 'PROT_LMP_PORT_CAPABILITY_TIMER', 'Capability Timer Register', '0xE0033418', []),
('uib', 'PROT_LMP_PORT_CONFIGURATION_TIMER', 'Configuration Timer Register', '0xE003341C', []),
('uib', 'PROT_LMP_RECEIVED', 'Received Register', '0xE003345C', []),
('uib', 'PROT_STREAM_ERROR_DISABLE', 'Stream Error Disable Register', '0xE0033700', []),
('uib', 'PROT_STREAM_ERROR_STATUS', 'Stream Error Status Register', '0xE0033704', []),
('gpif', 'GPIF_SERIAL_IN_CONFIG', 'Serial Input Configuration Register', '0XE001401C', []),
('gpif', 'GPIF_SERIAL_OUT_CONFIG', 'Serial Output Configuration Register', '0XE0014020', []),
# TODO: add EFUSE, MMU stuff -sys64738
]
# Missing register fields
missing_fields = {
'LNK_LTSSM_STATE' : [('11:6', 'LTSSM_OVERRIDE_VALUE[5:0]'),
('12', 'LTSSM_OVERRIDE_EN'),
('13', 'LTSSM_OVERRIDE_GO'),
('14', 'LOOPBACK_MASTER'),
('15', 'DISABLE_SCRAMBLING'),
('16', 'LOOPBACK_ERROR'),
('17', 'LOOPBACK_GOOD'),
('31', 'LTSSM_FREEZE')],
}
# Fixes for typos in TRM
reg_name_fixups = {
'0xE0000BF0': ('I2C_ID', 'UART_ID'),
'0xE003151C': ('DEV_CTRL_INTR_MASK', 'DEV_CTRL_INTR'),
'0xE003205C': ('OHCI_RH_PORT_STATUS', 'EHCI_HCCPARAMS'),
'0xE0032060': ('OHCI_RH_PORT_STATUS', 'EHCI_USBCMD'),
'0x00': ('SCK_INTR', 'SCK_INTR0'),
}
reg_addr_fixups = {
'OHCI_REVISION': ('0xE0032010', '0xE0032024'),
}
field_name_fixups = {
'OTG_CTRL': {'11': ('B_SESS_VALID', 'B_END_SESS')},
}
field_bits_fixups = {
'GPIF_ADDR_COUNT_CONFIG': {'INCREMENT': ('7:0', '15:8')},
'GPIF_DATA_COUNT_CONFIG': {'INCREMENT': ('7:0', '15:8')},
}
class Register:
rdb_prefix='FX3_'
pad_size=34
pad_size_field=45
def __init__(self, group, name, description, address, fields):
try:
fixup = reg_name_fixups[address]
if name == fixup[0]:
name = fixup[1]
except KeyError:
pass
try:
fixup = reg_addr_fixups[name]
if address == fixup[0]:
address = fixup[1]
except KeyError:
pass
try:
fields += missing_fields[name]
except KeyError:
pass
self.group = group
self.name = name
self.description = description
self.address = address
self.fields = fields
def print_reg_def(self, file):
file.write('#define %s%s%s%s /* %s */\n' % (self.rdb_prefix, self.name, ' '*(self.pad_size - len(self.name)), self.address, self.description))
def print_field_defs(self, file):
if self.fields and (len(self.fields)>1 or (self.fields[0][0] != '0:31' and self.fields[0][0] != '31:0')):
file.write('\n')
for field in self.fields:
bits = field[0].split(':')
name = field[1].replace('{','[').split('[')
try:
fixup = field_name_fixups[self.name][field[0]]
if name[0] == fixup[0]:
name[0] = fixup[1]
except KeyError:
pass
try:
fixup = field_bits_fixups[self.name][name[0]]
if field[0] == fixup[0]:
bits = fixup[1].split(':')
except KeyError:
pass
if len(bits) == 1 and len(name) == 2 and (name[0] == 'EN_GPIO' or name[0] == 'EV_GPIO' or name[0] == 'POL_GPIO'):
name = [name[0]+'_'+name[1].split(']')[0]]
pad_size = self.pad_size_field
while pad_size <= len(self.name+'_'+name[0]+'_SHIFT'):
pad_size = pad_size + 1
if len(bits)>1:
lsb = int(bits[0])
msb = int(bits[1])
if lsb > msb:
(lsb, msb) = (msb, lsb)
if len(name) > 1:
name_range = name[1].split(']')[0].split(':')
nmsb = int(name_range[0])
nlsb = int(name_range[1])
if nmsb-nlsb != msb-lsb:
print('Field size mismatch! %s != %s (%s %s)'%(nmsb-nlsb+1, msb-lsb+1, self.name, name[0]))
if nmsb == msb and nlsb == 0:
lsb = 0
file.write('#define %s%s_%s_SHIFT%s%s\n' % (self.rdb_prefix, self.name, name[0], ' '*(pad_size - len(self.name+'_'+name[0]+'_SHIFT')), lsb))
file.write('#define %s%s_%s_BITS%s%s\n' % (self.rdb_prefix, self.name, name[0], ' '*(pad_size - len(self.name+'_'+name[0]+'_BITS')), msb-lsb+1))
file.write('#define %s%s_%s_MASK%s(%sUL << %s)\n' % (self.rdb_prefix, self.name, name[0], ' '*(pad_size - len(self.name+'_'+name[0]+'_MASK')), hex((1<<(msb-lsb+1))-1), lsb))
else:
file.write('#define %s%s_%s%s(1UL << %s)\n' % (self.rdb_prefix, self.name, name[0], ' '*(pad_size - len(self.name+'_'+name[0])), bits[0]))
class FontDatabase:
def __init__(self):
self.fonts = {}
def addfont(self, id, size, family, color, **extra):
if color == '#000000':
color = ''
self.fonts[id] = family+'/'+size+color
def getfont(self, id, bold, italic):
fontname = id and self.fonts[id]
if bold and fontname:
fontname = '*'+fontname
if italic and fontname:
fontname = '~'+fontname
return fontname
class RegDefParser:
reg_detail_font = '*Times/9'
reg_detail_alt_font = 'Times/9'
reg_detail_superscript_font = '*Times/7'
def __init__(self, group):
self.group = group
self.details = []
self.detail = []
self.info = []
self.combine = False
self.fontsel = False
def flush(self):
if self.detail:
if len(self.detail) == 1:
pass
elif self.info and len(self.detail) == 2 and self.detail[0] == self.info[0]:
pass
elif len(self.detail) == 2 and '0123456789'.find(self.detail[0][:1]) < 0:
pass
elif len(self.detail) == 3:
if self.info:
sys.exit('Multiple info candidates! %s %s'%(self.info, self.detail))
else:
self.info = self.detail
else:
self.details.append(self.detail)
self.detail = []
self.combine = False
def feedtext(self, font, text, leftcol):
if text.strip() == '':
pass
elif font == self.reg_detail_font or (leftcol and not self.fontsel and font == self.reg_detail_alt_font):
if self.combine:
self.detail[-1] = self.detail[-1] + text
self.combine = False
else:
self.detail.append(text)
if font == self.reg_detail_font:
self.fontsel = True
elif font == self.reg_detail_superscript_font and self.detail:
if text == '2':
text = '²'
else:
sys.exit('Unable to handle superscript text: %s' % text)
self.detail[-1] = self.detail[-1] + text
self.combine = True
else:
self.flush()
def finalize(self):
self.flush()
if not self.details and not self.info:
return None
if self.info:
return Register(self.group, *self.info, fields=self.details)
else:
sys.exit('Incomplete register details')
return None
class RegDefFinder:
chapter_font = 'Times/34#fbfbfb'
heading_font = '*Times/18'
register_chapter = '10'
register_sections = {
'3': 'vic',
'4': 'gctl',
'5': 'gctl',
'6': 'pib',
'7': 'gpif',
'8': 'pport',
'9': 'uib',
'10': 'uib',
'11': 'uib',
'12': 'uib',
'13': 'uib',
'14': 'uib',
'15': 'uib',
'16': 'uib',
'17': 'uibin',
'18': 'i2s',
'19': 'i2c',
'20': 'uart',
'21': 'spi',
'22': 'gpio',
'23': 'gpio',
'24': 'lpp',
'25': 'dma',
'26': 'dma'
}
def __init__(self):
self.chapter_number = None
self.section = None
self.register = None
self.registers = {group: [] for group in self.register_sections.values()}
def flush(self):
if self.register:
reg = self.register.finalize()
if reg:
self.registers[reg.group].append(reg)
self.register = None
def feedtext(self, font, text, left):
if font == self.chapter_font:
self.chapter_number = text.split('.')[0]
self.section = None
elif self.chapter_number != self.register_chapter:
pass
elif font == self.heading_font:
if text.startswith(self.register_chapter+'.'):
section = text.split()[0]
if section != self.section:
self.flush()
self.section = section
secnr = section.split('.')
if len(secnr) == 3:
self.register = RegDefParser(self.register_sections[secnr[1]])
elif self.register:
self.register.feedtext(font, text, left < 250)
def add_missing(self, group, name, *rest):
if next((r for r in self.registers[group] if r.name == name), False):
pass
else:
self.registers[group].append(Register(group, name, *rest))
fontdb = FontDatabase()
finder = RegDefFinder()
file = open('trm.xml', 'r')
for event, elem in ElementTree.iterparse(file):
if elem.tag == 'text':
finder.feedtext(fontdb.getfont(elem.get('font'), elem.find('b') != None, elem.find('i') != None),
''.join(elem.itertext()), int(elem.get('left')))
elif elem.tag == 'fontspec':
fontdb.addfont(**elem.attrib)
elif elem.tag == 'page':
elem.clear() # save memory
file.close()
finder.flush()
for m in missing:
finder.add_missing(*m)
for group, registers in finder.registers.items():
if group != 'dma':
registers = sorted(registers, key=lambda r: int(r.address.replace('?', 'F'), 16))
ppguard = '%s%s_H_' % (ppguard_prefix, group.upper())
file = open('%s.h' % group, 'w')
file.write(boilerplate)
file.write('#ifndef %s\n#define %s\n\n' % (ppguard, ppguard))
for reg in registers:
reg.print_reg_def(file)
for reg in registers:
reg.print_field_defs(file)
file.write('\n#endif /* %s */\n' % ppguard)
file.close()

19
rdb/generator/convert.sh Executable file
View File

@ -0,0 +1,19 @@
#!/bin/sh
set -e
if [ "$#" -ne 1 ]; then
echo >&2 "Usage: $0 EZ-USB_FX3_TRM.pdf"
exit 1
fi
if [ -f "$1" -a -r "$1" ]; then
:
else
echo >&2 "$1 is not a readable file"
exit 1
fi
pdftohtml -s -i -xml -c "$1" trm.xml
python3 `dirname $0`/convert.py
rm trm.xml

436
rdb/gpif.h Normal file
View File

@ -0,0 +1,436 @@
/*
* Copyright (C) 2018 Marcus Comstedt
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef RDB_GPIF_H_
#define RDB_GPIF_H_
#define FX3_GPIF_CONFIG 0xE0014000 /* GPIF Configuration Register */
#define FX3_GPIF_BUS_CONFIG 0xE0014004 /* Bus Configuration Register */
#define FX3_GPIF_BUS_CONFIG2 0xE0014008 /* Bus Configuration Register #2 */
#define FX3_GPIF_AD_CONFIG 0xE001400C /* Address/Data Configuration Register */
#define FX3_GPIF_STATUS 0xE0014010 /* GPIF Status Register */
#define FX3_GPIF_INTR 0xE0014014 /* GPIF Interrupt Request Register */
#define FX3_GPIF_INTR_MASK 0xE0014018 /* GPIF Interrupt Mask Register */
#define FX3_GPIF_SERIAL_IN_CONFIG 0XE001401C /* Serial Input Configuration Register */
#define FX3_GPIF_SERIAL_OUT_CONFIG 0XE0014020 /* Serial Output Configuration Register */
#define FX3_GPIF_CTRL_BUS_DIRECTION 0xE0014024 /* Control Bus In/Out Direction Register */
#define FX3_GPIF_CTRL_BUS_DEFAULT 0xE0014028 /* Control Bus Default Values Register */
#define FX3_GPIF_CTRL_BUS_POLARITY 0xE001402C /* Control Bus SIgnal Polarity Register */
#define FX3_GPIF_CTRL_BUS_TOGGLE 0xE0014030 /* Control Bus Output Toggle Mode Register */
#define FX3_GPIF_CTRL_BUS_SELECT 0xE0014034 /* Control Bus Connection Matrix Register */
#define FX3_GPIF_CTRL_COUNT_CONFIG 0xE0014074 /* Control Counter Configuration Register */
#define FX3_GPIF_CTRL_COUNT_RESET 0xE0014078 /* Control Counter Reset Register */
#define FX3_GPIF_CTRL_COUNT_LIMIT 0xE001407C /* Control Counter Reset Register */
#define FX3_GPIF_ADDR_COUNT_CONFIG 0xE0014080 /* Address Counter Configuration Register */
#define FX3_GPIF_ADDR_COUNT_RESET 0xE0014084 /* Address Counter Reset Register */
#define FX3_GPIF_ADDR_COUNT_LIMIT 0xE0014088 /* Address Counter Limit Register */
#define FX3_GPIF_STATE_COUNT_CONFIG 0xE001408C /* State Counter Configuration Register */
#define FX3_GPIF_STATE_COUNT_LIMIT 0xE0014090 /* State Counter Limit Register */
#define FX3_GPIF_DATA_COUNT_CONFIG 0xE0014094 /* Data Counter Configuration Register */
#define FX3_GPIF_DATA_COUNT_RESET 0xE0014098 /* Data Counter Reset Register */
#define FX3_GPIF_DATA_COUNT_LIMIT 0xE001409C /* Data Counter Limit Register */
#define FX3_GPIF_CTRL_COMP_VALUE 0xE00140A0 /* Control Comparator Value Register */
#define FX3_GPIF_CTRL_COMP_MASK 0xE00140A4 /* Control Comparator Mask Register */
#define FX3_GPIF_DATA_COMP_VALUE 0xE00140A8 /* Data Comparator Value Register */
#define FX3_GPIF_DATA_COMP_MASK 0xE00140AC /* Data Comparator Mask Register */
#define FX3_GPIF_ADDR_COMP_VALUE 0xE00140B0 /* Address Comparator Value Register */
#define FX3_GPIF_ADDR_COMP_MASK 0xE00140B4 /* Address Comparator Mask Register */
#define FX3_GPIF_DATA_CTRL 0xE00140B8 /* Data Control Register */
#define FX3_GPIF_INGRESS_DATA 0xE00140BC /* Socket Ingress Data Register */
#define FX3_GPIF_EGRESS_DATA 0xE00140CC /* Socket Egress Data Register */
#define FX3_GPIF_INGRESS_ADDRESS 0xE00140DC /* Thread Ingress Address Register */
#define FX3_GPIF_EGRESS_ADDRESS 0xE00140EC /* Thread Egress Address Register */
#define FX3_GPIF_THREAD_CONFIG 0xE00140FC /* Thread Configuration Register */
#define FX3_GPIF_LAMBDA_STAT 0xE001410C /* Lambda Status Register */
#define FX3_GPIF_ALPHA_STAT 0xE0014110 /* Alpha Status Register */
#define FX3_GPIF_BETA_STAT 0xE0014114 /* Beta Status Register */
#define FX3_GPIF_WAVEFORM_CTRL_STAT 0xE0014118 /* Waveform Program Control Register */
#define FX3_GPIF_WAVEFORM_SWITCH 0xE001411C /* Waveform Switch Control Register */
#define FX3_GPIF_WAVEFORM_SWITCH_TIMEOUT 0xE0014120 /* Waveform Timeout Register */
#define FX3_GPIF_CRC_CONFIG 0xE0014124 /* CRC Configuration Register */
#define FX3_GPIF_CRC_DATA 0xE0014128 /* CRC Data Register */
#define FX3_GPIF_BETA_DEASSERT 0xE001412C /* Beta Deassert Register */
#define FX3_GPIF_FUNCTION 0xE0014130 /* Transition Function Registers */
#define FX3_GPIF_LEFT_WAVEFORM 0xE0015000 /* Left Edge Waveform Memory Register */
#define FX3_GPIF_RIGHT_WAVEFORM 0xE0016000 /* Right Edge Waveform Memory Register */
#define FX3_GPIF_CONFIG_ENABLE (1UL << 31)
#define FX3_GPIF_CONFIG_PP_MODE (1UL << 30)
#define FX3_GPIF_CONFIG_A7OVERRIDE (1UL << 19)
#define FX3_GPIF_CONFIG_THREAD_IN_STATE (1UL << 15)
#define FX3_GPIF_CONFIG_DATA_COMP_TOGGLE (1UL << 13)
#define FX3_GPIF_CONFIG_CTRL_COMP_TOGGLE (1UL << 12)
#define FX3_GPIF_CONFIG_ADDR_COMP_TOGGLE (1UL << 11)
#define FX3_GPIF_CONFIG_ENDIAN (1UL << 10)
#define FX3_GPIF_CONFIG_SYNC (1UL << 8)
#define FX3_GPIF_CONFIG_DOUT_POP_EN (1UL << 7)
#define FX3_GPIF_CONFIG_DDR_MODE (1UL << 6)
#define FX3_GPIF_CONFIG_CLK_OUT (1UL << 5)
#define FX3_GPIF_CONFIG_CLK_SOURCE (1UL << 4)
#define FX3_GPIF_CONFIG_CLK_INVERT (1UL << 3)
#define FX3_GPIF_CONFIG_DATA_COMP_ENABLE (1UL << 2)
#define FX3_GPIF_CONFIG_ADDR_COMP_ENABLE (1UL << 1)
#define FX3_GPIF_CONFIG_CTRL_COMP_ENABLE (1UL << 0)
#define FX3_GPIF_BUS_CONFIG_FIO1_CONF_SHIFT 28
#define FX3_GPIF_BUS_CONFIG_FIO1_CONF_BITS 4
#define FX3_GPIF_BUS_CONFIG_FIO1_CONF_MASK (0xfUL << 28)
#define FX3_GPIF_BUS_CONFIG_FIO0_CONF_SHIFT 24
#define FX3_GPIF_BUS_CONFIG_FIO0_CONF_BITS 4
#define FX3_GPIF_BUS_CONFIG_FIO0_CONF_MASK (0xfUL << 24)
#define FX3_GPIF_BUS_CONFIG_CE_CLKSTOP (1UL << 23)
#define FX3_GPIF_BUS_CONFIG_INT_CTRL (1UL << 22)
#define FX3_GPIF_BUS_CONFIG_DRQ_ASSERT_MODE (1UL << 20)
#define FX3_GPIF_BUS_CONFIG_DRQ_MODE_SHIFT 18
#define FX3_GPIF_BUS_CONFIG_DRQ_MODE_BITS 2
#define FX3_GPIF_BUS_CONFIG_DRQ_MODE_MASK (0x3UL << 18)
#define FX3_GPIF_BUS_CONFIG_ALE_PRESENT (1UL << 17)
#define FX3_GPIF_BUS_CONFIG_CNTR_PRESENT (1UL << 16)
#define FX3_GPIF_BUS_CONFIG_FIO1_PRESENT (1UL << 15)
#define FX3_GPIF_BUS_CONFIG_FIO0_PRESENT (1UL << 14)
#define FX3_GPIF_BUS_CONFIG_DRQ_PRESENT (1UL << 13)
#define FX3_GPIF_BUS_CONFIG_OE_PRESENT (1UL << 12)
#define FX3_GPIF_BUS_CONFIG_DLE_PRESENT (1UL << 11)
#define FX3_GPIF_BUS_CONFIG_WE_PRESENT (1UL << 10)
#define FX3_GPIF_BUS_CONFIG_CE_PRESENT (1UL << 9)
#define FX3_GPIF_BUS_CONFIG_ADR_CTRL_SHIFT 5
#define FX3_GPIF_BUS_CONFIG_ADR_CTRL_BITS 4
#define FX3_GPIF_BUS_CONFIG_ADR_CTRL_MASK (0xfUL << 5)
#define FX3_GPIF_BUS_CONFIG_MUX_MODE (1UL << 4)
#define FX3_GPIF_BUS_CONFIG_BUS_WIDTH_SHIFT 2
#define FX3_GPIF_BUS_CONFIG_BUS_WIDTH_BITS 2
#define FX3_GPIF_BUS_CONFIG_BUS_WIDTH_MASK (0x3UL << 2)
#define FX3_GPIF_BUS_CONFIG_PIN_COUNT_SHIFT 0
#define FX3_GPIF_BUS_CONFIG_PIN_COUNT_BITS 2
#define FX3_GPIF_BUS_CONFIG_PIN_COUNT_MASK (0x3UL << 0)
#define FX3_GPIF_BUS_CONFIG2_STATE7_SHIFT 24
#define FX3_GPIF_BUS_CONFIG2_STATE7_BITS 5
#define FX3_GPIF_BUS_CONFIG2_STATE7_MASK (0x1fUL << 24)
#define FX3_GPIF_BUS_CONFIG2_STATE6_SHIFT 16
#define FX3_GPIF_BUS_CONFIG2_STATE6_BITS 5
#define FX3_GPIF_BUS_CONFIG2_STATE6_MASK (0x1fUL << 16)
#define FX3_GPIF_BUS_CONFIG2_STATE5_SHIFT 8
#define FX3_GPIF_BUS_CONFIG2_STATE5_BITS 5
#define FX3_GPIF_BUS_CONFIG2_STATE5_MASK (0x1fUL << 8)
#define FX3_GPIF_BUS_CONFIG2_STATE_FROM_CTRL_SHIFT 0
#define FX3_GPIF_BUS_CONFIG2_STATE_FROM_CTRL_BITS 3
#define FX3_GPIF_BUS_CONFIG2_STATE_FROM_CTRL_MASK (0x7UL << 0)
#define FX3_GPIF_AD_CONFIG_DATA_THREAD_SHIFT 18
#define FX3_GPIF_AD_CONFIG_DATA_THREAD_BITS 2
#define FX3_GPIF_AD_CONFIG_DATA_THREAD_MASK (0x3UL << 18)
#define FX3_GPIF_AD_CONFIG_ADDRESS_THREAD_SHIFT 16
#define FX3_GPIF_AD_CONFIG_ADDRESS_THREAD_BITS 2
#define FX3_GPIF_AD_CONFIG_ADDRESS_THREAD_MASK (0x3UL << 16)
#define FX3_GPIF_AD_CONFIG_AIN_DATA (1UL << 9)
#define FX3_GPIF_AD_CONFIG_DOUT_SELECT (1UL << 8)
#define FX3_GPIF_AD_CONFIG_AOUT_SELECT_SHIFT 6
#define FX3_GPIF_AD_CONFIG_AOUT_SELECT_BITS 2
#define FX3_GPIF_AD_CONFIG_AOUT_SELECT_MASK (0x3UL << 6)
#define FX3_GPIF_AD_CONFIG_AIN_SELECT_SHIFT 4
#define FX3_GPIF_AD_CONFIG_AIN_SELECT_BITS 2
#define FX3_GPIF_AD_CONFIG_AIN_SELECT_MASK (0x3UL << 4)
#define FX3_GPIF_AD_CONFIG_A_OEN_CFG_SHIFT 2
#define FX3_GPIF_AD_CONFIG_A_OEN_CFG_BITS 2
#define FX3_GPIF_AD_CONFIG_A_OEN_CFG_MASK (0x3UL << 2)
#define FX3_GPIF_AD_CONFIG_DQ_OEN_CFG_SHIFT 0
#define FX3_GPIF_AD_CONFIG_DQ_OEN_CFG_BITS 2
#define FX3_GPIF_AD_CONFIG_DQ_OEN_CFG_MASK (0x3UL << 0)
#define FX3_GPIF_STATUS_INTERRUPT_STATE_SHIFT 24
#define FX3_GPIF_STATUS_INTERRUPT_STATE_BITS 8
#define FX3_GPIF_STATUS_INTERRUPT_STATE_MASK (0xffUL << 24)
#define FX3_GPIF_STATUS_IN_DATA_VALID_SHIFT 20
#define FX3_GPIF_STATUS_IN_DATA_VALID_BITS 4
#define FX3_GPIF_STATUS_IN_DATA_VALID_MASK (0xfUL << 20)
#define FX3_GPIF_STATUS_EG_DATA_EMPTY_SHIFT 16
#define FX3_GPIF_STATUS_EG_DATA_EMPTY_BITS 4
#define FX3_GPIF_STATUS_EG_DATA_EMPTY_MASK (0xfUL << 16)
#define FX3_GPIF_STATUS_WAVEFORM_BUSY (1UL << 10)
#define FX3_GPIF_STATUS_CTRL_COMP_HIT (1UL << 9)
#define FX3_GPIF_STATUS_DATA_COMP_HIT (1UL << 8)
#define FX3_GPIF_STATUS_ADDR_COMP_HIT (1UL << 7)
#define FX3_GPIF_STATUS_CTRL_COUNT_HIT (1UL << 6)
#define FX3_GPIF_STATUS_DATA_COUNT_HIT (1UL << 5)
#define FX3_GPIF_STATUS_ADDR_COUNT_HIT (1UL << 4)
#define FX3_GPIF_STATUS_CRC_ERROR (1UL << 3)
#define FX3_GPIF_STATUS_SWITCH_TIMEOUT (1UL << 2)
#define FX3_GPIF_STATUS_GPIF_INTR (1UL << 1)
#define FX3_GPIF_STATUS_GPIF_DONE (1UL << 0)
#define FX3_GPIF_INTR_IN_DATA_VALID_SHIFT 20
#define FX3_GPIF_INTR_IN_DATA_VALID_BITS 4
#define FX3_GPIF_INTR_IN_DATA_VALID_MASK (0xfUL << 20)
#define FX3_GPIF_INTR_EG_DATA_EMPTY_SHIFT 16
#define FX3_GPIF_INTR_EG_DATA_EMPTY_BITS 4
#define FX3_GPIF_INTR_EG_DATA_EMPTY_MASK (0xfUL << 16)
#define FX3_GPIF_INTR_WAVEFORM_BUSY (1UL << 10)
#define FX3_GPIF_INTR_CTRL_COMP_HIT (1UL << 9)
#define FX3_GPIF_INTR_DATA_COMP_HIT (1UL << 8)
#define FX3_GPIF_INTR_ADDR_COMP_HIT (1UL << 7)
#define FX3_GPIF_INTR_CTRL_COUNT_HIT (1UL << 6)
#define FX3_GPIF_INTR_DATA_COUNT_HIT (1UL << 5)
#define FX3_GPIF_INTR_ADDR_COUNT_HIT (1UL << 4)
#define FX3_GPIF_INTR_CRC_ERROR (1UL << 3)
#define FX3_GPIF_INTR_SWITCH_TIMEOUT (1UL << 2)
#define FX3_GPIF_INTR_GPIF_INTR (1UL << 1)
#define FX3_GPIF_INTR_GPIF_DONE (1UL << 0)
#define FX3_GPIF_INTR_MASK_IN_DATA_VALID_SHIFT 20
#define FX3_GPIF_INTR_MASK_IN_DATA_VALID_BITS 4
#define FX3_GPIF_INTR_MASK_IN_DATA_VALID_MASK (0xfUL << 20)
#define FX3_GPIF_INTR_MASK_EG_DATA_EMPTY_SHIFT 16
#define FX3_GPIF_INTR_MASK_EG_DATA_EMPTY_BITS 4
#define FX3_GPIF_INTR_MASK_EG_DATA_EMPTY_MASK (0xfUL << 16)
#define FX3_GPIF_INTR_MASK_WAVEFORM_BUSY (1UL << 10)
#define FX3_GPIF_INTR_MASK_CTRL_COMP_HIT (1UL << 9)
#define FX3_GPIF_INTR_MASK_DATA_COMP_HIT (1UL << 8)
#define FX3_GPIF_INTR_MASK_ADDR_COMP_HIT (1UL << 7)
#define FX3_GPIF_INTR_MASK_CTRL_COUNT_HIT (1UL << 6)
#define FX3_GPIF_INTR_MASK_DATA_COUNT_HIT (1UL << 5)
#define FX3_GPIF_INTR_MASK_ADDR_COUNT_HIT (1UL << 4)
#define FX3_GPIF_INTR_MASK_CRC_ERROR (1UL << 3)
#define FX3_GPIF_INTR_MASK_SWITCH_TIMEOUT (1UL << 2)
#define FX3_GPIF_INTR_MASK_GPIF_INTR (1UL << 1)
#define FX3_GPIF_INTR_MASK_GPIF_DONE (1UL << 0)
#define FX3_GPIF_CTRL_BUS_DEFAULT_DEFAULT_SHIFT 0
#define FX3_GPIF_CTRL_BUS_DEFAULT_DEFAULT_BITS 16
#define FX3_GPIF_CTRL_BUS_DEFAULT_DEFAULT_MASK (0xffffUL << 0)
#define FX3_GPIF_CTRL_BUS_POLARITY_POLARITY_SHIFT 0
#define FX3_GPIF_CTRL_BUS_POLARITY_POLARITY_BITS 16
#define FX3_GPIF_CTRL_BUS_POLARITY_POLARITY_MASK (0xffffUL << 0)
#define FX3_GPIF_CTRL_BUS_TOGGLE_TOGGLE_SHIFT 0
#define FX3_GPIF_CTRL_BUS_TOGGLE_TOGGLE_BITS 16
#define FX3_GPIF_CTRL_BUS_TOGGLE_TOGGLE_MASK (0xffffUL << 0)
#define FX3_GPIF_CTRL_BUS_SELECT_OMEGA_INDEX_SHIFT 0
#define FX3_GPIF_CTRL_BUS_SELECT_OMEGA_INDEX_BITS 5
#define FX3_GPIF_CTRL_BUS_SELECT_OMEGA_INDEX_MASK (0x1fUL << 0)
#define FX3_GPIF_CTRL_COUNT_CONFIG_CONNECT_SHIFT 4
#define FX3_GPIF_CTRL_COUNT_CONFIG_CONNECT_BITS 4
#define FX3_GPIF_CTRL_COUNT_CONFIG_CONNECT_MASK (0xfUL << 4)
#define FX3_GPIF_CTRL_COUNT_CONFIG_SW_RESET (1UL << 3)
#define FX3_GPIF_CTRL_COUNT_CONFIG_RELOAD (1UL << 2)
#define FX3_GPIF_CTRL_COUNT_CONFIG_DOWN_UP (1UL << 1)
#define FX3_GPIF_CTRL_COUNT_CONFIG_ENABLE (1UL << 0)
#define FX3_GPIF_CTRL_COUNT_RESET_RESET_LOAD_SHIFT 0
#define FX3_GPIF_CTRL_COUNT_RESET_RESET_LOAD_BITS 16
#define FX3_GPIF_CTRL_COUNT_RESET_RESET_LOAD_MASK (0xffffUL << 0)
#define FX3_GPIF_CTRL_COUNT_LIMIT_LIMIT_SHIFT 0
#define FX3_GPIF_CTRL_COUNT_LIMIT_LIMIT_BITS 16
#define FX3_GPIF_CTRL_COUNT_LIMIT_LIMIT_MASK (0xffffUL << 0)
#define FX3_GPIF_ADDR_COUNT_CONFIG_INCREMENT_SHIFT 8
#define FX3_GPIF_ADDR_COUNT_CONFIG_INCREMENT_BITS 8
#define FX3_GPIF_ADDR_COUNT_CONFIG_INCREMENT_MASK (0xffUL << 8)
#define FX3_GPIF_ADDR_COUNT_CONFIG_DOWN_UP (1UL << 3)
#define FX3_GPIF_ADDR_COUNT_CONFIG_SW_RESET (1UL << 2)
#define FX3_GPIF_ADDR_COUNT_CONFIG_RELOAD (1UL << 1)
#define FX3_GPIF_ADDR_COUNT_CONFIG_ENABLE (1UL << 0)
#define FX3_GPIF_STATE_COUNT_CONFIG_SW_RESET (1UL << 1)
#define FX3_GPIF_STATE_COUNT_CONFIG_ENABLE (1UL << 0)
#define FX3_GPIF_STATE_COUNT_LIMIT_LIMIT_SHIFT 0
#define FX3_GPIF_STATE_COUNT_LIMIT_LIMIT_BITS 16
#define FX3_GPIF_STATE_COUNT_LIMIT_LIMIT_MASK (0xffffUL << 0)
#define FX3_GPIF_DATA_COUNT_CONFIG_INCREMENT_SHIFT 8
#define FX3_GPIF_DATA_COUNT_CONFIG_INCREMENT_BITS 8
#define FX3_GPIF_DATA_COUNT_CONFIG_INCREMENT_MASK (0xffUL << 8)
#define FX3_GPIF_DATA_COUNT_CONFIG_DOWN_UP (1UL << 3)
#define FX3_GPIF_DATA_COUNT_CONFIG_SW_RESET (1UL << 2)
#define FX3_GPIF_DATA_COUNT_CONFIG_RELOAD (1UL << 1)
#define FX3_GPIF_DATA_COUNT_CONFIG_ENABLE (1UL << 0)
#define FX3_GPIF_CTRL_COMP_VALUE_VALUE_SHIFT 0
#define FX3_GPIF_CTRL_COMP_VALUE_VALUE_BITS 16
#define FX3_GPIF_CTRL_COMP_VALUE_VALUE_MASK (0xffffUL << 0)
#define FX3_GPIF_CTRL_COMP_MASK_MASK_SHIFT 0
#define FX3_GPIF_CTRL_COMP_MASK_MASK_BITS 16
#define FX3_GPIF_CTRL_COMP_MASK_MASK_MASK (0xffffUL << 0)
#define FX3_GPIF_DATA_CTRL_EG_ADDR_VALID_SHIFT 12
#define FX3_GPIF_DATA_CTRL_EG_ADDR_VALID_BITS 4
#define FX3_GPIF_DATA_CTRL_EG_ADDR_VALID_MASK (0xfUL << 12)
#define FX3_GPIF_DATA_CTRL_IN_ADDR_VALID_SHIFT 8
#define FX3_GPIF_DATA_CTRL_IN_ADDR_VALID_BITS 4
#define FX3_GPIF_DATA_CTRL_IN_ADDR_VALID_MASK (0xfUL << 8)
#define FX3_GPIF_DATA_CTRL_EG_DATA_VALID_SHIFT 4
#define FX3_GPIF_DATA_CTRL_EG_DATA_VALID_BITS 4
#define FX3_GPIF_DATA_CTRL_EG_DATA_VALID_MASK (0xfUL << 4)
#define FX3_GPIF_DATA_CTRL_IN_DATA_VALID_SHIFT 0
#define FX3_GPIF_DATA_CTRL_IN_DATA_VALID_BITS 4
#define FX3_GPIF_DATA_CTRL_IN_DATA_VALID_MASK (0xfUL << 0)
#define FX3_GPIF_THREAD_CONFIG_ENABLE (1UL << 31)
#define FX3_GPIF_THREAD_CONFIG_WATERMARK_SHIFT 16
#define FX3_GPIF_THREAD_CONFIG_WATERMARK_BITS 14
#define FX3_GPIF_THREAD_CONFIG_WATERMARK_MASK (0x3fffUL << 16)
#define FX3_GPIF_THREAD_CONFIG_BURST_SIZE_SHIFT 8
#define FX3_GPIF_THREAD_CONFIG_BURST_SIZE_BITS 4
#define FX3_GPIF_THREAD_CONFIG_BURST_SIZE_MASK (0xfUL << 8)
#define FX3_GPIF_THREAD_CONFIG_WM_CFG (1UL << 7)
#define FX3_GPIF_THREAD_CONFIG_THREAD_SOCK_SHIFT 0
#define FX3_GPIF_THREAD_CONFIG_THREAD_SOCK_BITS 5
#define FX3_GPIF_THREAD_CONFIG_THREAD_SOCK_MASK (0x1fUL << 0)
#define FX3_GPIF_ALPHA_STAT_ALPHA_SHIFT 0
#define FX3_GPIF_ALPHA_STAT_ALPHA_BITS 8
#define FX3_GPIF_ALPHA_STAT_ALPHA_MASK (0xffUL << 0)
#define FX3_GPIF_WAVEFORM_CTRL_STAT_CURRENT_STATE_SHIFT 24
#define FX3_GPIF_WAVEFORM_CTRL_STAT_CURRENT_STATE_BITS 8
#define FX3_GPIF_WAVEFORM_CTRL_STAT_CURRENT_STATE_MASK (0xffUL << 24)
#define FX3_GPIF_WAVEFORM_CTRL_STAT_ALPHA_INIT_SHIFT 16
#define FX3_GPIF_WAVEFORM_CTRL_STAT_ALPHA_INIT_BITS 8
#define FX3_GPIF_WAVEFORM_CTRL_STAT_ALPHA_INIT_MASK (0xffUL << 16)
#define FX3_GPIF_WAVEFORM_CTRL_STAT_CPU_LAMBDA (1UL << 11)
#define FX3_GPIF_WAVEFORM_CTRL_STAT_GPIF_STAT_SHIFT 8
#define FX3_GPIF_WAVEFORM_CTRL_STAT_GPIF_STAT_BITS 3
#define FX3_GPIF_WAVEFORM_CTRL_STAT_GPIF_STAT_MASK (0x7UL << 8)
#define FX3_GPIF_WAVEFORM_CTRL_STAT_PAUSE (1UL << 1)
#define FX3_GPIF_WAVEFORM_CTRL_STAT_WAVEFORM_VALID (1UL << 0)
#define FX3_GPIF_WAVEFORM_SWITCH_DONE_STATE_SHIFT 24
#define FX3_GPIF_WAVEFORM_SWITCH_DONE_STATE_BITS 8
#define FX3_GPIF_WAVEFORM_SWITCH_DONE_STATE_MASK (0xffUL << 24)
#define FX3_GPIF_WAVEFORM_SWITCH_DESTINATION_STATE_SHIFT 16
#define FX3_GPIF_WAVEFORM_SWITCH_DESTINATION_STATE_BITS 8
#define FX3_GPIF_WAVEFORM_SWITCH_DESTINATION_STATE_MASK (0xffUL << 16)
#define FX3_GPIF_WAVEFORM_SWITCH_TERMINAL_STATE_SHIFT 8
#define FX3_GPIF_WAVEFORM_SWITCH_TERMINAL_STATE_BITS 8
#define FX3_GPIF_WAVEFORM_SWITCH_TERMINAL_STATE_MASK (0xffUL << 8)
#define FX3_GPIF_WAVEFORM_SWITCH_TERMINATED (1UL << 7)
#define FX3_GPIF_WAVEFORM_SWITCH_TIMEOUT_REACHED (1UL << 6)
#define FX3_GPIF_WAVEFORM_SWITCH_TIMEOUT_MODE_SHIFT 3
#define FX3_GPIF_WAVEFORM_SWITCH_TIMEOUT_MODE_BITS 3
#define FX3_GPIF_WAVEFORM_SWITCH_TIMEOUT_MODE_MASK (0x7UL << 3)
#define FX3_GPIF_WAVEFORM_SWITCH_SWITCH_NOW (1UL << 2)
#define FX3_GPIF_WAVEFORM_SWITCH_DONE_ENABLE (1UL << 1)
#define FX3_GPIF_WAVEFORM_SWITCH_WAVEFORM_SWITCH (1UL << 0)
#define FX3_GPIF_CRC_CONFIG_ENABLE (1UL << 31)
#define FX3_GPIF_CRC_CONFIG_CRC_ERROR (1UL << 22)
#define FX3_GPIF_CRC_CONFIG_BYTE_ENDIAN (1UL << 21)
#define FX3_GPIF_CRC_CONFIG_BIT_ENDIAN (1UL << 20)
#define FX3_GPIF_CRC_CONFIG_CRC_RECEIVED_SHIFT 0
#define FX3_GPIF_CRC_CONFIG_CRC_RECEIVED_BITS 16
#define FX3_GPIF_CRC_CONFIG_CRC_RECEIVED_MASK (0xffffUL << 0)
#define FX3_GPIF_CRC_DATA_CRC_VALUE_SHIFT 16
#define FX3_GPIF_CRC_DATA_CRC_VALUE_BITS 16
#define FX3_GPIF_CRC_DATA_CRC_VALUE_MASK (0xffffUL << 16)
#define FX3_GPIF_CRC_DATA_INITIAL_VALUE_SHIFT 0
#define FX3_GPIF_CRC_DATA_INITIAL_VALUE_BITS 16
#define FX3_GPIF_CRC_DATA_INITIAL_VALUE_MASK (0xffffUL << 0)
#define FX3_GPIF_FUNCTION_FUNCTION_SHIFT 0
#define FX3_GPIF_FUNCTION_FUNCTION_BITS 16
#define FX3_GPIF_FUNCTION_FUNCTION_MASK (0xffffUL << 0)
#define FX3_GPIF_LEFT_WAVEFORM_UNUSED_SHIFT 96
#define FX3_GPIF_LEFT_WAVEFORM_UNUSED_BITS 32
#define FX3_GPIF_LEFT_WAVEFORM_UNUSED_MASK (0xffffffffUL << 96)
#define FX3_GPIF_LEFT_WAVEFORM_VALID (1UL << 95)
#define FX3_GPIF_LEFT_WAVEFORM_BETA_DEASSERT (1UL << 94)
#define FX3_GPIF_LEFT_WAVEFORM_REPEAT_COUNT_SHIFT 86
#define FX3_GPIF_LEFT_WAVEFORM_REPEAT_COUNT_BITS 8
#define FX3_GPIF_LEFT_WAVEFORM_REPEAT_COUNT_MASK (0xffUL << 86)
#define FX3_GPIF_LEFT_WAVEFORM_Beta_SHIFT 54
#define FX3_GPIF_LEFT_WAVEFORM_Beta_BITS 32
#define FX3_GPIF_LEFT_WAVEFORM_Beta_MASK (0xffffffffUL << 54)
#define FX3_GPIF_LEFT_WAVEFORM_Alpha_Right_SHIFT 46
#define FX3_GPIF_LEFT_WAVEFORM_Alpha_Right_BITS 8
#define FX3_GPIF_LEFT_WAVEFORM_Alpha_Right_MASK (0xffUL << 46)
#define FX3_GPIF_LEFT_WAVEFORM_Alpha_Left_SHIFT 38
#define FX3_GPIF_LEFT_WAVEFORM_Alpha_Left_BITS 8
#define FX3_GPIF_LEFT_WAVEFORM_Alpha_Left_MASK (0xffUL << 38)
#define FX3_GPIF_LEFT_WAVEFORM_f1_SHIFT 33
#define FX3_GPIF_LEFT_WAVEFORM_f1_BITS 5
#define FX3_GPIF_LEFT_WAVEFORM_f1_MASK (0x1fUL << 33)
#define FX3_GPIF_LEFT_WAVEFORM_f0_SHIFT 28
#define FX3_GPIF_LEFT_WAVEFORM_f0_BITS 5
#define FX3_GPIF_LEFT_WAVEFORM_f0_MASK (0x1fUL << 28)
#define FX3_GPIF_LEFT_WAVEFORM_Fd_SHIFT 23
#define FX3_GPIF_LEFT_WAVEFORM_Fd_BITS 5
#define FX3_GPIF_LEFT_WAVEFORM_Fd_MASK (0x1fUL << 23)
#define FX3_GPIF_LEFT_WAVEFORM_Fc_SHIFT 18
#define FX3_GPIF_LEFT_WAVEFORM_Fc_BITS 5
#define FX3_GPIF_LEFT_WAVEFORM_Fc_MASK (0x1fUL << 18)
#define FX3_GPIF_LEFT_WAVEFORM_Fb_SHIFT 13
#define FX3_GPIF_LEFT_WAVEFORM_Fb_BITS 5
#define FX3_GPIF_LEFT_WAVEFORM_Fb_MASK (0x1fUL << 13)
#define FX3_GPIF_LEFT_WAVEFORM_Fa_SHIFT 8
#define FX3_GPIF_LEFT_WAVEFORM_Fa_BITS 5
#define FX3_GPIF_LEFT_WAVEFORM_Fa_MASK (0x1fUL << 8)
#define FX3_GPIF_LEFT_WAVEFORM_NEXT_STATE_SHIFT 0
#define FX3_GPIF_LEFT_WAVEFORM_NEXT_STATE_BITS 8
#define FX3_GPIF_LEFT_WAVEFORM_NEXT_STATE_MASK (0xffUL << 0)
#define FX3_GPIF_RIGHT_WAVEFORM_UNUSED_SHIFT 96
#define FX3_GPIF_RIGHT_WAVEFORM_UNUSED_BITS 32
#define FX3_GPIF_RIGHT_WAVEFORM_UNUSED_MASK (0xffffffffUL << 96)
#define FX3_GPIF_RIGHT_WAVEFORM_VALID (1UL << 95)
#define FX3_GPIF_RIGHT_WAVEFORM_BETA_DEASSERT (1UL << 94)
#define FX3_GPIF_RIGHT_WAVEFORM_REPEAT_COUNT_SHIFT 86
#define FX3_GPIF_RIGHT_WAVEFORM_REPEAT_COUNT_BITS 8
#define FX3_GPIF_RIGHT_WAVEFORM_REPEAT_COUNT_MASK (0xffUL << 86)
#define FX3_GPIF_RIGHT_WAVEFORM_Beta_SHIFT 54
#define FX3_GPIF_RIGHT_WAVEFORM_Beta_BITS 32
#define FX3_GPIF_RIGHT_WAVEFORM_Beta_MASK (0xffffffffUL << 54)
#define FX3_GPIF_RIGHT_WAVEFORM_Alpha_Right_SHIFT 46
#define FX3_GPIF_RIGHT_WAVEFORM_Alpha_Right_BITS 8
#define FX3_GPIF_RIGHT_WAVEFORM_Alpha_Right_MASK (0xffUL << 46)
#define FX3_GPIF_RIGHT_WAVEFORM_Alpha_Left_SHIFT 38
#define FX3_GPIF_RIGHT_WAVEFORM_Alpha_Left_BITS 8
#define FX3_GPIF_RIGHT_WAVEFORM_Alpha_Left_MASK (0xffUL << 38)
#define FX3_GPIF_RIGHT_WAVEFORM_f1_SHIFT 33
#define FX3_GPIF_RIGHT_WAVEFORM_f1_BITS 5
#define FX3_GPIF_RIGHT_WAVEFORM_f1_MASK (0x1fUL << 33)
#define FX3_GPIF_RIGHT_WAVEFORM_f0_SHIFT 28
#define FX3_GPIF_RIGHT_WAVEFORM_f0_BITS 5
#define FX3_GPIF_RIGHT_WAVEFORM_f0_MASK (0x1fUL << 28)
#define FX3_GPIF_RIGHT_WAVEFORM_Fd_SHIFT 23
#define FX3_GPIF_RIGHT_WAVEFORM_Fd_BITS 5
#define FX3_GPIF_RIGHT_WAVEFORM_Fd_MASK (0x1fUL << 23)
#define FX3_GPIF_RIGHT_WAVEFORM_Fc_SHIFT 18
#define FX3_GPIF_RIGHT_WAVEFORM_Fc_BITS 5
#define FX3_GPIF_RIGHT_WAVEFORM_Fc_MASK (0x1fUL << 18)
#define FX3_GPIF_RIGHT_WAVEFORM_Fb_SHIFT 13
#define FX3_GPIF_RIGHT_WAVEFORM_Fb_BITS 5
#define FX3_GPIF_RIGHT_WAVEFORM_Fb_MASK (0x1fUL << 13)
#define FX3_GPIF_RIGHT_WAVEFORM_Fa_SHIFT 8
#define FX3_GPIF_RIGHT_WAVEFORM_Fa_BITS 5
#define FX3_GPIF_RIGHT_WAVEFORM_Fa_MASK (0x1fUL << 8)
#define FX3_GPIF_RIGHT_WAVEFORM_NEXT_STATE_SHIFT 0
#define FX3_GPIF_RIGHT_WAVEFORM_NEXT_STATE_BITS 8
#define FX3_GPIF_RIGHT_WAVEFORM_NEXT_STATE_MASK (0xffUL << 0)
#endif /* RDB_GPIF_H_ */

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/*
* Copyright (C) 2018 Marcus Comstedt
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef RDB_GPIO_H_
#define RDB_GPIO_H_
#define FX3_PIN_STATUS 0xE0001000 /* Configuration, mode and status of IO Pin */
#define FX3_PIN_TIMER 0xE0001004 /* Timer/counter for pulse and measurement modes */
#define FX3_PIN_PERIOD 0xE0001008 /* Period length for revolving counter GPIO_TIMER */
#define FX3_PIN_THRESHOLD 0xE000100C /* Threshold or Measurement Register */
#define FX3_GPIO_SIMPLE 0xE0001100 /* Simple General Purpose IO Register (one pin) */
#define FX3_GPIO_INVALUE0 0xE00013D0 /* GPIO Input Value Vector */
#define FX3_GPIO_INVALUE1 0xE00013D4 /* GPIO Input Value Vector */
#define FX3_GPIO_INTR0 0xE00013E0 /* GPIO Interrupt Vector */
#define FX3_GPIO_INTR1 0xE00013E4 /* GPIO Interrupt Vector */
#define FX3_GPIO_INTR 0xE00013E8 /* GPIO Interrupt Vector for PINs */
#define FX3_GPIO_ID 0xE00013F0 /* Block Identification and Version Number */
#define FX3_GPIO_POWER 0xE00013F4 /* Power, Clock, and Reset Control */
#define FX3_PIN_STATUS_ENABLE (1UL << 31)
#define FX3_PIN_STATUS_TIMER_MODE_SHIFT 28
#define FX3_PIN_STATUS_TIMER_MODE_BITS 3
#define FX3_PIN_STATUS_TIMER_MODE_MASK (0x7UL << 28)
#define FX3_PIN_STATUS_INTR (1UL << 27)
#define FX3_PIN_STATUS_INTRMODE_SHIFT 24
#define FX3_PIN_STATUS_INTRMODE_BITS 3
#define FX3_PIN_STATUS_INTRMODE_MASK (0x7UL << 24)
#define FX3_PIN_STATUS_MODE_SHIFT 8
#define FX3_PIN_STATUS_MODE_BITS 4
#define FX3_PIN_STATUS_MODE_MASK (0xfUL << 8)
#define FX3_PIN_STATUS_INPUT_EN (1UL << 6)
#define FX3_PIN_STATUS_DRIVE_HI_EN (1UL << 5)
#define FX3_PIN_STATUS_DRIVE_LO_EN (1UL << 4)
#define FX3_PIN_STATUS_IN_VALUE (1UL << 1)
#define FX3_PIN_STATUS_OUT_VALUE (1UL << 0)
#define FX3_GPIO_SIMPLE_ENABLE (1UL << 31)
#define FX3_GPIO_SIMPLE_INTR (1UL << 27)
#define FX3_GPIO_SIMPLE_INTRMODE_SHIFT 24
#define FX3_GPIO_SIMPLE_INTRMODE_BITS 3
#define FX3_GPIO_SIMPLE_INTRMODE_MASK (0x7UL << 24)
#define FX3_GPIO_SIMPLE_INPUT_EN (1UL << 6)
#define FX3_GPIO_SIMPLE_DRIVE_HI_EN (1UL << 5)
#define FX3_GPIO_SIMPLE_DRIVE_LO_EN (1UL << 4)
#define FX3_GPIO_SIMPLE_IN_VALUE (1UL << 1)
#define FX3_GPIO_SIMPLE_OUT_VALUE (1UL << 0)
#define FX3_GPIO_INVALUE1_INVALUE1_SHIFT 0
#define FX3_GPIO_INVALUE1_INVALUE1_BITS 29
#define FX3_GPIO_INVALUE1_INVALUE1_MASK (0x1fffffffUL << 0)
#define FX3_GPIO_INTR1_INTR1_SHIFT 0
#define FX3_GPIO_INTR1_INTR1_BITS 29
#define FX3_GPIO_INTR1_INTR1_MASK (0x1fffffffUL << 0)
#define FX3_GPIO_INTR_INTR7 (1UL << 7)
#define FX3_GPIO_INTR_INTR6 (1UL << 6)
#define FX3_GPIO_INTR_INTR5 (1UL << 5)
#define FX3_GPIO_INTR_INTR4 (1UL << 4)
#define FX3_GPIO_INTR_INTR3 (1UL << 3)
#define FX3_GPIO_INTR_INTR2 (1UL << 2)
#define FX3_GPIO_INTR_INTR1 (1UL << 1)
#define FX3_GPIO_INTR_INTR0 (1UL << 0)
#define FX3_GPIO_ID_BLOCK_VERSION_SHIFT 16
#define FX3_GPIO_ID_BLOCK_VERSION_BITS 16
#define FX3_GPIO_ID_BLOCK_VERSION_MASK (0xffffUL << 16)
#define FX3_GPIO_ID_BLOCK_ID_SHIFT 0
#define FX3_GPIO_ID_BLOCK_ID_BITS 16
#define FX3_GPIO_ID_BLOCK_ID_MASK (0xffffUL << 0)
#define FX3_GPIO_POWER_RESETN (1UL << 31)
#define FX3_GPIO_POWER_ACTIVE (1UL << 0)
#endif /* RDB_GPIO_H_ */

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/*
* Copyright (C) 2018 Marcus Comstedt
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef RDB_I2C_H_
#define RDB_I2C_H_
#define FX3_I2C_CONFIG 0xE0000400 /* I²C Configuration and Mode Register */
#define FX3_I2C_STATUS 0xE0000404 /* I²C Status Register */
#define FX3_I2C_INTR 0xE0000408 /* I²C Interrupt Request Register */
#define FX3_I2C_INTR_MASK 0xE000040C /* I²C Interrupt Mask Register */
#define FX3_I2C_TIMEOUT 0xE0000410 /* Timeout Register */
#define FX3_I2C_DMA_TIMEOUT 0xE0000414 /* DMA Timeout Register */
#define FX3_I2C_PREAMBLE_CTRL 0xE0000418 /* I²C Preamble Control Register */
#define FX3_I2C_PREAMBLE_DATA 0xE000041C /* I²C Preamble Data Register */
#define FX3_I2C_PREAMBLE_RPT 0xE0000424 /* I²C Preamble Repeat Register */
#define FX3_I2C_COMMAND 0xE0000428 /* I²C Command Register */
#define FX3_I2C_EGRESS_DATA 0xE000042C /* I²C Egress Data Register */
#define FX3_I2C_INGRESS_DATA 0xE0000430 /* I²C Ingress Data Register */
#define FX3_I2C_CLOCK_LOW_COUNT 0xE0000434 /* I²C Clock Low Count Register */
#define FX3_I2C_BYTE_COUNT 0xE0000438 /* I²C Byte Count Register */
#define FX3_I2C_BYTES_TRANSFERRED 0xE000043C /* Number of Bytes Transferred in the Data Phase */
#define FX3_I2C_SOCKET 0xE0000440 /* I²C Socket Register */
#define FX3_I2C_ID 0xE00007F0 /* Block Identification and Version Number */
#define FX3_I2C_POWER 0xE00007F4 /* Power, Clock, and Reset Control */
#define FX3_I2C_CONFIG_ENABLE (1UL << 31)
#define FX3_I2C_CONFIG_TX_CLEAR (1UL << 30)
#define FX3_I2C_CONFIG_RX_CLEAR (1UL << 29)
#define FX3_I2C_CONFIG_I2C_100KHz (1UL << 2)
#define FX3_I2C_CONFIG_CONTINUE_ON_NACK (1UL << 1)
#define FX3_I2C_CONFIG_DMA_MODE (1UL << 0)
#define FX3_I2C_STATUS_SDA_STAT (1UL << 31)
#define FX3_I2C_STATUS_SCL_STAT (1UL << 30)
#define FX3_I2C_STATUS_BUS_BUSY (1UL << 29)
#define FX3_I2C_STATUS_BUSY (1UL << 28)
#define FX3_I2C_STATUS_ERROR_CODE_SHIFT 24
#define FX3_I2C_STATUS_ERROR_CODE_BITS 4
#define FX3_I2C_STATUS_ERROR_CODE_MASK (0xfUL << 24)
#define FX3_I2C_STATUS_ERROR (1UL << 8)
#define FX3_I2C_STATUS_LOST_ARBITRATION (1UL << 7)
#define FX3_I2C_STATUS_TIMEOUT (1UL << 6)
#define FX3_I2C_STATUS_TX_HALF (1UL << 5)
#define FX3_I2C_STATUS_TX_SPACE (1UL << 4)
#define FX3_I2C_STATUS_TX_DONE (1UL << 3)
#define FX3_I2C_STATUS_RX_HALF (1UL << 2)
#define FX3_I2C_STATUS_RX_DATA (1UL << 1)
#define FX3_I2C_STATUS_RX_DONE (1UL << 0)
#define FX3_I2C_INTR_ERROR (1UL << 8)
#define FX3_I2C_INTR_LOST_ARBITRATION (1UL << 7)
#define FX3_I2C_INTR_TIMEOUT (1UL << 6)
#define FX3_I2C_INTR_TX_HALF (1UL << 5)
#define FX3_I2C_INTR_TX_SPACE (1UL << 4)
#define FX3_I2C_INTR_TX_DONE (1UL << 3)
#define FX3_I2C_INTR_RX_HALF (1UL << 2)
#define FX3_I2C_INTR_RX_DATA (1UL << 1)
#define FX3_I2C_INTR_RX_DONE (1UL << 0)
#define FX3_I2C_INTR_MASK_ERROR (1UL << 8)
#define FX3_I2C_INTR_MASK_LOST_ARBITRATION (1UL << 7)
#define FX3_I2C_INTR_MASK_TIMEOUT (1UL << 6)
#define FX3_I2C_INTR_MASK_TX_HALF (1UL << 5)
#define FX3_I2C_INTR_MASK_TX_SPACE (1UL << 4)
#define FX3_I2C_INTR_MASK_TX_DONE (1UL << 3)
#define FX3_I2C_INTR_MASK_RX_HALF (1UL << 2)
#define FX3_I2C_INTR_MASK_RX_DATA (1UL << 1)
#define FX3_I2C_INTR_MASK_RX_DONE (1UL << 0)
#define FX3_I2C_DMA_TIMEOUT_TIMEOUT16_SHIFT 0
#define FX3_I2C_DMA_TIMEOUT_TIMEOUT16_BITS 16
#define FX3_I2C_DMA_TIMEOUT_TIMEOUT16_MASK (0xffffUL << 0)
#define FX3_I2C_PREAMBLE_CTRL_STOP_SHIFT 8
#define FX3_I2C_PREAMBLE_CTRL_STOP_BITS 8
#define FX3_I2C_PREAMBLE_CTRL_STOP_MASK (0xffUL << 8)
#define FX3_I2C_PREAMBLE_CTRL_START_SHIFT 0
#define FX3_I2C_PREAMBLE_CTRL_START_BITS 8
#define FX3_I2C_PREAMBLE_CTRL_START_MASK (0xffUL << 0)
#define FX3_I2C_PREAMBLE_DATA_DATA_SHIFT 0
#define FX3_I2C_PREAMBLE_DATA_DATA_BITS 64
#define FX3_I2C_PREAMBLE_DATA_DATA_MASK (0xffffffffffffffffUL << 0)
#define FX3_I2C_PREAMBLE_RPT_COUNT_SHIFT 8
#define FX3_I2C_PREAMBLE_RPT_COUNT_BITS 24
#define FX3_I2C_PREAMBLE_RPT_COUNT_MASK (0xffffffUL << 8)
#define FX3_I2C_PREAMBLE_RPT_STOP_ON_NACK (1UL << 2)
#define FX3_I2C_PREAMBLE_RPT_STOP_ON_ACK (1UL << 1)
#define FX3_I2C_PREAMBLE_RPT_RPT_ENABLE (1UL << 0)
#define FX3_I2C_COMMAND_I2C_STAT_SHIFT 30
#define FX3_I2C_COMMAND_I2C_STAT_BITS 2
#define FX3_I2C_COMMAND_I2C_STAT_MASK (0x3UL << 30)
#define FX3_I2C_COMMAND_READ (1UL << 28)
#define FX3_I2C_COMMAND_START_FIRST (1UL << 7)
#define FX3_I2C_COMMAND_STOP_LAST (1UL << 6)
#define FX3_I2C_COMMAND_NAK_LAST (1UL << 5)
#define FX3_I2C_COMMAND_PREAMBLE_VALID (1UL << 4)
#define FX3_I2C_COMMAND_PREAMBLE_LEN_SHIFT 0
#define FX3_I2C_COMMAND_PREAMBLE_LEN_BITS 4
#define FX3_I2C_COMMAND_PREAMBLE_LEN_MASK (0xfUL << 0)
#define FX3_I2C_EGRESS_DATA_DATA_SHIFT 0
#define FX3_I2C_EGRESS_DATA_DATA_BITS 8
#define FX3_I2C_EGRESS_DATA_DATA_MASK (0xffUL << 0)
#define FX3_I2C_INGRESS_DATA_DATA_SHIFT 0
#define FX3_I2C_INGRESS_DATA_DATA_BITS 8
#define FX3_I2C_INGRESS_DATA_DATA_MASK (0xffUL << 0)
#define FX3_I2C_SOCKET_INGRESS_SOCKET_SHIFT 8
#define FX3_I2C_SOCKET_INGRESS_SOCKET_BITS 8
#define FX3_I2C_SOCKET_INGRESS_SOCKET_MASK (0xffUL << 8)
#define FX3_I2C_SOCKET_EGRESS_SOCKET_SHIFT 0
#define FX3_I2C_SOCKET_EGRESS_SOCKET_BITS 8
#define FX3_I2C_SOCKET_EGRESS_SOCKET_MASK (0xffUL << 0)
#define FX3_I2C_ID_BLOCK_VERSION_SHIFT 16
#define FX3_I2C_ID_BLOCK_VERSION_BITS 16
#define FX3_I2C_ID_BLOCK_VERSION_MASK (0xffffUL << 16)
#define FX3_I2C_ID_BLOCK_ID_SHIFT 0
#define FX3_I2C_ID_BLOCK_ID_BITS 16
#define FX3_I2C_ID_BLOCK_ID_MASK (0xffffUL << 0)
#define FX3_I2C_POWER_RESETN (1UL << 31)
#define FX3_I2C_POWER_ACTIVE (1UL << 0)
#endif /* RDB_I2C_H_ */

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/*
* Copyright (C) 2018 Marcus Comstedt
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef RDB_I2S_H_
#define RDB_I2S_H_
#define FX3_I2S_CONFIG 0xE0000000 /* I2S Configuration and Mode Register */
#define FX3_I2S_STATUS 0xE0000004 /* I2S Status Register */
#define FX3_I2S_INTR 0xE0000008 /* I2S Interrupt Request Register */
#define FX3_I2S_INTR_MASK 0xE000000C /* I2S Interrupt Mask Register */
#define FX3_I2S_EGRESS_DATA_LEFT 0xE0000010 /* I2S Egress Data Register (Left) */
#define FX3_I2S_EGRESS_DATA_RIGHT 0xE0000014 /* I2S Egress Data Register (Right) */
#define FX3_I2S_COUNTER 0xE0000018 /* I2S Sample Counter Register */
#define FX3_I2S_SOCKET 0xE0000304 /* I2S Socket Register */
#define FX3_I2S_ID 0xE00003F0 /* Block Identification and Version Number */
#define FX3_I2S_POWER 0xE00003F4 /* Power, Clock, and Reset Control */
#define FX3_I2S_CONFIG_ENABLE (1UL << 31)
#define FX3_I2S_CONFIG_TX_CLEAR (1UL << 30)
#define FX3_I2S_CONFIG_MODE_SHIFT 11
#define FX3_I2S_CONFIG_MODE_BITS 2
#define FX3_I2S_CONFIG_MODE_MASK (0x3UL << 11)
#define FX3_I2S_CONFIG_BIT_WIDTH_SHIFT 8
#define FX3_I2S_CONFIG_BIT_WIDTH_BITS 3
#define FX3_I2S_CONFIG_BIT_WIDTH_MASK (0x7UL << 8)
#define FX3_I2S_CONFIG_DMA_MODE (1UL << 6)
#define FX3_I2S_CONFIG_MONO (1UL << 5)
#define FX3_I2S_CONFIG_FIXED_SCK (1UL << 4)
#define FX3_I2S_CONFIG_WSMODE (1UL << 3)
#define FX3_I2S_CONFIG_ENDIAN (1UL << 2)
#define FX3_I2S_CONFIG_MUTE (1UL << 1)
#define FX3_I2S_CONFIG_PAUSE (1UL << 0)
#define FX3_I2S_STATUS_BUSY (1UL << 28)
#define FX3_I2S_STATUS_ERROR_CODE_SHIFT 24
#define FX3_I2S_STATUS_ERROR_CODE_BITS 4
#define FX3_I2S_STATUS_ERROR_CODE_MASK (0xfUL << 24)
#define FX3_I2S_STATUS_ERROR (1UL << 8)
#define FX3_I2S_STATUS_NO_DATA (1UL << 7)
#define FX3_I2S_STATUS_PAUSED (1UL << 6)
#define FX3_I2S_STATUS_TXR_HALF (1UL << 5)
#define FX3_I2S_STATUS_TXR_SPACE (1UL << 4)
#define FX3_I2S_STATUS_TXR_DONE (1UL << 3)
#define FX3_I2S_STATUS_TXL_HALF (1UL << 2)
#define FX3_I2S_STATUS_TXL_SPACE (1UL << 1)
#define FX3_I2S_STATUS_TXL_DONE (1UL << 0)
#define FX3_I2S_INTR_ERROR (1UL << 8)
#define FX3_I2S_INTR_NO_DATA (1UL << 7)
#define FX3_I2S_INTR_PAUSED (1UL << 6)
#define FX3_I2S_INTR_TXR_HALF (1UL << 5)
#define FX3_I2S_INTR_TXR_SPACE (1UL << 4)
#define FX3_I2S_INTR_TXR_DONE (1UL << 3)
#define FX3_I2S_INTR_TXL_HALF (1UL << 2)
#define FX3_I2S_INTR_TXL_SPACE (1UL << 1)
#define FX3_I2S_INTR_TXL_DONE (1UL << 0)
#define FX3_I2S_INTR_MASK_ERROR (1UL << 8)
#define FX3_I2S_INTR_MASK_NO_DATA (1UL << 7)
#define FX3_I2S_INTR_MASK_PAUSED (1UL << 6)
#define FX3_I2S_INTR_MASK_TXR_HALF (1UL << 5)
#define FX3_I2S_INTR_MASK_TXR_SPACE (1UL << 4)
#define FX3_I2S_INTR_MASK_TXR_DONE (1UL << 3)
#define FX3_I2S_INTR_MASK_TXL_HALF (1UL << 2)
#define FX3_I2S_INTR_MASK_TXL_SPACE (1UL << 1)
#define FX3_I2S_INTR_MASK_TXL_DONE (1UL << 0)
#define FX3_I2S_SOCKET_RIGHT_SOCKET_SHIFT 8
#define FX3_I2S_SOCKET_RIGHT_SOCKET_BITS 8
#define FX3_I2S_SOCKET_RIGHT_SOCKET_MASK (0xffUL << 8)
#define FX3_I2S_SOCKET_LEFT_SOCKET_SHIFT 0
#define FX3_I2S_SOCKET_LEFT_SOCKET_BITS 8
#define FX3_I2S_SOCKET_LEFT_SOCKET_MASK (0xffUL << 0)
#define FX3_I2S_ID_BLOCK_VERSION_SHIFT 16
#define FX3_I2S_ID_BLOCK_VERSION_BITS 16
#define FX3_I2S_ID_BLOCK_VERSION_MASK (0xffffUL << 16)
#define FX3_I2S_ID_BLOCK_ID_SHIFT 0
#define FX3_I2S_ID_BLOCK_ID_BITS 16
#define FX3_I2S_ID_BLOCK_ID_MASK (0xffffUL << 0)
#define FX3_I2S_POWER_RESETN (1UL << 31)
#define FX3_I2S_POWER_ACTIVE (1UL << 0)
#endif /* RDB_I2S_H_ */

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/*
* Copyright (C) 2018 Marcus Comstedt
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef RDB_LPP_H_
#define RDB_LPP_H_
#define FX3_LPP_ID 0xE0007F00 /* Block Identification and Version Number */
#define FX3_LPP_POWER 0xE0007F04 /* Power, Clock, and Reset Control */
#define FX3_LPP_ID_BLOCK_VERSION_SHIFT 16
#define FX3_LPP_ID_BLOCK_VERSION_BITS 16
#define FX3_LPP_ID_BLOCK_VERSION_MASK (0xffffUL << 16)
#define FX3_LPP_ID_BLOCK_ID_SHIFT 0
#define FX3_LPP_ID_BLOCK_ID_BITS 16
#define FX3_LPP_ID_BLOCK_ID_MASK (0xffffUL << 0)
#define FX3_LPP_POWER_RESETN (1UL << 31)
#define FX3_LPP_POWER_ACTIVE (1UL << 0)
#endif /* RDB_LPP_H_ */

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/*
* Copyright (C) 2018 Marcus Comstedt
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef RDB_PIB_H_
#define RDB_PIB_H_
#define FX3_PIB_CONFIG 0xE0010000 /* PIB Configuration Register */
#define FX3_PIB_INTR 0xE0010004 /* PIB Interrupt Request Register */
#define FX3_PIB_INTR_MASK 0xE0010008 /* PIB Interrupt Mask Register */
#define FX3_PIB_CLOCK_DETECT 0xE001000C /* PIB Clock Detector Configuration Register */
#define FX3_PIB_RD_MAILBOX 0xE0010010 /* Read (Egress) Mailbox Register */
#define FX3_PIB_WR_MAILBOX 0xE0010018 /* Write (Ingress) Mailbox Register */
#define FX3_PIB_ERROR 0xE0010020 /* PIB Error Indicator Register */
#define FX3_PIB EOP/EOT 0xE0010024 /* Configuration Register */
#define FX3_PIB_DLL_CTRL 0xE0010028 /* DLL Configuration Register */
#define FX3_PIB_WR_THRESHOLD 0xE001002C /* Write Threshold Register */
#define FX3_PIB_RD_THRESHOLD 0xE0010030 /* Read Threshold Register */
#define FX3_PIB_ID 0xE0017F00 /* Block Identification and Version Number Register */
#define FX3_PIB_POWER 0xE0017F04 /* Power, Clock, and Reset Control Register */
#define FX3_PIB_CONFIG_ENABLE (1UL << 31)
#define FX3_PIB_CONFIG_MMIO_ENABLE (1UL << 30)
#define FX3_PIB_CONFIG_PP_CFGMODE (1UL << 29)
#define FX3_PIB_CONFIG_PCFG (1UL << 28)
#define FX3_PIB_CONFIG_DEVICE_ID_SHIFT 8
#define FX3_PIB_CONFIG_DEVICE_ID_BITS 8
#define FX3_PIB_CONFIG_DEVICE_ID_MASK (0xffUL << 8)
#define FX3_PIB_INTR_GPIF_ERR (1UL << 31)
#define FX3_PIB_INTR_PIB_ERR (1UL << 29)
#define FX3_PIB_INTR_RD_THRESHOLD (1UL << 10)
#define FX3_PIB_INTR_WR_THRESHOLD (1UL << 9)
#define FX3_PIB_INTR_CONFIG_CHANGE (1UL << 8)
#define FX3_PIB_INTR_CLOCK_LOST (1UL << 7)
#define FX3_PIB_INTR_DLL_LOST_LOCK (1UL << 6)
#define FX3_PIB_INTR_DLL_LOCKED (1UL << 5)
#define FX3_PIB_INTR_GPIF_INTERRUPT (1UL << 4)
#define FX3_PIB_INTR_WR_MB_FULL (1UL << 1)
#define FX3_PIB_INTR_RD_MB_EMPTY (1UL << 0)
#define FX3_PIB_INTR_MASK_GPIF_ERR (1UL << 31)
#define FX3_PIB_INTR_MASK_PIB_ERR (1UL << 29)
#define FX3_PIB_INTR_MASK_RD_THRESHOLD (1UL << 10)
#define FX3_PIB_INTR_MASK_WR_THRESHOLD (1UL << 9)
#define FX3_PIB_INTR_MASK_CONFIG_CHANGE (1UL << 8)
#define FX3_PIB_INTR_MASK_CLOCK_LOST (1UL << 7)
#define FX3_PIB_INTR_MASK_DLL_LOST_LOCK (1UL << 6)
#define FX3_PIB_INTR_MASK_DLL_LOCKED (1UL << 5)
#define FX3_PIB_INTR_MASK_GPIF_INTERRUPT (1UL << 4)
#define FX3_PIB_INTR_MASK_WR_MB_FULL (1UL << 1)
#define FX3_PIB_INTR_MASK_RD_MB_EMPTY (1UL << 0)
#define FX3_PIB_CLOCK_DETECT_ENABLE (1UL << 31)
#define FX3_PIB_CLOCK_DETECT_CLOCK_PRESENT (1UL << 30)
#define FX3_PIB_CLOCK_DETECT_INTF_CYCLES_SHIFT 16
#define FX3_PIB_CLOCK_DETECT_INTF_CYCLES_BITS 4
#define FX3_PIB_CLOCK_DETECT_INTF_CYCLES_MASK (0xfUL << 16)
#define FX3_PIB_CLOCK_DETECT_BUS_CYCLES_SHIFT 0
#define FX3_PIB_CLOCK_DETECT_BUS_CYCLES_BITS 16
#define FX3_PIB_CLOCK_DETECT_BUS_CYCLES_MASK (0xffffUL << 0)
#define FX3_PIB_RD_MAILBOX_PP_RD_MAILBOX_SHIFT 0
#define FX3_PIB_RD_MAILBOX_PP_RD_MAILBOX_BITS 64
#define FX3_PIB_RD_MAILBOX_PP_RD_MAILBOX_MASK (0xffffffffffffffffUL << 0)
#define FX3_PIB_WR_MAILBOX_PP_WR_MAILBOX_SHIFT 0
#define FX3_PIB_WR_MAILBOX_PP_WR_MAILBOX_BITS 64
#define FX3_PIB_WR_MAILBOX_PP_WR_MAILBOX_MASK (0xffffffffffffffffUL << 0)
#define FX3_PIB_ERROR_GPIF_ERR_CODE_SHIFT 10
#define FX3_PIB_ERROR_GPIF_ERR_CODE_BITS 5
#define FX3_PIB_ERROR_GPIF_ERR_CODE_MASK (0x1fUL << 10)
#define FX3_PIB_ERROR_PIB_ERR_CODE_SHIFT 0
#define FX3_PIB_ERROR_PIB_ERR_CODE_BITS 6
#define FX3_PIB_ERROR_PIB_ERR_CODE_MASK (0x3fUL << 0)
#define FX3_PIB_DLL_CTRL_ENABLE_RESET_ON_ERR (1UL << 31)
#define FX3_PIB_DLL_CTRL_DLL_RESET_N (1UL << 30)
#define FX3_PIB_DLL_CTRL_DLL_STAT (1UL << 2)
#define FX3_PIB_DLL_CTRL_HIGH_FREQ (1UL << 1)
#define FX3_PIB_DLL_CTRL_ENABLE (1UL << 0)
#define FX3_PIB_WR_THRESHOLD_VALUE16_SHIFT 0
#define FX3_PIB_WR_THRESHOLD_VALUE16_BITS 16
#define FX3_PIB_WR_THRESHOLD_VALUE16_MASK (0xffffUL << 0)
#define FX3_PIB_RD_THRESHOLD_VALUE16_SHIFT 0
#define FX3_PIB_RD_THRESHOLD_VALUE16_BITS 16
#define FX3_PIB_RD_THRESHOLD_VALUE16_MASK (0xffffUL << 0)
#define FX3_PIB_ID_BLOCK_VERSION_SHIFT 16
#define FX3_PIB_ID_BLOCK_VERSION_BITS 16
#define FX3_PIB_ID_BLOCK_VERSION_MASK (0xffffUL << 16)
#define FX3_PIB_ID_BLOCK_ID_SHIFT 0
#define FX3_PIB_ID_BLOCK_ID_BITS 16
#define FX3_PIB_ID_BLOCK_ID_MASK (0xffffUL << 0)
#define FX3_PIB_POWER_RESETN (1UL << 31)
#define FX3_PIB_POWER_ACTIVE (1UL << 0)
#endif /* RDB_PIB_H_ */

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/*
* Copyright (C) 2018 Marcus Comstedt
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef RDB_PPORT_H_
#define RDB_PPORT_H_
#define FX3_PP_ID 0xE0017E00 /* P-Port Device ID Register */
#define FX3_PP_INIT 0xE0017E04 /* P-Port Reset and Power Control Register */
#define FX3_PP_CONFIG 0xE0017E08 /* P-Port Configuration Register */
#define FX3_PP_INTR_MASK 0xE0017E1C /* P-Port Interrupt Mask Register */
#define FX3_PP_DRQR5_MASK 0xE0017E20 /* P-Port DRQ/R5 Mask Register */
#define FX3_PP_SOCK_MASK 0xE0017E24 /* P-Port Socket Mask Register */
#define FX3_PP_ERROR 0xE0017E28 /* P-Port Error Indicator Register */
#define FX3_PP_DMA_XFER 0xE0017E2C /* P-Port DMA Transfer Register */
#define FX3_PP_DMA_SIZE 0xE0017E30 /* P-Port DMA Transfer Size Register */
#define FX3_PP_WR_MAILBOX 0xE0017E34 /* P-Port Write (Ingress) Mailbox Registers */
#define FX3_PP_MMIO_ADDR 0xE0017E3C /* P-Port MMIO Address Registers */
#define FX3_PP_MMIO_DATA 0xE0017E40 /* P-Port MMIO Data Registers */
#define FX3_PP_MMIO 0xE0017E44 /* P-Port MMIO Control Registers */
#define FX3_PP_EVENT 0xE0017E48 /* P-Port Event Register */
#define FX3_PP_RD_MAILBOX 0xE0017E4C /* P-Port Read (Egress) Mailbox Registers */
#define FX3_PP_SOCK_STAT 0xE0017E54 /* P-Port Socket Status Register */
#define FX3_PP_BUF_SIZE_CNT 0xE0017E?? /* P-Port Socket Buffer Size or Count Register */
#define FX3_PP_ID_DEVICE_ID_SHIFT 0
#define FX3_PP_ID_DEVICE_ID_BITS 16
#define FX3_PP_ID_DEVICE_ID_MASK (0xffffUL << 0)
#define FX3_PP_INIT_BIG_ENDIAN (1UL << 15)
#define FX3_PP_INIT_HARD_RESET_N (1UL << 11)
#define FX3_PP_INIT_CPU_RESET_N (1UL << 10)
#define FX3_PP_INIT_WAKEUP_CLK (1UL << 4)
#define FX3_PP_INIT_WAKEUP_PWR (1UL << 3)
#define FX3_PP_INIT_WDT_RESET (1UL << 2)
#define FX3_PP_INIT_SW_RESET (1UL << 1)
#define FX3_PP_INIT_POR (1UL << 0)
#define FX3_PP_CONFIG_DACK_POLARITY (1UL << 15)
#define FX3_PP_CONFIG_DRQ_POLARITY (1UL << 14)
#define FX3_PP_CONFIG_DRQ_VALUE (1UL << 13)
#define FX3_PP_CONFIG_DRQ_OVERRIDE (1UL << 12)
#define FX3_PP_CONFIG_INTR_POLARITY (1UL << 11)
#define FX3_PP_CONFIG_INTR_VALUE (1UL << 10)
#define FX3_PP_CONFIG_INTR_OVERRIDE (1UL << 9)
#define FX3_PP_CONFIG_DRQMODE (1UL << 7)
#define FX3_PP_CONFIG_CFGMODE (1UL << 6)
#define FX3_PP_CONFIG_BURSTSIZE_SHIFT 0
#define FX3_PP_CONFIG_BURSTSIZE_BITS 4
#define FX3_PP_CONFIG_BURSTSIZE_MASK (0xfUL << 0)
#define FX3_PP_INTR_MASK_WAKEUP (1UL << 15)
#define FX3_PP_INTR_MASK_WR_MB_EMPTY (1UL << 14)
#define FX3_PP_INTR_MASK_RD_MB_FULL (1UL << 13)
#define FX3_PP_INTR_MASK_DMA_READY_EV (1UL << 12)
#define FX3_PP_INTR_MASK_DMA_WMARK_EV (1UL << 11)
#define FX3_PP_INTR_MASK_GPIF_ERR (1UL << 7)
#define FX3_PP_INTR_MASK_PIB_ERR (1UL << 5)
#define FX3_PP_INTR_MASK_GPIF_INT (1UL << 4)
#define FX3_PP_INTR_MASK_SOCK_AGG_BH (1UL << 3)
#define FX3_PP_INTR_MASK_SOCK_AGG_BL (1UL << 2)
#define FX3_PP_INTR_MASK_SOCK_AGG_AH (1UL << 1)
#define FX3_PP_INTR_MASK_SOCK_AGG_AL (1UL << 0)
#define FX3_PP_DRQR5_MASK_WAKEUP (1UL << 15)
#define FX3_PP_DRQR5_MASK_WR_MB_EMPTY (1UL << 14)
#define FX3_PP_DRQR5_MASK_RD_MB_FULL (1UL << 13)
#define FX3_PP_DRQR5_MASK_DMA_READY_EV (1UL << 12)
#define FX3_PP_DRQR5_MASK_DMA_WMARK_EV (1UL << 11)
#define FX3_PP_DRQR5_MASK_GPIF_ERR (1UL << 7)
#define FX3_PP_DRQR5_MASK_PIB_ERR (1UL << 5)
#define FX3_PP_DRQR5_MASK_GPIF_INT (1UL << 4)
#define FX3_PP_DRQR5_MASK_SOCK_AGG_BH (1UL << 3)
#define FX3_PP_DRQR5_MASK_SOCK_AGG_BL (1UL << 2)
#define FX3_PP_DRQR5_MASK_SOCK_AGG_AH (1UL << 1)
#define FX3_PP_DRQR5_MASK_SOCK_AGG_AL (1UL << 0)
#define FX3_PP_ERROR_GPIF_ERR_CODE_SHIFT 10
#define FX3_PP_ERROR_GPIF_ERR_CODE_BITS 5
#define FX3_PP_ERROR_GPIF_ERR_CODE_MASK (0x1fUL << 10)
#define FX3_PP_ERROR_PIB_ERR_CODE_SHIFT 0
#define FX3_PP_ERROR_PIB_ERR_CODE_BITS 6
#define FX3_PP_ERROR_PIB_ERR_CODE_MASK (0x3fUL << 0)
#define FX3_PP_DMA_XFER_DMA_READY (1UL << 15)
#define FX3_PP_DMA_XFER_DMA_ERROR (1UL << 14)
#define FX3_PP_DMA_XFER_DMA_BUSY (1UL << 13)
#define FX3_PP_DMA_XFER_SIZE_VALID (1UL << 12)
#define FX3_PP_DMA_XFER_LONG_TRANSFER (1UL << 10)
#define FX3_PP_DMA_XFER_DMA_DIRECTION (1UL << 9)
#define FX3_PP_DMA_XFER_DMA_ENABLE (1UL << 8)
#define FX3_PP_DMA_XFER_DMA_SOCK_SHIFT 0
#define FX3_PP_DMA_XFER_DMA_SOCK_BITS 8
#define FX3_PP_DMA_XFER_DMA_SOCK_MASK (0xffUL << 0)
#define FX3_PP_DMA_SIZE_DMA_SIZE_SHIFT 0
#define FX3_PP_DMA_SIZE_DMA_SIZE_BITS 16
#define FX3_PP_DMA_SIZE_DMA_SIZE_MASK (0xffffUL << 0)
#define FX3_PP_WR_MAILBOX_WR_MAILBOX_SHIFT 0
#define FX3_PP_WR_MAILBOX_WR_MAILBOX_BITS 64
#define FX3_PP_WR_MAILBOX_WR_MAILBOX_MASK (0xffffffffffffffffUL << 0)
#define FX3_PP_MMIO_MMIO_FAIL (1UL << 3)
#define FX3_PP_MMIO_MMIO_BUSY (1UL << 2)
#define FX3_PP_MMIO_MMIO_WR (1UL << 1)
#define FX3_PP_MMIO_MMIO_RD (1UL << 0)
#define FX3_PP_EVENT_WAKEUP (1UL << 15)
#define FX3_PP_EVENT_WR_MB_EMPTY (1UL << 14)
#define FX3_PP_EVENT_RD_MB_FULL (1UL << 13)
#define FX3_PP_EVENT_DMA_READY_EV (1UL << 12)
#define FX3_PP_EVENT_DMA_WMARK_EV (1UL << 11)
#define FX3_PP_EVENT_GPIF_ERR (1UL << 7)
#define FX3_PP_EVENT_PIB_ERR (1UL << 5)
#define FX3_PP_EVENT_GPIF_INT (1UL << 4)
#define FX3_PP_EVENT_SOCK_AGG_BH (1UL << 3)
#define FX3_PP_EVENT_SOCK_AGG_BL (1UL << 2)
#define FX3_PP_EVENT_SOCK_AGG_AH (1UL << 1)
#define FX3_PP_EVENT_SOCK_AGG_AL (1UL << 0)
#define FX3_PP_RD_MAILBOX_RD_MAILBOX_SHIFT 0
#define FX3_PP_RD_MAILBOX_RD_MAILBOX_BITS 64
#define FX3_PP_RD_MAILBOX_RD_MAILBOX_MASK (0xffffffffffffffffUL << 0)
#define FX3_PP_BUF_SIZE_CNT_SIZE_CNT_SHIFT 0
#define FX3_PP_BUF_SIZE_CNT_SIZE_CNT_BITS 16
#define FX3_PP_BUF_SIZE_CNT_SIZE_CNT_MASK (0xffffUL << 0)
#endif /* RDB_PPORT_H_ */

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The include files in this directory have been generated from
the TRM using the script generator/convert.sh.

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/*
* Copyright (C) 2018 Marcus Comstedt
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef RDB_SPI_H_
#define RDB_SPI_H_
#define FX3_SPI_CONFIG 0xE0000C00 /* SPI Configuration and Modes Register */
#define FX3_SPI_STATUS 0xE0000C04 /* SPI Status Register */
#define FX3_SPI_INTR 0xE0000C08 /* SPI Interrupt Request Register */
#define FX3_SPI_INTR_MASK 0xE0000C0C /* SPI Interrupt Mask Register */
#define FX3_SPI_EGRESS_DATA 0xE0000C10 /* SPI Egress Data Register */
#define FX3_SPI_INGRESS_DATA 0xE0000C14 /* SPI Ingress Data Register */
#define FX3_SPI_SOCKET 0xE0000C18 /* SPI Socket Register */
#define FX3_SPI_RX_BYTE_COUNT 0xE0000C1C /* SPI Receive Byte Count Register */
#define FX3_SPI_TX_BYTE_COUNT 0xE0000C20 /* SPI Transmit Byte Count Register */
#define FX3_SPI_ID 0xE0000FF0 /* Block Identification and Version Number */
#define FX3_SPI_POWER 0xE0000FF4 /* Power, Clock, and Reset Control */
#define FX3_SPI_CONFIG_ENABLE (1UL << 31)
#define FX3_SPI_CONFIG_TX_CLEAR (1UL << 30)
#define FX3_SPI_CONFIG_RX_CLEAR (1UL << 29)
#define FX3_SPI_CONFIG_DESELECT (1UL << 23)
#define FX3_SPI_CONFIG_WL_SHIFT 17
#define FX3_SPI_CONFIG_WL_BITS 6
#define FX3_SPI_CONFIG_WL_MASK (0x3fUL << 17)
#define FX3_SPI_CONFIG_SSPOL (1UL << 16)
#define FX3_SPI_CONFIG_LAG_SHIFT 14
#define FX3_SPI_CONFIG_LAG_BITS 2
#define FX3_SPI_CONFIG_LAG_MASK (0x3UL << 14)
#define FX3_SPI_CONFIG_LEAD_SHIFT 12
#define FX3_SPI_CONFIG_LEAD_BITS 2
#define FX3_SPI_CONFIG_LEAD_MASK (0x3UL << 12)
#define FX3_SPI_CONFIG_CPHA (1UL << 11)
#define FX3_SPI_CONFIG_CPOL (1UL << 10)
#define FX3_SPI_CONFIG_SSNCTRL_SHIFT 8
#define FX3_SPI_CONFIG_SSNCTRL_BITS 2
#define FX3_SPI_CONFIG_SSNCTRL_MASK (0x3UL << 8)
#define FX3_SPI_CONFIG_LOOPBACK (1UL << 5)
#define FX3_SPI_CONFIG_SSN_BIT (1UL << 4)
#define FX3_SPI_CONFIG_ENDIAN (1UL << 3)
#define FX3_SPI_CONFIG_DMA_MODE (1UL << 2)
#define FX3_SPI_CONFIG_TX_ENABLE (1UL << 1)
#define FX3_SPI_CONFIG_RX_ENABLE (1UL << 0)
#define FX3_SPI_STATUS_BUSY (1UL << 28)
#define FX3_SPI_STATUS_ERROR_CODE_SHIFT 24
#define FX3_SPI_STATUS_ERROR_CODE_BITS 4
#define FX3_SPI_STATUS_ERROR_CODE_MASK (0xfUL << 24)
#define FX3_SPI_STATUS_ERROR (1UL << 6)
#define FX3_SPI_STATUS_TX_HALF (1UL << 5)
#define FX3_SPI_STATUS_TX_SPACE (1UL << 4)
#define FX3_SPI_STATUS_TX_DONE (1UL << 3)
#define FX3_SPI_STATUS_RX_HALF (1UL << 2)
#define FX3_SPI_STATUS_RX_DATA (1UL << 1)
#define FX3_SPI_STATUS_RX_DONE (1UL << 0)
#define FX3_SPI_INTR_ERROR (1UL << 6)
#define FX3_SPI_INTR_TX_HALF (1UL << 5)
#define FX3_SPI_INTR_TX_SPACE (1UL << 4)
#define FX3_SPI_INTR_TX_DONE (1UL << 3)
#define FX3_SPI_INTR_RX_HALF (1UL << 2)
#define FX3_SPI_INTR_RX_DATA (1UL << 1)
#define FX3_SPI_INTR_RX_DONE (1UL << 0)
#define FX3_SPI_INTR_MASK_ERROR (1UL << 6)
#define FX3_SPI_INTR_MASK_TX_HALF (1UL << 5)
#define FX3_SPI_INTR_MASK_TX_SPACE (1UL << 4)
#define FX3_SPI_INTR_MASK_TX_DONE (1UL << 3)
#define FX3_SPI_INTR_MASK_RX_HALF (1UL << 2)
#define FX3_SPI_INTR_MASK_RX_DATA (1UL << 1)
#define FX3_SPI_INTR_MASK_RX_DONE (1UL << 0)
#define FX3_SPI_SOCKET_INGRESS_SOCKET_SHIFT 8
#define FX3_SPI_SOCKET_INGRESS_SOCKET_BITS 8
#define FX3_SPI_SOCKET_INGRESS_SOCKET_MASK (0xffUL << 8)
#define FX3_SPI_SOCKET_EGRESS_SOCKET_SHIFT 0
#define FX3_SPI_SOCKET_EGRESS_SOCKET_BITS 8
#define FX3_SPI_SOCKET_EGRESS_SOCKET_MASK (0xffUL << 0)
#define FX3_SPI_ID_BLOCK_VERSION_SHIFT 16
#define FX3_SPI_ID_BLOCK_VERSION_BITS 16
#define FX3_SPI_ID_BLOCK_VERSION_MASK (0xffffUL << 16)
#define FX3_SPI_ID_BLOCK_ID_SHIFT 0
#define FX3_SPI_ID_BLOCK_ID_BITS 16
#define FX3_SPI_ID_BLOCK_ID_MASK (0xffffUL << 0)
#define FX3_SPI_POWER_RESETN (1UL << 31)
#define FX3_SPI_POWER_ACTIVE (1UL << 0)
#endif /* RDB_SPI_H_ */

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/*
* Copyright (C) 2018 Marcus Comstedt
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef RDB_UART_H_
#define RDB_UART_H_
#define FX3_UART_CONFIG 0xE0000800 /* UART Configuration and Mode Register */
#define FX3_UART_STATUS 0xE0000804 /* UART Status Register */
#define FX3_UART_INTR 0xE0000808 /* UART Interrupt Request Register */
#define FX3_UART_INTR_MASK 0xE000080C /* UART Interrupt Mask Register */
#define FX3_UART_EGRESS_DATA 0xE0000810 /* UART Egress Data Register */
#define FX3_UART_INGRESS_DATA 0xE0000814 /* UART Ingress Data Register */
#define FX3_UART_SOCKET 0xE0000818 /* UART Socket Register */
#define FX3_UART_RX_BYTE_COUNT 0xE000081C /* UART Receive Byte Count Register */
#define FX3_UART_TX_BYTE_COUNT 0xE0000820 /* UART Transmit Byte Count Register */
#define FX3_UART_ID 0xE0000BF0 /* Block Identification and Version Number */
#define FX3_UART_POWER 0xE0000BF4 /* Power, Clock, and Reset Control */
#define FX3_UART_CONFIG_ENABLE (1UL << 31)
#define FX3_UART_CONFIG_TX_CLEAR (1UL << 30)
#define FX3_UART_CONFIG_RX_CLEAR (1UL << 29)
#define FX3_UART_CONFIG_RX_POLL_SHIFT 16
#define FX3_UART_CONFIG_RX_POLL_BITS 4
#define FX3_UART_CONFIG_RX_POLL_MASK (0xfUL << 16)
#define FX3_UART_CONFIG_TX_BREAK (1UL << 15)
#define FX3_UART_CONFIG_RX_FLOW_CTRL_ENBL (1UL << 14)
#define FX3_UART_CONFIG_TX_FLOW_CTRL_ENBL (1UL << 13)
#define FX3_UART_CONFIG_RTS (1UL << 12)
#define FX3_UART_CONFIG_DMA_MODE (1UL << 10)
#define FX3_UART_CONFIG_STOP_BITS_SHIFT 8
#define FX3_UART_CONFIG_STOP_BITS_BITS 2
#define FX3_UART_CONFIG_STOP_BITS_MASK (0x3UL << 8)
#define FX3_UART_CONFIG_RX_STICKY_BIT (1UL << 7)
#define FX3_UART_CONFIG_TX_STICKY_BIT (1UL << 6)
#define FX3_UART_CONFIG_PARITY_STICKY (1UL << 5)
#define FX3_UART_CONFIG_PARITY_ODD (1UL << 4)
#define FX3_UART_CONFIG_PARITY (1UL << 3)
#define FX3_UART_CONFIG_LOOP_BACK (1UL << 2)
#define FX3_UART_CONFIG_TX_ENABLE (1UL << 1)
#define FX3_UART_CONFIG_RX_ENABLE (1UL << 0)
#define FX3_UART_STATUS_BUSY (1UL << 28)
#define FX3_UART_STATUS_ERROR_CODE_SHIFT 24
#define FX3_UART_STATUS_ERROR_CODE_BITS 4
#define FX3_UART_STATUS_ERROR_CODE_MASK (0xfUL << 24)
#define FX3_UART_STATUS_ERROR (1UL << 9)
#define FX3_UART_STATUS_BREAK (1UL << 8)
#define FX3_UART_STATUS_CTS_TOGGLE (1UL << 7)
#define FX3_UART_STATUS_CTS_STAT (1UL << 6)
#define FX3_UART_STATUS_TX_HALF (1UL << 5)
#define FX3_UART_STATUS_TX_SPACE (1UL << 4)
#define FX3_UART_STATUS_TX_DONE (1UL << 3)
#define FX3_UART_STATUS_RX_HALF (1UL << 2)
#define FX3_UART_STATUS_RX_DATA (1UL << 1)
#define FX3_UART_STATUS_RX_DONE (1UL << 0)
#define FX3_UART_INTR_ERROR (1UL << 9)
#define FX3_UART_INTR_BREAK (1UL << 8)
#define FX3_UART_INTR_CTS_TOGGLE (1UL << 7)
#define FX3_UART_INTR_CTS_STAT (1UL << 6)
#define FX3_UART_INTR_TX_HALF (1UL << 5)
#define FX3_UART_INTR_TX_SPACE (1UL << 4)
#define FX3_UART_INTR_TX_DONE (1UL << 3)
#define FX3_UART_INTR_RX_HALF (1UL << 2)
#define FX3_UART_INTR_RX_DATA (1UL << 1)
#define FX3_UART_INTR_RX_DONE (1UL << 0)
#define FX3_UART_INTR_MASK_ERROR (1UL << 9)
#define FX3_UART_INTR_MASK_BREAK (1UL << 8)
#define FX3_UART_INTR_MASK_CTS_TOGGLE (1UL << 7)
#define FX3_UART_INTR_MASK_CTS_STAT (1UL << 6)
#define FX3_UART_INTR_MASK_TX_HALF (1UL << 5)
#define FX3_UART_INTR_MASK_TX_SPACE (1UL << 4)
#define FX3_UART_INTR_MASK_TX_DONE (1UL << 3)
#define FX3_UART_INTR_MASK_RX_HALF (1UL << 2)
#define FX3_UART_INTR_MASK_RX_DATA (1UL << 1)
#define FX3_UART_INTR_MASK_RX_DONE (1UL << 0)
#define FX3_UART_EGRESS_DATA_DATA_SHIFT 0
#define FX3_UART_EGRESS_DATA_DATA_BITS 8
#define FX3_UART_EGRESS_DATA_DATA_MASK (0xffUL << 0)
#define FX3_UART_INGRESS_DATA_DATA_SHIFT 0
#define FX3_UART_INGRESS_DATA_DATA_BITS 8
#define FX3_UART_INGRESS_DATA_DATA_MASK (0xffUL << 0)
#define FX3_UART_SOCKET_INGRESS_SOCKET_SHIFT 8
#define FX3_UART_SOCKET_INGRESS_SOCKET_BITS 8
#define FX3_UART_SOCKET_INGRESS_SOCKET_MASK (0xffUL << 8)
#define FX3_UART_SOCKET_EGRESS_SOCKET_SHIFT 0
#define FX3_UART_SOCKET_EGRESS_SOCKET_BITS 8
#define FX3_UART_SOCKET_EGRESS_SOCKET_MASK (0xffUL << 0)
#define FX3_UART_ID_BLOCK_VERSION_SHIFT 16
#define FX3_UART_ID_BLOCK_VERSION_BITS 16
#define FX3_UART_ID_BLOCK_VERSION_MASK (0xffffUL << 16)
#define FX3_UART_ID_BLOCK_ID_SHIFT 0
#define FX3_UART_ID_BLOCK_ID_BITS 16
#define FX3_UART_ID_BLOCK_ID_MASK (0xffffUL << 0)
#define FX3_UART_POWER_RESETN (1UL << 31)
#define FX3_UART_POWER_ACTIVE (1UL << 0)
#endif /* RDB_UART_H_ */

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/*
* Copyright (C) 2018 Marcus Comstedt
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef RDB_UIBIN_H_
#define RDB_UIBIN_H_
#define FX3_UIBIN_ID 0xE0040000 /* Block Identification and Version Number Register */
#define FX3_UIBIN_POWER 0xE0040004 /* Power, Clock, and Reset Control Registers */
#define FX3_UIBIN_ID_BLOCK_VERSION_SHIFT 16
#define FX3_UIBIN_ID_BLOCK_VERSION_BITS 16
#define FX3_UIBIN_ID_BLOCK_VERSION_MASK (0xffffUL << 16)
#define FX3_UIBIN_ID_BLOCK_ID_SHIFT 0
#define FX3_UIBIN_ID_BLOCK_ID_BITS 16
#define FX3_UIBIN_ID_BLOCK_ID_MASK (0xffffUL << 0)
#define FX3_UIBIN_POWER_RESETN (1UL << 31)
#define FX3_UIBIN_POWER_ACTIVE (1UL << 0)
#endif /* RDB_UIBIN_H_ */

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/*
* Copyright (C) 2018 Marcus Comstedt
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef RDB_VIC_H_
#define RDB_VIC_H_
#define FX3_VIC_IRQ_STATUS 0xFFFFF000 /* IRQ Status after Masking */
#define FX3_VIC_FIQ_STATUS 0xFFFFF004 /* FIQ Status after Masking */
#define FX3_VIC_RAW_STATUS 0xFFFFF008 /* IRQ Status before Masking */
#define FX3_VIC_INT_SELECT 0xFFFFF00C /* IRQ/FIQ Designation Register */
#define FX3_VIC_INT_ENABLE 0xFFFFF010 /* Interrupt Enable Register */
#define FX3_VIC_INT_CLEAR 0xFFFFF014 /* Interrupt Clear Register */
#define FX3_VIC_PRIORITY_MASK 0xFFFFF024 /* Per-Priority Interrupt Mask Register */
#define FX3_VIC_VEC_ADDRESS 0xFFFFF100 /* Interrupt Vector Register */
#define FX3_VIC_VECT_PRIORITY 0xFFFFF200 /* Interrupt Priority Register */
#define FX3_VIC_ADDRESS 0xFFFFFF00 /* Active ISR Address Register */
#define FX3_VIC_PRIORITY_MASK_PRIO_MASK_SHIFT 0
#define FX3_VIC_PRIORITY_MASK_PRIO_MASK_BITS 16
#define FX3_VIC_PRIORITY_MASK_PRIO_MASK_MASK (0xffffUL << 0)
#define FX3_VIC_VECT_PRIORITY_VIC_INTR_PRI_SHIFT 0
#define FX3_VIC_VECT_PRIORITY_VIC_INTR_PRI_BITS 4
#define FX3_VIC_VECT_PRIORITY_VIC_INTR_PRI_MASK (0xfUL << 0)
#endif /* RDB_VIC_H_ */