70 lines
2.4 KiB
C
70 lines
2.4 KiB
C
/*
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* Copyright (C) 2018 Marcus Comstedt
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <bsp/gctl.h>
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#include <bsp/regaccess.h>
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#include <bsp/util.h>
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#include <rdb/gctl.h>
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void Fx3GctlInitClock(void)
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{
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/* Select minimum scalers for all clocks */
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Fx3WriteReg32(FX3_GCTL_CPU_CLK_CFG,
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(1UL << FX3_GCTL_CPU_CLK_CFG_MMIO_DIV_SHIFT) |
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(1UL << FX3_GCTL_CPU_CLK_CFG_DMA_DIV_SHIFT) |
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(3UL << FX3_GCTL_CPU_CLK_CFG_SRC_SHIFT) |
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((CPU_DIV - 1UL) << FX3_GCTL_CPU_CLK_CFG_CPU_DIV_SHIFT));
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Fx3UtilDelayUs(10);
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/* Change PLL feedback divisor if needed */
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if (Fx3GetField32(FX3_GCTL_PLL_CFG, FBDIV) != PLL_FBDIV) {
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Fx3SetField32(FX3_GCTL_PLL_CFG, FBDIV, PLL_FBDIV);
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Fx3UtilDelayUs(10);
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while ((Fx3ReadReg32(FX3_GCTL_PLL_CFG) & FX3_GCTL_PLL_CFG_PLL_LOCK) == 0)
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;
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Fx3UtilDelayUs(10);
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}
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}
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void Fx3GctlInitIoMatrix(Fx3GctlPinAltFunc_t alt_func)
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{
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/* Disable all GPIO overrides */
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Fx3WriteReg32(FX3_GCTL_GPIO_SIMPLE, 0);
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Fx3WriteReg32(FX3_GCTL_GPIO_SIMPLE+4, 0);
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Fx3WriteReg32(FX3_GCTL_GPIO_COMPLEX, 0);
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Fx3WriteReg32(FX3_GCTL_GPIO_COMPLEX+4, 0);
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Fx3UtilDelayUs(1);
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/* Configure matrix */
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Fx3WriteReg32(FX3_GCTL_IOMATRIX,
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(alt_func << FX3_GCTL_IOMATRIX_S1CFG_SHIFT) |
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(alt_func == FX3_GCTL_ALTFUNC_GPIF32BIT_UART_I2S?
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FX3_GCTL_IOMATRIX_S0CFG : 0));
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}
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void Fx3GctlHardReset(void)
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{
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Fx3UtilDelayUs(5);
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Fx3ClearReg32(FX3_GCTL_CONTROL, FX3_GCTL_CONTROL_HARD_RESET_N);
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Fx3UtilDelayUs(5);
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}
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