238 lines
8.6 KiB
C
238 lines
8.6 KiB
C
/*
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* Copyright (C) 2018 Marcus Comstedt
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef BSP_GPIF_H_
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#define BSP_GPIF_H_
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#include <stdint.h>
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#include <rdb/gpif.h>
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/* Perform bitwise operations on the following constants to achieve the
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corresponding logical operations on the four 1-bit operands */
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#define FX3_GPIF_FUNCTION_Fa 0xAAAAU
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#define FX3_GPIF_FUNCTION_Fb 0xCCCCU
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#define FX3_GPIF_FUNCTION_Fc 0xF0F0U
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#define FX3_GPIF_FUNCTION_Fd 0xFF00U
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/* Fixed function alphas and betas */
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/* (Alpha 4-7 and Beta 0-3 are user defined) */
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#define FX3_GPIF_ALPHA_DQ_OEN (1UL<<0) /* Alpha 0 */
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#define FX3_GPIF_ALPHA_UPDATE_DOUT (1UL<<1) /* Alpha 1 */
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#define FX3_GPIF_ALPHA_SAMPLE_DIN (1UL<<2) /* Alpha 2 */
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#define FX3_GPIF_ALPHA_SAMPLE_AIN (1UL<<3) /* Alpha 3 */
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#define FX3_GPIF_BETA_THREAD_0 (0UL<<4) /* Beta 4&5 */
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#define FX3_GPIF_BETA_THREAD_1 (1UL<<4) /* - " - */
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#define FX3_GPIF_BETA_THREAD_2 (2UL<<4) /* - " - */
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#define FX3_GPIF_BETA_THREAD_3 (3UL<<4) /* - " - */
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#define FX3_GPIF_BETA_RQ_POP (1UL<<6) /* Beta 6 */
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#define FX3_GPIF_BETA_WQ_PUSH (1UL<<7) /* Beta 7 */
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#define FX3_GPIF_BETA_RQ_POP_ADDR (1UL<<8) /* Beta 8 */
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#define FX3_GPIF_BETA_WQ_PUSH_ADDR (1UL<<9) /* Beta 9 */
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#define FX3_GPIF_BETA_A_OEN (1UL<<10) /* Beta 10 */
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/* 11 = ? */
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#define FX3_GPIF_BETA_COUNT_CTRL (1UL<<12) /* Beta 12 */
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#define FX3_GPIF_BETA_LD_CTRL_COUNT (1UL<<13) /* Beta 13 */
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#define FX3_GPIF_BETA_COUNT_ADDR (1UL<<14) /* Beta 14 */
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#define FX3_GPIF_BETA_LD_ADDR_COUNT (1UL<<15) /* Beta 15 */
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#define FX3_GPIF_BETA_COUNT_DATA (1UL<<16) /* Beta 16 */
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#define FX3_GPIF_BETA_LD_DATA_COUNT (1UL<<17) /* Beta 17 */
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#define FX3_GPIF_BETA_INTR_CPU (1UL<<18) /* Beta 18 */
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#define FX3_GPIF_BETA_INTR_HOST (1UL<<19) /* Beta 19 */
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#define FX3_GPIF_BETA_UPDATE_AOUT (1UL<<20) /* Beta 20 */
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#define FX3_GPIF_BETA_REGISTER_ACCESS (1UL<<21) /* Beta 21 */
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/* 22, 23, 24 = ? */
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#define FX3_GPIF_BETA_ASSERT_DRQ (1UL<<25) /* Beta 25 */
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#define FX3_GPIF_BETA_DEASSERT_DRQ (1UL<<26) /* Beta 26 */
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/* 27, 28, 29 = ? */
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#define FX3_GPIF_BETA_COMMIT (1UL<<30) /* Beta 30 */
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#define FX3_GPIF_BETA_PP_ACCESS (1UL<<31) /* Beta 31 */
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/* For compatibility with GPIF II Designer output */
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typedef struct {
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uint32_t left[3], right[3];
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} Fx3GpifWaveformCompat_t;
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typedef struct {
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uint32_t state[3];
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uint16_t left, right;
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} Fx3GpifWaveform_t;
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#define GPIF_START_STATE(n) {(n)&0xff,0,0}
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#define GPIF_STATE(n,Fa,Fb,Fc,Fd,f0,f1,AL,AR,B,rep,BD) { \
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((n)&0xff)|(((Fa)&0x1f)<<8)|(((Fb)&0x1f)<<13)|(((Fc)&0x1f)<<18)|(((Fd)&0x1f)<<23)|(((f0)&0xf)<<28), \
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(((f0)&0x10)>>4)|(((f1)&0x1f)<<1)|(((AL)&0xff)<<6)|(((AR)&0xff)<<14)|(((B)&0x3ff)<<22), \
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(((B)&0xfffffc00)>>10)|(((rep)&0xff)<<22)|(((BD)&1)<<30)|(1UL<<31)}
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typedef enum {
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FX3_GPIF_CTRL_BUS_DIRECTION_INPUT = 0,
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FX3_GPIF_CTRL_BUS_DIRECTION_OUTPUT,
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FX3_GPIF_CTRL_BUS_DIRECTION_BIDIR,
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FX3_GPIF_CTRL_BUS_DIRECTION_OPEN_DRAIN,
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} Fx3GpifCtrlBusDirection_t;
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typedef enum {
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FX3_GPIF_OEN_CFG_OUTPUT = 0,
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FX3_GPIF_OEN_CFG_INPUT,
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FX3_GPIF_OEN_CFG_DYNAMIC, /* Controlled by alpha/beta */
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} Fx3GpifOenCfg_t;
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typedef enum {
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FX3_GPIF_LAMBDA_INDEX_CTL0 = 0, /* GPIO 17 */
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FX3_GPIF_LAMBDA_INDEX_CTL1, /* GPIO 18 */
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FX3_GPIF_LAMBDA_INDEX_CTL2, /* GPIO 19 */
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FX3_GPIF_LAMBDA_INDEX_CTL3, /* GPIO 20 */
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FX3_GPIF_LAMBDA_INDEX_CTL4, /* GPIO 21 */
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FX3_GPIF_LAMBDA_INDEX_CTL5, /* GPIO 22 */
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FX3_GPIF_LAMBDA_INDEX_CTL6, /* GPIO 23 */
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FX3_GPIF_LAMBDA_INDEX_CTL7, /* GPIO 24 */
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FX3_GPIF_LAMBDA_INDEX_CTL8, /* GPIO 25 */
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FX3_GPIF_LAMBDA_INDEX_CTL9, /* GPIO 26 */
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FX3_GPIF_LAMBDA_INDEX_CTL10, /* GPIO 27 */
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FX3_GPIF_LAMBDA_INDEX_CTL11, /* GPIO 28 */
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FX3_GPIF_LAMBDA_INDEX_CTL12, /* GPIO 29 */
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FX3_GPIF_LAMBDA_INDEX_CTL13, /* GPIO 49 */
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FX3_GPIF_LAMBDA_INDEX_CTL14, /* GPIO 48 */
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FX3_GPIF_LAMBDA_INDEX_CTL15, /* GPIO 47 */
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FX3_GPIF_LAMBDA_INDEX_OUT_REG_CR_VALID = 16,
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FX3_GPIF_LAMBDA_INDEX_IN_REG_CR_VALID = 17,
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FX3_GPIF_LAMBDA_INDEX_CTRL_CNT_HIT = 18,
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FX3_GPIF_LAMBDA_INDEX_ADDR_CNT_HIT = 19,
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FX3_GPIF_LAMBDA_INDEX_DATA_CNT_HIT = 20,
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FX3_GPIF_LAMBDA_INDEX_CTRL_CMP_MATCH = 21,
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FX3_GPIF_LAMBDA_INDEX_ADDR_CMP_MATCH = 22,
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FX3_GPIF_LAMBDA_INDEX_DATA_CMP_MATCH = 23,
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FX3_GPIF_LAMBDA_INDEX_DMA_WM = 24,
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FX3_GPIF_LAMBDA_INDEX_DMA_RDY_ADDR = 25,
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FX3_GPIF_LAMBDA_INDEX_DMA_RDY = 26,
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/* 27, 28 = ? */
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FX3_GPIF_LAMBDA_INDEX_INTR_PEND = 29,
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FX3_GPIF_LAMBDA_INDEX_FW_TRG = 30,
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FX3_GPIF_LAMBDA_INDEX_OUT_ADDR_VALID = 31,
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} Fx3GpifLambdaIndex_t;
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typedef enum {
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FX3_GPIF_OMEGA_INDEX_ALPHA4 = 0,
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FX3_GPIF_OMEGA_INDEX_ALPHA5,
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FX3_GPIF_OMEGA_INDEX_ALPHA6,
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FX3_GPIF_OMEGA_INDEX_ALPHA7,
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FX3_GPIF_OMEGA_INDEX_BETA0 = 8,
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FX3_GPIF_OMEGA_INDEX_BETA1,
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FX3_GPIF_OMEGA_INDEX_BETA2,
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FX3_GPIF_OMEGA_INDEX_BETA3,
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FX3_GPIF_OMEGA_INDEX_EMPTY_FULL_TH0 = 16,
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FX3_GPIF_OMEGA_INDEX_EMPTY_FULL_TH1,
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FX3_GPIF_OMEGA_INDEX_EMPTY_FULL_TH2,
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FX3_GPIF_OMEGA_INDEX_EMPTY_FULL_TH3,
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FX3_GPIF_OMEGA_INDEX_PARTIAL_TH0,
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FX3_GPIF_OMEGA_INDEX_PARTIAL_TH1,
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FX3_GPIF_OMEGA_INDEX_PARTIAL_TH2,
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FX3_GPIF_OMEGA_INDEX_PARTIAL_TH3,
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FX3_GPIF_OMEGA_INDEX_EMPTY_FULL_CURRENT,
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FX3_GPIF_OMEGA_INDEX_PARTIAL_CURRENT,
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FX3_GPIF_OMEGA_INDEX_PP_DRQR5,
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FX3_GPIF_OMEGA_INDEX_CONSTANT_0 = 31
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} Fx3GpifOmegaIndex_t;
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typedef struct {
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uint32_t config;
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uint32_t bus_config;
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uint32_t bus_config2;
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uint32_t ad_config;
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uint32_t status;
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uint32_t intr;
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uint32_t intr_mask;
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uint32_t serial_in_config;
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uint32_t serial_out_config;
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uint32_t ctrl_bus_direction;
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uint32_t ctrl_bus_default;
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uint32_t ctrl_bus_polarity;
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uint32_t ctrl_bus_toggle;
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uint32_t ctrl_bus_select[16];
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uint32_t ctrl_count_config;
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uint32_t ctrl_count_reset;
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uint32_t ctrl_count_limit;
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uint32_t addr_count_config;
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uint32_t addr_count_reset;
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uint32_t addr_count_limit;
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uint32_t state_count_config;
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uint32_t state_count_limit;
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uint32_t data_count_config;
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uint32_t data_count_reset;
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uint32_t data_count_limit;
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uint32_t ctrl_comp_value;
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uint32_t ctrl_comp_mask;
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uint32_t data_comp_value;
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uint32_t data_comp_mask;
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uint32_t addr_comp_value;
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uint32_t addr_comp_mask;
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uint32_t data_ctrl;
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uint32_t ingress_data[4];
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uint32_t egress_data[4];
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uint32_t ingress_address[4];
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uint32_t egress_address[4];
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uint32_t thread_config[4];
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uint32_t lambda_stat;
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uint32_t alpha_stat;
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uint32_t beta_stat;
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uint32_t waveform_ctrl_stat;
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uint32_t waveform_switch;
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uint32_t waveform_switch_timeout;
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uint32_t crc_config;
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uint32_t crc_data;
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uint32_t beta_deassert;
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} Fx3GpifRegisters_t;
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typedef enum {
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FX3_GPIF_INVALID = 0,
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FX3_GPIF_ARMED = 2,
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FX3_GPIF_RUNNING,
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FX3_GPIF_DONE,
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FX3_GPIF_PAUSED,
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FX3_GPIF_SWITCHING,
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FX3_GPIF_ERROR,
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} Fx3GpifStat_t;
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extern void Fx3GpifStart(uint8_t state, uint8_t alpha);
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extern void Fx3GpifStop(void);
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extern void Fx3GpifInvalidate(void);
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extern void Fx3GpifConfigure(const Fx3GpifWaveform_t *waveforms,
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uint16_t num_waveforms,
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const uint16_t *functions, uint16_t num_functions,
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const Fx3GpifRegisters_t *registers);
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extern void Fx3GpifConfigureCompat(const Fx3GpifWaveformCompat_t *waveforms,
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const uint8_t *waveform_select,
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uint16_t num_waveforms,
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const uint16_t *functions, uint16_t num_functions,
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const uint32_t *registers, uint16_t num_registers);
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extern void Fx3GpifPibStart(uint16_t clock_divisor_x2);
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extern void Fx3GpifPibStop(void);
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extern Fx3GpifStat_t Fx3GpifGetStat(uint8_t *current_state);
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#endif /* BSP_GPIF_H_ */
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