120 lines
6.8 KiB
C
120 lines
6.8 KiB
C
/*
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* Copyright (C) 2018 Marcus Comstedt
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef RDB_PIB_H_
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#define RDB_PIB_H_
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#define FX3_PIB_CONFIG 0xE0010000 /* PIB Configuration Register */
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#define FX3_PIB_INTR 0xE0010004 /* PIB Interrupt Request Register */
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#define FX3_PIB_INTR_MASK 0xE0010008 /* PIB Interrupt Mask Register */
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#define FX3_PIB_CLOCK_DETECT 0xE001000C /* PIB Clock Detector Configuration Register */
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#define FX3_PIB_RD_MAILBOX 0xE0010010 /* Read (Egress) Mailbox Register */
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#define FX3_PIB_WR_MAILBOX 0xE0010018 /* Write (Ingress) Mailbox Register */
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#define FX3_PIB_ERROR 0xE0010020 /* PIB Error Indicator Register */
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#define FX3_PIB EOP/EOT 0xE0010024 /* Configuration Register */
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#define FX3_PIB_DLL_CTRL 0xE0010028 /* DLL Configuration Register */
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#define FX3_PIB_WR_THRESHOLD 0xE001002C /* Write Threshold Register */
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#define FX3_PIB_RD_THRESHOLD 0xE0010030 /* Read Threshold Register */
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#define FX3_PIB_ID 0xE0017F00 /* Block Identification and Version Number Register */
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#define FX3_PIB_POWER 0xE0017F04 /* Power, Clock, and Reset Control Register */
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#define FX3_PIB_CONFIG_ENABLE (1UL << 31)
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#define FX3_PIB_CONFIG_MMIO_ENABLE (1UL << 30)
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#define FX3_PIB_CONFIG_PP_CFGMODE (1UL << 29)
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#define FX3_PIB_CONFIG_PCFG (1UL << 28)
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#define FX3_PIB_CONFIG_DEVICE_ID_SHIFT 8
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#define FX3_PIB_CONFIG_DEVICE_ID_BITS 8
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#define FX3_PIB_CONFIG_DEVICE_ID_MASK (0xffUL << 8)
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#define FX3_PIB_INTR_GPIF_ERR (1UL << 31)
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#define FX3_PIB_INTR_PIB_ERR (1UL << 29)
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#define FX3_PIB_INTR_RD_THRESHOLD (1UL << 10)
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#define FX3_PIB_INTR_WR_THRESHOLD (1UL << 9)
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#define FX3_PIB_INTR_CONFIG_CHANGE (1UL << 8)
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#define FX3_PIB_INTR_CLOCK_LOST (1UL << 7)
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#define FX3_PIB_INTR_DLL_LOST_LOCK (1UL << 6)
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#define FX3_PIB_INTR_DLL_LOCKED (1UL << 5)
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#define FX3_PIB_INTR_GPIF_INTERRUPT (1UL << 4)
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#define FX3_PIB_INTR_WR_MB_FULL (1UL << 1)
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#define FX3_PIB_INTR_RD_MB_EMPTY (1UL << 0)
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#define FX3_PIB_INTR_MASK_GPIF_ERR (1UL << 31)
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#define FX3_PIB_INTR_MASK_PIB_ERR (1UL << 29)
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#define FX3_PIB_INTR_MASK_RD_THRESHOLD (1UL << 10)
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#define FX3_PIB_INTR_MASK_WR_THRESHOLD (1UL << 9)
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#define FX3_PIB_INTR_MASK_CONFIG_CHANGE (1UL << 8)
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#define FX3_PIB_INTR_MASK_CLOCK_LOST (1UL << 7)
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#define FX3_PIB_INTR_MASK_DLL_LOST_LOCK (1UL << 6)
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#define FX3_PIB_INTR_MASK_DLL_LOCKED (1UL << 5)
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#define FX3_PIB_INTR_MASK_GPIF_INTERRUPT (1UL << 4)
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#define FX3_PIB_INTR_MASK_WR_MB_FULL (1UL << 1)
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#define FX3_PIB_INTR_MASK_RD_MB_EMPTY (1UL << 0)
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#define FX3_PIB_CLOCK_DETECT_ENABLE (1UL << 31)
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#define FX3_PIB_CLOCK_DETECT_CLOCK_PRESENT (1UL << 30)
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#define FX3_PIB_CLOCK_DETECT_INTF_CYCLES_SHIFT 16
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#define FX3_PIB_CLOCK_DETECT_INTF_CYCLES_BITS 4
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#define FX3_PIB_CLOCK_DETECT_INTF_CYCLES_MASK (0xfUL << 16)
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#define FX3_PIB_CLOCK_DETECT_BUS_CYCLES_SHIFT 0
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#define FX3_PIB_CLOCK_DETECT_BUS_CYCLES_BITS 16
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#define FX3_PIB_CLOCK_DETECT_BUS_CYCLES_MASK (0xffffUL << 0)
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#define FX3_PIB_RD_MAILBOX_PP_RD_MAILBOX_SHIFT 0
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#define FX3_PIB_RD_MAILBOX_PP_RD_MAILBOX_BITS 64
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#define FX3_PIB_RD_MAILBOX_PP_RD_MAILBOX_MASK (0xffffffffffffffffUL << 0)
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#define FX3_PIB_WR_MAILBOX_PP_WR_MAILBOX_SHIFT 0
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#define FX3_PIB_WR_MAILBOX_PP_WR_MAILBOX_BITS 64
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#define FX3_PIB_WR_MAILBOX_PP_WR_MAILBOX_MASK (0xffffffffffffffffUL << 0)
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#define FX3_PIB_ERROR_GPIF_ERR_CODE_SHIFT 10
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#define FX3_PIB_ERROR_GPIF_ERR_CODE_BITS 5
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#define FX3_PIB_ERROR_GPIF_ERR_CODE_MASK (0x1fUL << 10)
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#define FX3_PIB_ERROR_PIB_ERR_CODE_SHIFT 0
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#define FX3_PIB_ERROR_PIB_ERR_CODE_BITS 6
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#define FX3_PIB_ERROR_PIB_ERR_CODE_MASK (0x3fUL << 0)
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#define FX3_PIB_DLL_CTRL_ENABLE_RESET_ON_ERR (1UL << 31)
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#define FX3_PIB_DLL_CTRL_DLL_RESET_N (1UL << 30)
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#define FX3_PIB_DLL_CTRL_DLL_STAT (1UL << 2)
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#define FX3_PIB_DLL_CTRL_HIGH_FREQ (1UL << 1)
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#define FX3_PIB_DLL_CTRL_ENABLE (1UL << 0)
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#define FX3_PIB_WR_THRESHOLD_VALUE16_SHIFT 0
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#define FX3_PIB_WR_THRESHOLD_VALUE16_BITS 16
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#define FX3_PIB_WR_THRESHOLD_VALUE16_MASK (0xffffUL << 0)
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#define FX3_PIB_RD_THRESHOLD_VALUE16_SHIFT 0
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#define FX3_PIB_RD_THRESHOLD_VALUE16_BITS 16
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#define FX3_PIB_RD_THRESHOLD_VALUE16_MASK (0xffffUL << 0)
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#define FX3_PIB_ID_BLOCK_VERSION_SHIFT 16
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#define FX3_PIB_ID_BLOCK_VERSION_BITS 16
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#define FX3_PIB_ID_BLOCK_VERSION_MASK (0xffffUL << 16)
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#define FX3_PIB_ID_BLOCK_ID_SHIFT 0
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#define FX3_PIB_ID_BLOCK_ID_BITS 16
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#define FX3_PIB_ID_BLOCK_ID_MASK (0xffffUL << 0)
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#define FX3_PIB_POWER_RESETN (1UL << 31)
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#define FX3_PIB_POWER_ACTIVE (1UL << 0)
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#endif /* RDB_PIB_H_ */
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