more work..more work....
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parent
1af0d77575
commit
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53
src/main.rs
53
src/main.rs
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@ -1,6 +1,6 @@
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use byteorder::{ReadBytesExt, LE};
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use std::io::Cursor;
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use std::convert::TryInto;
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use std::convert::{TryInto, TryFrom};
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struct Machine {
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RX: u16,
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@ -18,6 +18,19 @@ struct Machine {
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IP: u16,
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}
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impl Machine {
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fn push_stack(&mut self, val: u16) {
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self.SSK[self.RSK as usize] = val;
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self.RSK -= 1;
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}
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fn pop_stack(&mut self) -> u16 {
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let v = self.SSK[self.RSK as usize];
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self.RSK += 1;
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v
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}
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}
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impl Machine {
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fn write_reg(&mut self, reg: Register, val: u16) {
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match reg {
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@ -440,6 +453,8 @@ impl Machine {
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let oc = cur_instruction.def.opcode();
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let mut should_inc_ip = true;
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match oc {
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OP::HALT => return false,
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OP::NOOP => {},
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@ -453,8 +468,21 @@ impl Machine {
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OP::CALL => {
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if self.RTRGT == 0 {
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} else {
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unimplemented!("calling not implemented");
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self.push_stack(self.RCALL);
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self.push_stack(self.RSTAT.bits());
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self.push_stack(self.RX);
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self.push_stack(self.RY);
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self.push_stack(self.RZ);
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self.push_stack(u16::try_from(inc_by).unwrap());
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self.RSR = self.RSK;
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self.RX = self.read(cur_instruction.args[0]);
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self.RY = self.read(cur_instruction.args[1]);
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self.RZ = self.read(cur_instruction.args[2]);
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self.RCALL = self.IP;
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self.IP = self.RTRGT;
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should_inc_ip = false;
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self.RTRGT = 0;
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self.RSTAT = Flags::empty();
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}
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}
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OP::POP => {
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@ -481,13 +509,28 @@ impl Machine {
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}
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OP::JEQU => {
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if self.RSTAT.contains(Flags::FEQUL) {
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unimplemented!("{:?}", self.RTRGT);
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self.IP = self.RTRGT;
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should_inc_ip = false;
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}
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}
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OP::INC => {
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let mut val = self.read(cur_instruction.args[0]);
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val += 1;
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self.write(cur_instruction.args[0], val);
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self.RSTAT.set(Flags::FZERO, val == 0);
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}
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OP::READ => {
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let input = 50;
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self.write(cur_instruction.args[0], input);
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self.RSTAT.set(Flags::FZERO, input == 0);
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}
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_ => { eprintln!("unsupported opcode {:?}, continuing", oc); return false; }
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}
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self.IP += inc_by as u16;
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if should_inc_ip {
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self.IP += inc_by as u16;
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}
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true
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}
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