2013-02-12 01:07:04 +00:00
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/*
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* This program source code file is part of KiCad, a free EDA CAD application.
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*
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2015-01-30 18:42:46 +00:00
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* Copyright (C) 1992-2015 KiCad Developers, see AUTHORS.txt for contributors.
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2013-02-12 01:07:04 +00:00
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you may find one here:
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* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
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* or you may search the http://www.gnu.org website for the version 2 license,
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* or you may write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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2011-09-23 13:57:12 +00:00
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/**
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2018-02-02 20:57:12 +00:00
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* @file board_design_settings.cpp
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2011-09-23 13:57:12 +00:00
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* BOARD_DESIGN_SETTINGS class functions.
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*/
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2012-01-23 04:33:36 +00:00
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#include <fctsys.h>
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#include <common.h>
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2018-04-28 15:22:25 +00:00
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#include <class_board.h>
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2012-01-23 04:33:36 +00:00
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#include <layers_id_colors_and_visibility.h>
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2018-04-28 15:22:25 +00:00
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#include <kiface_i.h>
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2012-01-23 04:33:36 +00:00
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#include <pcbnew.h>
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2018-02-02 20:57:12 +00:00
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#include <board_design_settings.h>
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2009-10-28 11:48:47 +00:00
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2018-04-14 14:58:01 +00:00
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2018-04-28 15:22:25 +00:00
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#define CopperLayerCountKey wxT( "CopperLayerCount" )
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#define BoardThicknessKey wxT( "BoardThickness" )
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#define LayerKeyPrefix wxT( "Layer" )
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#define LayerNameKey wxT( "Name" )
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#define LayerTypeKey wxT( "Type" )
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2019-03-07 04:55:14 +00:00
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#define LayerEnabledKey wxT( "Enabled" )
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2018-04-28 15:22:25 +00:00
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#define NetclassNameKey wxT( "Name" )
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#define ClearanceKey wxT( "Clearance" )
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#define TrackWidthKey wxT( "TrackWidth" )
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#define ViaDiameterKey wxT( "ViaDiameter" )
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#define ViaDrillKey wxT( "ViaDrill" )
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#define uViaDiameterKey wxT( "uViaDiameter" )
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#define uViaDrillKey wxT( "uViaDrill" )
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#define dPairWidthKey wxT( "dPairWidth" )
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#define dPairGapKey wxT( "dPairGap" )
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#define dPairViaGapKey wxT( "dPairViaGap" )
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//
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// NOTE: layer configuration info is stored in both the BOARD and BOARD_DESIGN_SETTINGS so one
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// of the two needs to read/write the config so we don't end up with order dependency issues.
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//
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class PARAM_CFG_LAYERS : public PARAM_CFG_BASE
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{
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protected:
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BOARD* m_Pt_param; ///< Pointer to the parameter value
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public:
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PARAM_CFG_LAYERS( BOARD* ptparam, const wxChar* group = nullptr ) :
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PARAM_CFG_BASE( wxEmptyString, PARAM_LAYERS, group )
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{
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m_Pt_param = ptparam;
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}
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void ReadParam( wxConfigBase* aConfig ) const override
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{
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if( !m_Pt_param || !aConfig )
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return;
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BOARD* board = m_Pt_param;
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BOARD_DESIGN_SETTINGS& bds = board->GetDesignSettings();
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2019-03-07 04:55:14 +00:00
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LSET enabledLayers = bds.GetEnabledLayers();
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2018-04-28 15:22:25 +00:00
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wxString oldPath = aConfig->GetPath();
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2019-03-07 04:55:14 +00:00
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wxString layerKeyPrefix = LayerKeyPrefix;
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2018-04-28 15:22:25 +00:00
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bds.SetCopperLayerCount( aConfig->Read( CopperLayerCountKey, 2 ) );
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double thickness = aConfig->ReadDouble( BoardThicknessKey, DEFAULT_BOARD_THICKNESS_MM );
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bds.SetBoardThickness( Millimeter2iu( thickness ) );
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2019-03-07 04:55:14 +00:00
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for( LSEQ seq = LSET::AllLayersMask().Seq(); seq; ++seq )
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2018-04-28 15:22:25 +00:00
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{
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PCB_LAYER_ID layer = *seq;
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2019-03-07 04:55:14 +00:00
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wxString path = layerKeyPrefix + wxT( "." ) + board->GetStandardLayerName( layer );
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2018-04-28 15:22:25 +00:00
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wxString layerName;
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int layerType;
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2019-03-07 04:55:14 +00:00
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bool layerEnabled;
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2018-04-28 15:22:25 +00:00
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aConfig->SetPath( oldPath );
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2019-03-07 04:55:14 +00:00
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aConfig->SetPath( path );
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2018-04-28 15:22:25 +00:00
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if( aConfig->Read( LayerNameKey, &layerName ) )
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board->SetLayerName( layer, layerName );
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if( aConfig->Read( LayerTypeKey, &layerType ) )
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board->SetLayerType( layer, (LAYER_T) layerType );
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2019-03-07 04:55:14 +00:00
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if( aConfig->Read( LayerEnabledKey, &layerEnabled ) )
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enabledLayers.set( layer, layerEnabled );
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2018-04-28 15:22:25 +00:00
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}
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2019-03-07 04:55:14 +00:00
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board->SetEnabledLayers( enabledLayers );
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2018-04-28 15:22:25 +00:00
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aConfig->SetPath( oldPath );
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}
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void SaveParam( wxConfigBase* aConfig ) const override
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{
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if( !m_Pt_param || !aConfig )
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return;
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BOARD* board = m_Pt_param;
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BOARD_DESIGN_SETTINGS& bds = board->GetDesignSettings();
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wxString oldPath = aConfig->GetPath();
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wxString layerKeyPrefix = LayerKeyPrefix;
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aConfig->Write( CopperLayerCountKey, board->GetCopperLayerCount() );
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aConfig->Write( BoardThicknessKey, Iu2Millimeter( bds.GetBoardThickness() ) );
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2019-03-07 04:55:14 +00:00
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for( LSEQ seq = LSET::AllLayersMask().Seq(); seq; ++seq )
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2018-04-28 15:22:25 +00:00
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{
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PCB_LAYER_ID layer = *seq;
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2019-03-07 04:55:14 +00:00
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wxString path = layerKeyPrefix + wxT( "." ) + board->GetStandardLayerName( layer );
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wxString layerName = board->GetLayerName( layer );
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LAYER_T layerType = board->GetLayerType( layer );
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2018-04-28 15:22:25 +00:00
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aConfig->SetPath( oldPath );
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2019-03-07 04:55:14 +00:00
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aConfig->SetPath( path );
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2018-04-28 15:22:25 +00:00
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2019-03-07 04:55:14 +00:00
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if( IsCopperLayer( layer ) )
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2018-04-28 15:22:25 +00:00
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{
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aConfig->Write( LayerNameKey, layerName );
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aConfig->Write( LayerTypeKey, (int) layerType );
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}
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2019-03-07 04:55:14 +00:00
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aConfig->Write( LayerEnabledKey, board->IsLayerEnabled( layer ) );
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2018-04-28 15:22:25 +00:00
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}
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aConfig->SetPath( oldPath );
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}
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};
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class PARAM_CFG_TRACKWIDTHS : public PARAM_CFG_BASE
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{
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protected:
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std::vector<int>* m_Pt_param; ///< Pointer to the parameter value
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public:
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PARAM_CFG_TRACKWIDTHS( std::vector<int>* ptparam, const wxChar* group = nullptr ) :
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PARAM_CFG_BASE( wxEmptyString, PARAM_TRACKWIDTHS, group )
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{
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m_Pt_param = ptparam;
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}
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void ReadParam( wxConfigBase* aConfig ) const override
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{
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if( !m_Pt_param || !aConfig )
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return;
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m_Pt_param->clear();
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for( int index = 1; ; ++index )
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{
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wxString key = TrackWidthKey;
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double width;
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if( !aConfig->Read( key << index, &width ) )
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break;
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m_Pt_param->push_back( Millimeter2iu( width ) );
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}
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}
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void SaveParam( wxConfigBase* aConfig ) const override
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{
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if( !m_Pt_param || !aConfig )
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return;
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for( size_t index = 1; index <= m_Pt_param->size(); ++index )
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{
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wxString key = TrackWidthKey;
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aConfig->Write( key << index, Iu2Millimeter( m_Pt_param->at( index - 1 ) ) );
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}
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}
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};
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class PARAM_CFG_VIADIMENSIONS : public PARAM_CFG_BASE
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{
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protected:
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std::vector<VIA_DIMENSION>* m_Pt_param; ///< Pointer to the parameter value
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public:
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PARAM_CFG_VIADIMENSIONS( std::vector<VIA_DIMENSION>* ptparam, const wxChar* group = nullptr ) :
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PARAM_CFG_BASE( wxEmptyString, PARAM_VIADIMENSIONS, group )
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{
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m_Pt_param = ptparam;
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}
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void ReadParam( wxConfigBase* aConfig ) const override
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{
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if( !m_Pt_param || !aConfig )
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return;
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m_Pt_param->clear();
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for( int index = 1; ; ++index )
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{
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double diameter = 0.0, drill = 0.0;
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wxString key = ViaDiameterKey;
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if( !aConfig->Read( key << index, &diameter ) )
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break;
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key = ViaDrillKey;
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drill = aConfig->ReadDouble( key << index, 0.0 );
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m_Pt_param->emplace_back( VIA_DIMENSION( Millimeter2iu( diameter ),
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Millimeter2iu( drill ) ) );
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}
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}
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void SaveParam( wxConfigBase* aConfig ) const override
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{
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if( !m_Pt_param || !aConfig )
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return;
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for( size_t index = 1; index <= m_Pt_param->size(); ++index )
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{
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wxString key = ViaDiameterKey;
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aConfig->Write( key << index, Iu2Millimeter( m_Pt_param->at( index - 1 ).m_Diameter ) );
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key = ViaDrillKey;
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aConfig->Write( key << index, Iu2Millimeter( m_Pt_param->at( index - 1 ).m_Drill ) );
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}
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}
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};
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class PARAM_CFG_DIFFPAIRDIMENSIONS : public PARAM_CFG_BASE
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{
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protected:
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std::vector<DIFF_PAIR_DIMENSION>* m_Pt_param; ///< Pointer to the parameter value
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public:
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PARAM_CFG_DIFFPAIRDIMENSIONS( std::vector<DIFF_PAIR_DIMENSION>* ptparam,
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const wxChar* group = nullptr ) :
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PARAM_CFG_BASE( wxEmptyString, PARAM_DIFFPAIRDIMENSIONS, group )
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{
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m_Pt_param = ptparam;
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}
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void ReadParam( wxConfigBase* aConfig ) const override
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{
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if( !m_Pt_param || !aConfig )
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return;
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m_Pt_param->clear();
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for( int index = 1; ; ++index )
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{
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double width, gap, viagap;
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wxString key = dPairWidthKey;
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if( !aConfig->Read( key << index, &width ) )
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break;
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key = dPairGapKey;
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gap = aConfig->ReadDouble( key << index, 0.0 );
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key = dPairViaGapKey;
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viagap = aConfig->ReadDouble( key << index, 0.0 );
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m_Pt_param->emplace_back( DIFF_PAIR_DIMENSION( Millimeter2iu( width ),
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Millimeter2iu( gap ),
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Millimeter2iu( viagap ) ) );
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}
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}
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void SaveParam( wxConfigBase* aConfig ) const override
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{
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if( !m_Pt_param || !aConfig )
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return;
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for( size_t index = 1; index <= m_Pt_param->size(); ++index )
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{
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wxString key = dPairWidthKey;
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aConfig->Write( key << index, Iu2Millimeter( m_Pt_param->at( index - 1 ).m_Width ) );
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key = dPairGapKey;
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aConfig->Write( key << index, Iu2Millimeter( m_Pt_param->at( index - 1 ).m_Gap ) );
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key = dPairViaGapKey;
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aConfig->Write( key << index, Iu2Millimeter( m_Pt_param->at( index - 1 ).m_ViaGap ) );
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}
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}
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};
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class PARAM_CFG_NETCLASSES : public PARAM_CFG_BASE
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{
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protected:
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NETCLASSES* m_Pt_param; ///< Pointer to the parameter value
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public:
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PARAM_CFG_NETCLASSES( const wxChar* ident, NETCLASSES* ptparam,
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const wxChar* group = nullptr ) :
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PARAM_CFG_BASE( ident, PARAM_NETCLASSES, group )
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{
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m_Pt_param = ptparam;
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}
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void ReadParam( wxConfigBase* aConfig ) const override
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{
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if( !m_Pt_param || !aConfig )
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return;
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wxString oldPath = aConfig->GetPath();
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m_Pt_param->Clear();
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2019-03-07 04:55:14 +00:00
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for( int index = 0; ; ++index )
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2018-04-28 15:22:25 +00:00
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{
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2019-03-07 04:55:14 +00:00
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wxString path = "";
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NETCLASSPTR netclass;
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wxString netclassName;
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if( index == 0 )
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path = "Default";
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else
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path << index;
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2018-04-28 15:22:25 +00:00
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aConfig->SetPath( oldPath );
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aConfig->SetPath( m_Ident );
|
2019-03-07 04:55:14 +00:00
|
|
|
aConfig->SetPath( path );
|
2018-04-28 15:22:25 +00:00
|
|
|
|
|
|
|
if( !aConfig->Read( NetclassNameKey, &netclassName ) )
|
|
|
|
break;
|
|
|
|
|
2019-03-07 04:55:14 +00:00
|
|
|
if( index == 0 )
|
|
|
|
netclass = m_Pt_param->GetDefault();
|
|
|
|
else
|
|
|
|
netclass = std::make_shared<NETCLASS>( netclassName );
|
2018-04-28 15:22:25 +00:00
|
|
|
|
|
|
|
#define READ_MM( aKey, aDefault ) Millimeter2iu( aConfig->ReadDouble( aKey, aDefault ) )
|
|
|
|
netclass->SetClearance( READ_MM( ClearanceKey, netclass->GetClearance() ) );
|
|
|
|
netclass->SetTrackWidth( READ_MM( TrackWidthKey, netclass->GetTrackWidth() ) );
|
|
|
|
netclass->SetViaDiameter( READ_MM( ViaDiameterKey, netclass->GetViaDiameter() ) );
|
|
|
|
netclass->SetViaDrill( READ_MM( ViaDrillKey, netclass->GetViaDrill() ) );
|
|
|
|
netclass->SetuViaDiameter( READ_MM( uViaDiameterKey, netclass->GetuViaDiameter() ) );
|
|
|
|
netclass->SetuViaDrill( READ_MM( uViaDrillKey, netclass->GetuViaDrill() ) );
|
|
|
|
netclass->SetDiffPairWidth( READ_MM( dPairWidthKey, netclass->GetDiffPairWidth() ) );
|
|
|
|
netclass->SetDiffPairGap( READ_MM( dPairGapKey, netclass->GetDiffPairGap() ) );
|
|
|
|
netclass->SetDiffPairViaGap( READ_MM( dPairViaGapKey, netclass->GetDiffPairViaGap() ) );
|
|
|
|
|
2019-03-07 04:55:14 +00:00
|
|
|
if( index > 0 )
|
|
|
|
m_Pt_param->Add( netclass );
|
2018-04-28 15:22:25 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
aConfig->SetPath( oldPath );
|
|
|
|
}
|
|
|
|
|
|
|
|
void SaveParam( wxConfigBase* aConfig ) const override
|
|
|
|
{
|
|
|
|
if( !m_Pt_param || !aConfig )
|
|
|
|
return;
|
|
|
|
|
2019-03-07 04:55:14 +00:00
|
|
|
wxString oldPath = aConfig->GetPath();
|
|
|
|
NETCLASSES::const_iterator nc = m_Pt_param->begin();
|
2018-04-28 15:22:25 +00:00
|
|
|
|
2019-04-02 06:25:34 +00:00
|
|
|
for( unsigned index = 0; index <= m_Pt_param->GetCount(); ++index )
|
2018-04-28 15:22:25 +00:00
|
|
|
{
|
2019-03-07 04:55:14 +00:00
|
|
|
wxString path = "";
|
|
|
|
NETCLASSPTR netclass;
|
|
|
|
|
|
|
|
if( index == 0 )
|
|
|
|
path = "Default";
|
|
|
|
else
|
|
|
|
path << index;
|
2018-04-28 15:22:25 +00:00
|
|
|
|
|
|
|
aConfig->SetPath( oldPath );
|
|
|
|
aConfig->SetPath( m_Ident );
|
2019-03-07 04:55:14 +00:00
|
|
|
aConfig->SetPath( path );
|
|
|
|
|
|
|
|
if( index == 0 )
|
|
|
|
{
|
|
|
|
netclass = m_Pt_param->GetDefault();
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
netclass = nc->second;
|
|
|
|
++nc;
|
|
|
|
}
|
2018-04-28 15:22:25 +00:00
|
|
|
|
|
|
|
aConfig->Write( NetclassNameKey, netclass->GetName() );
|
|
|
|
|
|
|
|
#define WRITE_MM( aKey, aValue ) aConfig->Write( aKey, Iu2Millimeter( aValue ) )
|
|
|
|
WRITE_MM( ClearanceKey, netclass->GetClearance() );
|
|
|
|
WRITE_MM( TrackWidthKey, netclass->GetTrackWidth() );
|
|
|
|
WRITE_MM( ViaDiameterKey, netclass->GetViaDiameter() );
|
|
|
|
WRITE_MM( ViaDrillKey, netclass->GetViaDrill() );
|
|
|
|
WRITE_MM( uViaDiameterKey, netclass->GetuViaDiameter() );
|
|
|
|
WRITE_MM( uViaDrillKey, netclass->GetuViaDrill() );
|
|
|
|
WRITE_MM( dPairWidthKey, netclass->GetDiffPairWidth() );
|
|
|
|
WRITE_MM( dPairGapKey, netclass->GetDiffPairGap() );
|
|
|
|
WRITE_MM( dPairViaGapKey, netclass->GetDiffPairViaGap() );
|
|
|
|
}
|
|
|
|
|
|
|
|
aConfig->SetPath( oldPath );
|
|
|
|
}
|
|
|
|
};
|
2009-10-28 11:48:47 +00:00
|
|
|
|
|
|
|
|
2012-02-19 04:02:19 +00:00
|
|
|
BOARD_DESIGN_SETTINGS::BOARD_DESIGN_SETTINGS() :
|
BOARD_CONNECTED_ITEMs do not store net code anymore (m_NetCode field), instead net info is stored using a pointer to NETINFO_ITEM.
GetNet() refers to the net code stored in the NETINFO_ITEM. SetNet() finds an appropriate NETINFO_ITEM and uses it.
Removing GetNet() & SetNet() (and the whole net code idea) requires too many changes in the code (~250 references to the mentioned functions).
BOARD_CONNECTED_ITEMs by default get a pointer to NETINFO_ITEM that stores unconnected items. This requires for all BOARD_CONNECTED_ITEMs to have a parent (so BOARD* is accessible). The only orphaned item is BOARD_DESIGN_SETTINGS::m_Pad_Master, but it does not cause any issues so far.
Items that do not have access to a BOARD (do not have set parents) and therefore cannot get net assigned, by default get const static NETINFO_LIST::ORPHANED.
Performed tests:
- loaded .kicad_pcb, KiCad legacy board, Eagle 6.0 board, P-CAD board - all ok
- load a simple project, reload netlist after changing connections in eeschema - ok
- save & reload a board - ok, but still contain empty nets
- remove everything, restore with undo - ok
- remove everything, reload netlist - ok
- changing net names (all possibilites: empty->existing, empty->not existing, existing->empty, existing->not existing) - all ok
- zones: when net is changed to a net that does not have any nodes besides the zone itself, it does not get filled
2014-01-15 17:03:06 +00:00
|
|
|
m_Pad_Master( NULL )
|
2009-10-28 11:48:47 +00:00
|
|
|
{
|
2018-04-28 15:22:25 +00:00
|
|
|
LSET all_set = LSET().set();
|
2012-02-06 05:44:19 +00:00
|
|
|
|
2014-06-30 15:46:47 +00:00
|
|
|
m_enabledLayers = all_set; // All layers enabled at first.
|
|
|
|
// SetCopperLayerCount() will adjust this.
|
2014-06-24 16:17:18 +00:00
|
|
|
SetVisibleLayers( all_set );
|
2012-02-06 05:44:19 +00:00
|
|
|
|
|
|
|
// set all but hidden text as visible.
|
2017-03-13 03:19:33 +00:00
|
|
|
m_visibleElements = ~( 1 << GAL_LAYER_INDEX( LAYER_MOD_TEXT_INVISIBLE ) );
|
2011-09-23 13:57:12 +00:00
|
|
|
|
2014-06-30 15:46:47 +00:00
|
|
|
SetCopperLayerCount( 2 ); // Default design is a double sided board
|
2011-09-23 13:57:12 +00:00
|
|
|
|
|
|
|
m_CurrentViaType = VIA_THROUGH;
|
|
|
|
|
|
|
|
// if true, when creating a new track starting on an existing track, use this track width
|
|
|
|
m_UseConnectedTrackWidth = false;
|
|
|
|
|
2018-04-28 15:22:25 +00:00
|
|
|
m_BlindBuriedViaAllowed = false;
|
|
|
|
m_MicroViasAllowed = false;
|
|
|
|
|
|
|
|
m_LineThickness[ LAYER_CLASS_SILK ] = Millimeter2iu( DEFAULT_SILK_LINE_WIDTH );
|
|
|
|
m_TextSize[ LAYER_CLASS_SILK ] = wxSize( Millimeter2iu( DEFAULT_SILK_TEXT_SIZE ),
|
|
|
|
Millimeter2iu( DEFAULT_SILK_TEXT_SIZE ) );
|
|
|
|
m_TextThickness[ LAYER_CLASS_SILK ] = Millimeter2iu( DEFAULT_SILK_TEXT_WIDTH );
|
|
|
|
m_TextItalic[ LAYER_CLASS_SILK ] = false;
|
|
|
|
m_TextUpright[ LAYER_CLASS_SILK ] = true;
|
|
|
|
|
|
|
|
m_LineThickness[ LAYER_CLASS_COPPER ] = Millimeter2iu( DEFAULT_COPPER_LINE_WIDTH );
|
|
|
|
m_TextSize[ LAYER_CLASS_COPPER ] = wxSize( Millimeter2iu( DEFAULT_COPPER_TEXT_SIZE ),
|
|
|
|
Millimeter2iu( DEFAULT_COPPER_TEXT_SIZE ) );
|
|
|
|
m_TextThickness[ LAYER_CLASS_COPPER ] = Millimeter2iu( DEFAULT_COPPER_TEXT_WIDTH );
|
|
|
|
m_TextItalic[ LAYER_CLASS_COPPER ] = false;
|
|
|
|
m_TextUpright[ LAYER_CLASS_COPPER ] = true;
|
|
|
|
|
|
|
|
// Edges & Courtyards; text properties aren't used but better to have them holding
|
|
|
|
// reasonable values than not.
|
|
|
|
m_LineThickness[ LAYER_CLASS_EDGES ] = Millimeter2iu( DEFAULT_EDGE_WIDTH );
|
|
|
|
m_TextSize[ LAYER_CLASS_EDGES ] = wxSize( Millimeter2iu( DEFAULT_TEXT_SIZE ),
|
|
|
|
Millimeter2iu( DEFAULT_TEXT_SIZE ) );
|
|
|
|
m_TextThickness[ LAYER_CLASS_EDGES ] = Millimeter2iu( DEFAULT_TEXT_WIDTH );
|
|
|
|
m_TextItalic[ LAYER_CLASS_EDGES ] = false;
|
|
|
|
m_TextUpright[ LAYER_CLASS_EDGES ] = true;
|
|
|
|
|
2018-08-24 20:08:30 +00:00
|
|
|
m_LineThickness[ LAYER_CLASS_COURTYARD ] = Millimeter2iu( DEFAULT_COURTYARD_WIDTH );
|
|
|
|
m_TextSize[ LAYER_CLASS_COURTYARD ] = wxSize( Millimeter2iu( DEFAULT_TEXT_SIZE ),
|
|
|
|
Millimeter2iu( DEFAULT_TEXT_SIZE ) );
|
|
|
|
m_TextThickness[ LAYER_CLASS_COURTYARD ] = Millimeter2iu( DEFAULT_TEXT_WIDTH );
|
|
|
|
m_TextItalic[ LAYER_CLASS_COURTYARD ] = false;
|
|
|
|
m_TextUpright[ LAYER_CLASS_COURTYARD ] = true;
|
|
|
|
|
2018-04-28 15:22:25 +00:00
|
|
|
m_LineThickness[ LAYER_CLASS_OTHERS ] = Millimeter2iu( DEFAULT_LINE_WIDTH );
|
|
|
|
m_TextSize[ LAYER_CLASS_OTHERS ] = wxSize( Millimeter2iu( DEFAULT_TEXT_SIZE ),
|
|
|
|
Millimeter2iu( DEFAULT_TEXT_SIZE ) );
|
|
|
|
m_TextThickness[ LAYER_CLASS_OTHERS ] = Millimeter2iu( DEFAULT_TEXT_WIDTH );
|
|
|
|
m_TextItalic[ LAYER_CLASS_OTHERS ] = false;
|
|
|
|
m_TextUpright[ LAYER_CLASS_OTHERS ] = true;
|
2012-04-08 23:32:32 +00:00
|
|
|
|
2015-02-15 22:21:52 +00:00
|
|
|
m_useCustomTrackVia = false;
|
2015-03-13 16:48:42 +00:00
|
|
|
m_customTrackWidth = Millimeter2iu( DEFAULT_CUSTOMTRACKWIDTH );
|
2015-06-15 15:54:58 +00:00
|
|
|
m_customViaSize.m_Diameter = Millimeter2iu( DEFAULT_VIASMINSIZE );
|
|
|
|
m_customViaSize.m_Drill = Millimeter2iu( DEFAULT_VIASMINDRILL );
|
|
|
|
|
2018-04-28 15:22:25 +00:00
|
|
|
m_useCustomDiffPair = false;
|
|
|
|
m_customDiffPair.m_Width = Millimeter2iu( DEFAULT_CUSTOMDPAIRWIDTH );
|
|
|
|
m_customDiffPair.m_Gap = Millimeter2iu( DEFAULT_CUSTOMDPAIRGAP );
|
|
|
|
m_customDiffPair.m_ViaGap = Millimeter2iu( DEFAULT_CUSTOMDPAIRVIAGAP );
|
|
|
|
|
2019-04-05 16:10:59 +00:00
|
|
|
m_TrackMinWidth = Millimeter2iu( DEFAULT_TRACKMINWIDTH );
|
|
|
|
m_ViasMinSize = Millimeter2iu( DEFAULT_VIASMINSIZE );
|
|
|
|
m_ViasMinDrill = Millimeter2iu( DEFAULT_VIASMINDRILL );
|
|
|
|
m_MicroViasMinSize = Millimeter2iu( DEFAULT_MICROVIASMINSIZE );
|
|
|
|
m_MicroViasMinDrill = Millimeter2iu( DEFAULT_MICROVIASMINDRILL );
|
|
|
|
m_CopperEdgeClearance = Millimeter2iu( DEFAULT_COPPEREDGECLEARANCE );
|
2009-12-07 06:16:11 +00:00
|
|
|
|
2009-11-04 19:08:08 +00:00
|
|
|
// Global mask margins:
|
2018-04-28 15:22:25 +00:00
|
|
|
m_SolderMaskMargin = Millimeter2iu( DEFAULT_SOLDERMASK_CLEARANCE );
|
|
|
|
m_SolderMaskMinWidth = Millimeter2iu( DEFAULT_SOLDERMASK_MIN_WIDTH );
|
2011-09-23 13:57:12 +00:00
|
|
|
m_SolderPasteMargin = 0; // Solder paste margin absolute value
|
2018-04-28 15:22:25 +00:00
|
|
|
m_SolderPasteMarginRatio = 0.0; // Solder paste margin as a ratio of pad size
|
2011-09-23 13:57:12 +00:00
|
|
|
// The final margin is the sum of these 2 values
|
|
|
|
// Usually < 0 because the mask is smaller than pad
|
|
|
|
// Layer thickness for 3D viewer
|
2012-10-17 10:57:21 +00:00
|
|
|
m_boardThickness = Millimeter2iu( DEFAULT_BOARD_THICKNESS_MM );
|
2014-05-13 09:22:51 +00:00
|
|
|
|
|
|
|
m_viaSizeIndex = 0;
|
|
|
|
m_trackWidthIndex = 0;
|
2018-04-28 15:22:25 +00:00
|
|
|
m_diffPairIndex = 0;
|
2015-01-30 18:42:46 +00:00
|
|
|
|
2018-04-28 15:22:25 +00:00
|
|
|
// Default ref text on fp creation. If empty, use footprint name as default
|
2015-01-30 18:42:46 +00:00
|
|
|
m_RefDefaultText = wxT( "REF**" );
|
2018-04-28 15:22:25 +00:00
|
|
|
m_RefDefaultVisibility = true;
|
|
|
|
m_RefDefaultlayer = int( F_SilkS );
|
|
|
|
// Default value text on fp creation. If empty, use footprint name as default
|
2015-01-30 18:42:46 +00:00
|
|
|
m_ValueDefaultText = wxEmptyString;
|
|
|
|
m_ValueDefaultVisibility = true;
|
|
|
|
m_ValueDefaultlayer = int( F_Fab );
|
2009-10-28 11:48:47 +00:00
|
|
|
}
|
|
|
|
|
2012-10-17 10:57:21 +00:00
|
|
|
// Add parameters to save in project config.
|
|
|
|
// values are saved in mm
|
2018-04-28 15:22:25 +00:00
|
|
|
void BOARD_DESIGN_SETTINGS::AppendConfigs( BOARD* aBoard, PARAM_CFG_ARRAY* aResult )
|
2012-02-19 04:02:19 +00:00
|
|
|
{
|
2018-04-28 15:22:25 +00:00
|
|
|
aResult->push_back( new PARAM_CFG_LAYERS( aBoard ) );
|
|
|
|
|
|
|
|
aResult->push_back( new PARAM_CFG_BOOL( wxT( "AllowMicroVias" ),
|
|
|
|
&m_MicroViasAllowed, false ) );
|
|
|
|
|
|
|
|
aResult->push_back( new PARAM_CFG_BOOL( wxT( "AllowBlindVias" ),
|
|
|
|
&m_BlindBuriedViaAllowed, false ) );
|
|
|
|
|
|
|
|
aResult->push_back( new PARAM_CFG_BOOL( wxT( "RequireCourtyardDefinitions" ),
|
|
|
|
&m_RequireCourtyards, false ) );
|
|
|
|
|
|
|
|
aResult->push_back( new PARAM_CFG_BOOL( wxT( "ProhibitOverlappingCourtyards" ),
|
|
|
|
&m_ProhibitOverlappingCourtyards, true ) );
|
|
|
|
|
|
|
|
aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "MinTrackWidth" ),
|
|
|
|
&m_TrackMinWidth,
|
|
|
|
Millimeter2iu( DEFAULT_TRACKMINWIDTH ), Millimeter2iu( 0.01 ), Millimeter2iu( 25.0 ),
|
|
|
|
nullptr, MM_PER_IU ) );
|
|
|
|
|
|
|
|
aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "MinViaDiameter" ),
|
|
|
|
&m_ViasMinSize,
|
|
|
|
Millimeter2iu( DEFAULT_VIASMINSIZE ), Millimeter2iu( 0.01 ), Millimeter2iu( 25.0 ),
|
|
|
|
nullptr, MM_PER_IU ) );
|
|
|
|
|
|
|
|
aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "MinViaDrill" ),
|
|
|
|
&m_ViasMinDrill,
|
|
|
|
Millimeter2iu( DEFAULT_VIASMINDRILL ), Millimeter2iu( 0.01 ), Millimeter2iu( 25.0 ),
|
|
|
|
nullptr, MM_PER_IU ) );
|
|
|
|
|
|
|
|
aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "MinMicroViaDiameter" ),
|
|
|
|
&m_MicroViasMinSize,
|
|
|
|
Millimeter2iu( DEFAULT_MICROVIASMINSIZE ), Millimeter2iu( 0.01 ), Millimeter2iu( 10.0 ),
|
|
|
|
nullptr, MM_PER_IU ) );
|
|
|
|
|
|
|
|
aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "MinMicroViaDrill" ),
|
|
|
|
&m_MicroViasMinDrill,
|
|
|
|
Millimeter2iu( DEFAULT_MICROVIASMINDRILL ), Millimeter2iu( 0.01 ), Millimeter2iu( 10.0 ),
|
|
|
|
nullptr, MM_PER_IU ) );
|
|
|
|
|
|
|
|
aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "MinHoleToHole" ),
|
|
|
|
&m_HoleToHoleMin,
|
2019-04-05 16:10:59 +00:00
|
|
|
Millimeter2iu( DEFAULT_HOLETOHOLEMIN ), Millimeter2iu( 0.0 ), Millimeter2iu( 10.0 ),
|
|
|
|
nullptr, MM_PER_IU ) );
|
|
|
|
|
|
|
|
// Note: a clearance of -0.01 is a flag indicating we should use the legacy (pre-6.0) method
|
|
|
|
// based on the edge cut thicknesses.
|
|
|
|
aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "CopperEdgeClearance" ),
|
|
|
|
&m_CopperEdgeClearance,
|
|
|
|
Millimeter2iu( LEGACY_COPPEREDGECLEARANCE ), Millimeter2iu( -0.01 ), Millimeter2iu( 25.0 ),
|
2018-04-28 15:22:25 +00:00
|
|
|
nullptr, MM_PER_IU ) );
|
|
|
|
|
|
|
|
aResult->push_back( new PARAM_CFG_TRACKWIDTHS( &m_TrackWidthList ) );
|
|
|
|
aResult->push_back( new PARAM_CFG_VIADIMENSIONS( &m_ViasDimensionsList ) );
|
|
|
|
aResult->push_back( new PARAM_CFG_DIFFPAIRDIMENSIONS( &m_DiffPairDimensionsList ) );
|
|
|
|
|
|
|
|
aResult->push_back( new PARAM_CFG_NETCLASSES( wxT( "Netclasses" ), &m_NetClasses ) );
|
|
|
|
|
|
|
|
aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "SilkLineWidth" ),
|
|
|
|
&m_LineThickness[ LAYER_CLASS_SILK ],
|
|
|
|
Millimeter2iu( DEFAULT_SILK_LINE_WIDTH ), Millimeter2iu( 0.01 ), Millimeter2iu( 5.0 ),
|
|
|
|
nullptr, MM_PER_IU, wxT( "ModuleOutlineThickness" ) ) );
|
|
|
|
|
|
|
|
aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "SilkTextSizeV" ),
|
|
|
|
&m_TextSize[ LAYER_CLASS_SILK ].y,
|
|
|
|
Millimeter2iu( DEFAULT_SILK_TEXT_SIZE ), TEXTS_MIN_SIZE, TEXTS_MAX_SIZE,
|
|
|
|
nullptr, MM_PER_IU, wxT( "ModuleTextSizeV" ) ) );
|
|
|
|
|
|
|
|
aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "SilkTextSizeH" ),
|
|
|
|
&m_TextSize[ LAYER_CLASS_SILK ].x,
|
|
|
|
Millimeter2iu( DEFAULT_SILK_TEXT_SIZE ), TEXTS_MIN_SIZE, TEXTS_MAX_SIZE,
|
|
|
|
nullptr, MM_PER_IU, wxT( "ModuleTextSizeH" ) ) );
|
|
|
|
|
|
|
|
aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "SilkTextSizeThickness" ),
|
|
|
|
&m_TextThickness[ LAYER_CLASS_SILK ],
|
|
|
|
Millimeter2iu( DEFAULT_SILK_TEXT_WIDTH ), 1, TEXTS_MAX_WIDTH,
|
|
|
|
nullptr, MM_PER_IU, wxT( "ModuleTextSizeThickness" ) ) );
|
|
|
|
|
|
|
|
aResult->push_back( new PARAM_CFG_BOOL( wxT( "SilkTextItalic" ),
|
|
|
|
&m_TextItalic[ LAYER_CLASS_SILK ], false ) );
|
|
|
|
|
|
|
|
aResult->push_back( new PARAM_CFG_BOOL( wxT( "SilkTextUpright" ),
|
|
|
|
&m_TextUpright[ LAYER_CLASS_SILK ], true ) );
|
|
|
|
|
|
|
|
aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "CopperLineWidth" ),
|
|
|
|
&m_LineThickness[ LAYER_CLASS_COPPER ],
|
|
|
|
Millimeter2iu( DEFAULT_SILK_LINE_WIDTH ), Millimeter2iu( 0.01 ), Millimeter2iu( 5.0 ),
|
|
|
|
nullptr, MM_PER_IU, wxT( "DrawSegmentWidth" ) ) );
|
|
|
|
|
|
|
|
aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "CopperTextSizeV" ),
|
|
|
|
&m_TextSize[ LAYER_CLASS_COPPER ].y,
|
|
|
|
Millimeter2iu( DEFAULT_COPPER_TEXT_SIZE ), TEXTS_MIN_SIZE, TEXTS_MAX_SIZE,
|
|
|
|
nullptr, MM_PER_IU, wxT( "PcbTextSizeV" ) ) );
|
|
|
|
|
|
|
|
aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "CopperTextSizeH" ),
|
|
|
|
&m_TextSize[ LAYER_CLASS_COPPER ].x,
|
|
|
|
Millimeter2iu( DEFAULT_COPPER_TEXT_SIZE ), TEXTS_MIN_SIZE, TEXTS_MAX_SIZE,
|
|
|
|
nullptr, MM_PER_IU, wxT( "PcbTextSizeH" ) ) );
|
|
|
|
|
|
|
|
aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "CopperTextThickness" ),
|
|
|
|
&m_TextThickness[ LAYER_CLASS_COPPER ],
|
|
|
|
Millimeter2iu( DEFAULT_COPPER_TEXT_WIDTH ), Millimeter2iu( 0.01 ), Millimeter2iu( 5.0 ),
|
|
|
|
nullptr, MM_PER_IU, wxT( "PcbTextThickness" ) ) );
|
|
|
|
|
|
|
|
aResult->push_back( new PARAM_CFG_BOOL( wxT( "CopperTextItalic" ),
|
|
|
|
&m_TextItalic[ LAYER_CLASS_COPPER ], false ) );
|
|
|
|
|
|
|
|
aResult->push_back( new PARAM_CFG_BOOL( wxT( "CopperTextUpright" ),
|
|
|
|
&m_TextUpright[ LAYER_CLASS_COPPER ], true ) );
|
|
|
|
|
2018-08-24 20:08:30 +00:00
|
|
|
aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "EdgeCutLineWidth" ),
|
2018-04-28 15:22:25 +00:00
|
|
|
&m_LineThickness[ LAYER_CLASS_EDGES ],
|
|
|
|
Millimeter2iu( DEFAULT_SILK_LINE_WIDTH ), Millimeter2iu( 0.01 ), Millimeter2iu( 5.0 ),
|
|
|
|
nullptr, MM_PER_IU, wxT( "BoardOutlineThickness" ) ) );
|
|
|
|
|
2018-08-24 20:08:30 +00:00
|
|
|
aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "CourtyardLineWidth" ),
|
|
|
|
&m_LineThickness[ LAYER_CLASS_COURTYARD ],
|
|
|
|
Millimeter2iu( DEFAULT_SILK_LINE_WIDTH ), Millimeter2iu( 0.01 ), Millimeter2iu( 5.0 ),
|
|
|
|
nullptr, MM_PER_IU ) );
|
|
|
|
|
2018-04-28 15:22:25 +00:00
|
|
|
aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "OthersLineWidth" ),
|
|
|
|
&m_LineThickness[ LAYER_CLASS_OTHERS ],
|
|
|
|
Millimeter2iu( DEFAULT_SILK_LINE_WIDTH ), Millimeter2iu( 0.01 ), Millimeter2iu( 5.0 ),
|
|
|
|
nullptr, MM_PER_IU, wxT( "ModuleOutlineThickness" ) ) );
|
|
|
|
|
|
|
|
aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "OthersTextSizeV" ),
|
|
|
|
&m_TextSize[ LAYER_CLASS_OTHERS ].x,
|
|
|
|
Millimeter2iu( DEFAULT_TEXT_SIZE ), TEXTS_MIN_SIZE, TEXTS_MAX_SIZE,
|
|
|
|
nullptr, MM_PER_IU ) );
|
|
|
|
|
|
|
|
aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "OthersTextSizeH" ),
|
|
|
|
&m_TextSize[ LAYER_CLASS_OTHERS ].y,
|
|
|
|
Millimeter2iu( DEFAULT_TEXT_SIZE ), TEXTS_MIN_SIZE, TEXTS_MAX_SIZE,
|
|
|
|
nullptr, MM_PER_IU ) );
|
|
|
|
|
|
|
|
aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "OthersTextSizeThickness" ),
|
|
|
|
&m_TextThickness[ LAYER_CLASS_OTHERS ],
|
|
|
|
Millimeter2iu( DEFAULT_TEXT_WIDTH ), 1, TEXTS_MAX_WIDTH,
|
|
|
|
nullptr, MM_PER_IU ) );
|
|
|
|
|
|
|
|
aResult->push_back( new PARAM_CFG_BOOL( wxT( "OthersTextItalic" ),
|
|
|
|
&m_TextItalic[ LAYER_CLASS_OTHERS ], false ) );
|
|
|
|
|
|
|
|
aResult->push_back( new PARAM_CFG_BOOL( wxT( "OthersTextUpright" ),
|
|
|
|
&m_TextUpright[ LAYER_CLASS_OTHERS ], true ) );
|
2012-10-17 10:57:21 +00:00
|
|
|
|
|
|
|
aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "SolderMaskClearance" ),
|
2018-04-28 15:22:25 +00:00
|
|
|
&m_SolderMaskMargin,
|
|
|
|
Millimeter2iu( DEFAULT_SOLDERMASK_CLEARANCE ), Millimeter2iu( -1.0 ), Millimeter2iu( 1.0 ),
|
|
|
|
nullptr, MM_PER_IU ) );
|
2012-10-17 10:57:21 +00:00
|
|
|
|
2012-11-05 20:20:34 +00:00
|
|
|
aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "SolderMaskMinWidth" ),
|
2018-04-28 15:22:25 +00:00
|
|
|
&m_SolderMaskMinWidth,
|
|
|
|
Millimeter2iu( DEFAULT_SOLDERMASK_MIN_WIDTH ), 0, Millimeter2iu( 1.0 ),
|
|
|
|
nullptr, MM_PER_IU ) );
|
|
|
|
|
|
|
|
aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "SolderPasteClearance" ),
|
|
|
|
&m_SolderPasteMargin,
|
|
|
|
Millimeter2iu( DEFAULT_SOLDERPASTE_CLEARANCE ), Millimeter2iu( -1.0 ), Millimeter2iu( 1.0 ),
|
|
|
|
nullptr, MM_PER_IU ) );
|
|
|
|
|
|
|
|
aResult->push_back( new PARAM_CFG_DOUBLE( wxT( "SolderPasteRatio" ),
|
|
|
|
&m_SolderPasteMarginRatio,
|
2019-03-07 04:55:14 +00:00
|
|
|
DEFAULT_SOLDERPASTE_RATIO, -0.5, 1.0 ) );
|
2012-02-19 04:02:19 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2014-05-13 09:22:51 +00:00
|
|
|
bool BOARD_DESIGN_SETTINGS::SetCurrentNetClass( const wxString& aNetClassName )
|
|
|
|
{
|
2014-05-20 09:29:37 +00:00
|
|
|
NETCLASSPTR netClass = m_NetClasses.Find( aNetClassName );
|
|
|
|
bool lists_sizes_modified = false;
|
2014-05-13 09:22:51 +00:00
|
|
|
|
|
|
|
// if not found (should not happen) use the default
|
2018-04-28 15:22:25 +00:00
|
|
|
if( !netClass )
|
2014-05-13 09:22:51 +00:00
|
|
|
netClass = m_NetClasses.GetDefault();
|
|
|
|
|
|
|
|
m_currentNetClassName = netClass->GetName();
|
|
|
|
|
|
|
|
// Initialize others values:
|
2018-04-28 15:22:25 +00:00
|
|
|
if( m_TrackWidthList.size() == 0 )
|
|
|
|
{
|
|
|
|
lists_sizes_modified = true;
|
|
|
|
m_TrackWidthList.push_back( 0 );
|
|
|
|
}
|
|
|
|
|
2014-05-13 09:22:51 +00:00
|
|
|
if( m_ViasDimensionsList.size() == 0 )
|
|
|
|
{
|
|
|
|
lists_sizes_modified = true;
|
2018-04-28 15:22:25 +00:00
|
|
|
m_ViasDimensionsList.emplace_back( VIA_DIMENSION() );
|
2014-05-13 09:22:51 +00:00
|
|
|
}
|
|
|
|
|
2018-04-28 15:22:25 +00:00
|
|
|
if( m_DiffPairDimensionsList.size() == 0 )
|
2014-05-13 09:22:51 +00:00
|
|
|
{
|
|
|
|
lists_sizes_modified = true;
|
2018-04-28 15:22:25 +00:00
|
|
|
m_DiffPairDimensionsList.emplace_back( DIFF_PAIR_DIMENSION() );
|
2014-05-13 09:22:51 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* note the m_ViasDimensionsList[0] and m_TrackWidthList[0] values
|
|
|
|
* are always the Netclass values
|
|
|
|
*/
|
2018-04-28 15:22:25 +00:00
|
|
|
if( m_TrackWidthList[0] != netClass->GetTrackWidth() )
|
|
|
|
{
|
|
|
|
lists_sizes_modified = true;
|
|
|
|
m_TrackWidthList[0] = netClass->GetTrackWidth();
|
|
|
|
}
|
|
|
|
|
2014-05-13 09:22:51 +00:00
|
|
|
if( m_ViasDimensionsList[0].m_Diameter != netClass->GetViaDiameter() )
|
2015-06-15 15:54:58 +00:00
|
|
|
{
|
2014-05-13 09:22:51 +00:00
|
|
|
lists_sizes_modified = true;
|
2015-06-15 15:54:58 +00:00
|
|
|
m_ViasDimensionsList[0].m_Diameter = netClass->GetViaDiameter();
|
|
|
|
}
|
2014-05-13 09:22:51 +00:00
|
|
|
|
2015-06-15 15:54:58 +00:00
|
|
|
if( m_ViasDimensionsList[0].m_Drill != netClass->GetViaDrill() )
|
|
|
|
{
|
|
|
|
lists_sizes_modified = true;
|
|
|
|
m_ViasDimensionsList[0].m_Drill = netClass->GetViaDrill();
|
|
|
|
}
|
2014-05-13 09:22:51 +00:00
|
|
|
|
2018-04-28 15:22:25 +00:00
|
|
|
if( m_DiffPairDimensionsList[0].m_Width != netClass->GetDiffPairWidth() )
|
2015-06-15 15:54:58 +00:00
|
|
|
{
|
2014-05-13 09:22:51 +00:00
|
|
|
lists_sizes_modified = true;
|
2018-04-28 15:22:25 +00:00
|
|
|
m_DiffPairDimensionsList[0].m_Width = netClass->GetDiffPairWidth();
|
|
|
|
}
|
|
|
|
|
|
|
|
if( m_DiffPairDimensionsList[0].m_Gap != netClass->GetDiffPairGap() )
|
|
|
|
{
|
|
|
|
lists_sizes_modified = true;
|
|
|
|
m_DiffPairDimensionsList[0].m_Gap = netClass->GetDiffPairGap();
|
|
|
|
}
|
|
|
|
|
|
|
|
if( m_DiffPairDimensionsList[0].m_ViaGap != netClass->GetDiffPairViaGap() )
|
|
|
|
{
|
|
|
|
lists_sizes_modified = true;
|
|
|
|
m_DiffPairDimensionsList[0].m_ViaGap = netClass->GetDiffPairViaGap();
|
2015-06-15 15:54:58 +00:00
|
|
|
}
|
2014-05-13 09:22:51 +00:00
|
|
|
|
|
|
|
if( GetViaSizeIndex() >= m_ViasDimensionsList.size() )
|
|
|
|
SetViaSizeIndex( m_ViasDimensionsList.size() );
|
|
|
|
|
|
|
|
if( GetTrackWidthIndex() >= m_TrackWidthList.size() )
|
|
|
|
SetTrackWidthIndex( m_TrackWidthList.size() );
|
|
|
|
|
2018-04-28 15:22:25 +00:00
|
|
|
if( GetDiffPairIndex() >= m_DiffPairDimensionsList.size() )
|
|
|
|
SetDiffPairIndex( m_DiffPairDimensionsList.size() );
|
|
|
|
|
2014-05-13 09:22:51 +00:00
|
|
|
return lists_sizes_modified;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
int BOARD_DESIGN_SETTINGS::GetBiggestClearanceValue()
|
|
|
|
{
|
|
|
|
int clearance = m_NetClasses.GetDefault()->GetClearance();
|
|
|
|
|
|
|
|
//Read list of Net Classes
|
2015-02-22 09:39:58 +00:00
|
|
|
for( NETCLASSES::const_iterator nc = m_NetClasses.begin(); nc != m_NetClasses.end(); ++nc )
|
2014-05-13 09:22:51 +00:00
|
|
|
{
|
2014-05-20 09:29:37 +00:00
|
|
|
NETCLASSPTR netclass = nc->second;
|
2014-05-13 09:22:51 +00:00
|
|
|
clearance = std::max( clearance, netclass->GetClearance() );
|
|
|
|
}
|
|
|
|
|
|
|
|
return clearance;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
int BOARD_DESIGN_SETTINGS::GetSmallestClearanceValue()
|
|
|
|
{
|
|
|
|
int clearance = m_NetClasses.GetDefault()->GetClearance();
|
|
|
|
|
|
|
|
//Read list of Net Classes
|
2015-02-22 09:39:58 +00:00
|
|
|
for( NETCLASSES::const_iterator nc = m_NetClasses.begin(); nc != m_NetClasses.end(); ++nc )
|
2014-05-13 09:22:51 +00:00
|
|
|
{
|
2014-05-20 09:29:37 +00:00
|
|
|
NETCLASSPTR netclass = nc->second;
|
2014-05-13 09:22:51 +00:00
|
|
|
clearance = std::min( clearance, netclass->GetClearance() );
|
|
|
|
}
|
|
|
|
|
|
|
|
return clearance;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
int BOARD_DESIGN_SETTINGS::GetCurrentMicroViaSize()
|
|
|
|
{
|
2014-05-20 09:29:37 +00:00
|
|
|
NETCLASSPTR netclass = m_NetClasses.Find( m_currentNetClassName );
|
2014-05-13 09:22:51 +00:00
|
|
|
|
|
|
|
return netclass->GetuViaDiameter();
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
int BOARD_DESIGN_SETTINGS::GetCurrentMicroViaDrill()
|
|
|
|
{
|
2014-05-20 09:29:37 +00:00
|
|
|
NETCLASSPTR netclass = m_NetClasses.Find( m_currentNetClassName );
|
2014-05-13 09:22:51 +00:00
|
|
|
|
|
|
|
return netclass->GetuViaDrill();
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2014-05-13 09:22:51 +00:00
|
|
|
void BOARD_DESIGN_SETTINGS::SetViaSizeIndex( unsigned aIndex )
|
|
|
|
{
|
2018-04-28 15:22:25 +00:00
|
|
|
m_viaSizeIndex = std::min( aIndex, (unsigned) m_ViasDimensionsList.size() );
|
2014-06-03 14:09:27 +00:00
|
|
|
m_useCustomTrackVia = false;
|
2014-05-13 09:22:51 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
int BOARD_DESIGN_SETTINGS::GetCurrentViaDrill() const
|
|
|
|
{
|
|
|
|
int drill;
|
|
|
|
|
|
|
|
if( m_useCustomTrackVia )
|
|
|
|
drill = m_customViaSize.m_Drill;
|
|
|
|
else
|
|
|
|
drill = m_ViasDimensionsList[m_viaSizeIndex].m_Drill;
|
|
|
|
|
|
|
|
return drill > 0 ? drill : -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void BOARD_DESIGN_SETTINGS::SetTrackWidthIndex( unsigned aIndex )
|
|
|
|
{
|
2018-04-28 15:22:25 +00:00
|
|
|
m_trackWidthIndex = std::min( aIndex, (unsigned) m_TrackWidthList.size() );
|
2014-06-03 14:09:27 +00:00
|
|
|
m_useCustomTrackVia = false;
|
2014-05-13 09:22:51 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2018-04-28 15:22:25 +00:00
|
|
|
void BOARD_DESIGN_SETTINGS::SetDiffPairIndex( unsigned aIndex )
|
2018-04-14 14:58:01 +00:00
|
|
|
{
|
2018-04-28 15:22:25 +00:00
|
|
|
m_diffPairIndex = std::min( aIndex, (unsigned) 8 );
|
|
|
|
m_useCustomDiffPair = false;
|
2018-04-14 14:58:01 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void BOARD_DESIGN_SETTINGS::SetMinHoleSeparation( int aDistance )
|
|
|
|
{
|
2018-04-28 15:22:25 +00:00
|
|
|
m_HoleToHoleMin = aDistance;
|
2018-04-14 14:58:01 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2019-04-05 16:10:59 +00:00
|
|
|
void BOARD_DESIGN_SETTINGS::SetCopperEdgeClearance( int aDistance )
|
|
|
|
{
|
|
|
|
m_CopperEdgeClearance = aDistance;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2018-04-14 14:58:01 +00:00
|
|
|
void BOARD_DESIGN_SETTINGS::SetRequireCourtyardDefinitions( bool aRequire )
|
|
|
|
{
|
2018-04-28 15:22:25 +00:00
|
|
|
m_RequireCourtyards = aRequire;
|
2018-04-14 14:58:01 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2018-04-28 15:22:25 +00:00
|
|
|
void BOARD_DESIGN_SETTINGS::SetProhibitOverlappingCourtyards( bool aProhibit )
|
2018-04-14 14:58:01 +00:00
|
|
|
{
|
2018-04-28 15:22:25 +00:00
|
|
|
m_ProhibitOverlappingCourtyards = aProhibit;
|
2018-04-14 14:58:01 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2011-09-23 13:57:12 +00:00
|
|
|
void BOARD_DESIGN_SETTINGS::SetVisibleAlls()
|
2010-01-27 20:07:50 +00:00
|
|
|
{
|
2014-06-24 16:17:18 +00:00
|
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|
SetVisibleLayers( LSET().set() );
|
2014-05-13 09:22:51 +00:00
|
|
|
m_visibleElements = -1;
|
2009-10-28 11:48:47 +00:00
|
|
|
}
|
|
|
|
|
2009-11-04 19:08:08 +00:00
|
|
|
|
2017-03-13 03:19:33 +00:00
|
|
|
void BOARD_DESIGN_SETTINGS::SetLayerVisibility( PCB_LAYER_ID aLayer, bool aNewState )
|
2009-10-28 11:48:47 +00:00
|
|
|
{
|
2018-04-28 15:22:25 +00:00
|
|
|
m_visibleLayers.set( aLayer, aNewState && IsLayerEnabled( aLayer ));
|
2009-10-28 11:48:47 +00:00
|
|
|
}
|
|
|
|
|
2009-11-04 19:08:08 +00:00
|
|
|
|
2017-03-13 03:19:33 +00:00
|
|
|
void BOARD_DESIGN_SETTINGS::SetElementVisibility( GAL_LAYER_ID aElementCategory, bool aNewState )
|
2009-10-28 11:48:47 +00:00
|
|
|
{
|
|
|
|
if( aNewState )
|
2017-03-13 03:19:33 +00:00
|
|
|
m_visibleElements |= 1 << GAL_LAYER_INDEX( aElementCategory );
|
2009-10-28 11:48:47 +00:00
|
|
|
else
|
2017-03-13 03:19:33 +00:00
|
|
|
m_visibleElements &= ~( 1 << GAL_LAYER_INDEX( aElementCategory ) );
|
2009-10-28 11:48:47 +00:00
|
|
|
}
|
2009-11-04 19:08:08 +00:00
|
|
|
|
|
|
|
|
2010-01-31 20:01:46 +00:00
|
|
|
void BOARD_DESIGN_SETTINGS::SetCopperLayerCount( int aNewLayerCount )
|
2009-10-28 11:48:47 +00:00
|
|
|
{
|
2010-01-21 07:41:30 +00:00
|
|
|
// if( aNewLayerCount < 2 ) aNewLayerCount = 2;
|
|
|
|
|
2014-05-13 09:22:51 +00:00
|
|
|
m_copperLayerCount = aNewLayerCount;
|
2009-11-04 19:08:08 +00:00
|
|
|
|
2009-10-28 11:48:47 +00:00
|
|
|
// ensure consistency with the m_EnabledLayers member
|
2014-06-24 16:17:18 +00:00
|
|
|
#if 0
|
|
|
|
// was:
|
2014-05-13 09:22:51 +00:00
|
|
|
m_enabledLayers &= ~ALL_CU_LAYERS;
|
|
|
|
m_enabledLayers |= LAYER_BACK;
|
2009-12-07 03:46:13 +00:00
|
|
|
|
2014-05-13 09:22:51 +00:00
|
|
|
if( m_copperLayerCount > 1 )
|
|
|
|
m_enabledLayers |= LAYER_FRONT;
|
2009-12-07 03:46:13 +00:00
|
|
|
|
2013-03-31 13:27:46 +00:00
|
|
|
for( LAYER_NUM ii = LAYER_N_2; ii < aNewLayerCount - 1; ++ii )
|
2014-06-24 16:17:18 +00:00
|
|
|
m_enabledLayers |= GetLayerSet( ii );
|
|
|
|
#else
|
2014-06-30 15:46:47 +00:00
|
|
|
// Update only enabled copper layers mask
|
|
|
|
m_enabledLayers &= ~LSET::AllCuMask();
|
|
|
|
m_enabledLayers |= LSET::AllCuMask( aNewLayerCount );
|
2014-06-24 16:17:18 +00:00
|
|
|
#endif
|
2009-10-28 11:48:47 +00:00
|
|
|
}
|
2009-12-07 03:46:13 +00:00
|
|
|
|
2011-09-23 13:57:12 +00:00
|
|
|
|
2014-06-24 16:17:18 +00:00
|
|
|
void BOARD_DESIGN_SETTINGS::SetEnabledLayers( LSET aMask )
|
2009-12-21 12:05:36 +00:00
|
|
|
{
|
2010-01-21 07:41:30 +00:00
|
|
|
// Back and front layers are always enabled.
|
2014-06-24 16:17:18 +00:00
|
|
|
aMask.set( B_Cu ).set( F_Cu );
|
2010-01-21 07:41:30 +00:00
|
|
|
|
2014-05-13 09:22:51 +00:00
|
|
|
m_enabledLayers = aMask;
|
2009-12-21 12:05:36 +00:00
|
|
|
|
2010-01-21 07:41:30 +00:00
|
|
|
// A disabled layer cannot be visible
|
2014-05-13 09:22:51 +00:00
|
|
|
m_visibleLayers &= aMask;
|
2009-12-21 12:05:36 +00:00
|
|
|
|
2010-01-21 07:41:30 +00:00
|
|
|
// update m_CopperLayerCount to ensure its consistency with m_EnabledLayers
|
2014-06-24 16:17:18 +00:00
|
|
|
m_copperLayerCount = ( aMask & LSET::AllCuMask() ).count();
|
2009-12-21 12:05:36 +00:00
|
|
|
}
|
2014-02-07 19:54:58 +00:00
|
|
|
|
|
|
|
|
2018-04-28 15:22:25 +00:00
|
|
|
// Return the layer class index { silk, copper, edges & courtyards, others } of the
|
|
|
|
// given layer.
|
|
|
|
int BOARD_DESIGN_SETTINGS::GetLayerClass( PCB_LAYER_ID aLayer ) const
|
|
|
|
{
|
|
|
|
if( aLayer == F_SilkS || aLayer == B_SilkS )
|
2018-10-07 15:31:16 +00:00
|
|
|
return LAYER_CLASS_SILK;
|
2018-04-28 15:22:25 +00:00
|
|
|
else if( IsCopperLayer( aLayer ) )
|
2018-10-07 15:31:16 +00:00
|
|
|
return LAYER_CLASS_COPPER;
|
|
|
|
else if( aLayer == Edge_Cuts )
|
|
|
|
return LAYER_CLASS_EDGES;
|
|
|
|
else if( aLayer == F_CrtYd || aLayer == B_CrtYd )
|
|
|
|
return LAYER_CLASS_COURTYARD;
|
2018-04-28 15:22:25 +00:00
|
|
|
else
|
2018-10-07 15:31:16 +00:00
|
|
|
return LAYER_CLASS_OTHERS;
|
2018-04-28 15:22:25 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
int BOARD_DESIGN_SETTINGS::GetLineThickness( PCB_LAYER_ID aLayer ) const
|
|
|
|
{
|
|
|
|
return m_LineThickness[ GetLayerClass( aLayer ) ];
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
wxSize BOARD_DESIGN_SETTINGS::GetTextSize( PCB_LAYER_ID aLayer ) const
|
|
|
|
{
|
|
|
|
return m_TextSize[ GetLayerClass( aLayer ) ];
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
int BOARD_DESIGN_SETTINGS::GetTextThickness( PCB_LAYER_ID aLayer ) const
|
|
|
|
{
|
|
|
|
return m_TextThickness[ GetLayerClass( aLayer ) ];
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
bool BOARD_DESIGN_SETTINGS::GetTextItalic( PCB_LAYER_ID aLayer ) const
|
|
|
|
{
|
|
|
|
return m_TextItalic[ GetLayerClass( aLayer ) ];
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
bool BOARD_DESIGN_SETTINGS::GetTextUpright( PCB_LAYER_ID aLayer ) const
|
|
|
|
{
|
|
|
|
return m_TextUpright[ GetLayerClass( aLayer ) ];
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2014-02-07 19:54:58 +00:00
|
|
|
#ifndef NDEBUG
|
2014-03-06 09:43:40 +00:00
|
|
|
struct list_size_check {
|
|
|
|
list_size_check()
|
2014-02-07 19:54:58 +00:00
|
|
|
{
|
|
|
|
// Int (the type used for saving visibility settings) is only 32 bits guaranteed,
|
|
|
|
// be sure that we do not cross the limit
|
2017-03-13 03:19:33 +00:00
|
|
|
assert( GAL_LAYER_INDEX( GAL_LAYER_ID_BITMASK_END ) <= 32 );
|
2014-02-07 19:54:58 +00:00
|
|
|
};
|
|
|
|
};
|
2014-03-06 09:43:40 +00:00
|
|
|
static list_size_check check;
|
2014-02-07 19:54:58 +00:00
|
|
|
#endif
|
2018-04-28 15:22:25 +00:00
|
|
|
|
|
|
|
|