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kicad/demos/interf_u/interf_u.pro

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Demos update
2020-01-01 10:19:36 +00:00
update=02/01/2020 08:47:28
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
version=1
Minor fixes: specctra export: skip malformed circles (having a radius = 0) in board outline creation, which can crash 3d-viewer or vrml export. dialog_fp_lib_table: remember during a session the last open table (global or local). drawing_tool: fix compil warning Update demos.
2014-09-22 07:51:06 +00:00
last_client=kicad
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
[common]
NetDir=
[general]
version=1
RootSch=interf_u.sch
BoardNm=interf_u.brd
[cvpcb]
version=1
NetIExt=net
[cvpcb/libraries]
EquName1=devcms
Demos update
2020-01-01 10:19:36 +00:00
[eeschema]
version=1
LibDir=
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
[pcbnew]
version=1
Eeschema: fix Bug #1210120
2013-08-09 06:51:14 +00:00
PageLayoutDescrFile=pagelayout_logo.kicad_wks
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
LastNetListRead=interf_u.net
Demos update
2020-01-01 10:19:36 +00:00
LastSTEPExportPath=
LastIDFExportPath=
LastVRMLExportPath=
LastSpecctraDSNExportPath=
LastGenCADExportPath=
CopperLayerCount=2
BoardThickness=1.6002
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.2
MinViaDiameter=0.8999999999999999
MinViaDrill=0.5
MinMicroViaDiameter=0.5
MinMicroViaDrill=0.127
MinHoleToHole=0.25
CopperEdgeClearance=0.01
TrackWidth1=0.4
TrackWidth2=0.381
TrackWidth3=0.762
ViaDiameter1=1.4
ViaDrill1=0.6
ViaDiameter2=1.524
ViaDrill2=0.762
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.381
SilkTextSizeV=1.524
SilkTextSizeH=1.524
SilkTextSizeThickness=0.3048
SilkTextItalic=0
SilkTextUpright=0
CopperLineWidth=0.381
CopperTextSizeV=2.032
CopperTextSizeH=1.524
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=0
EdgeCutLineWidth=0.127
CourtyardLineWidth=0.05
OthersLineWidth=0.09999999999999999
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=0
DimensionUnits=0
DimensionPrecision=1
Eeschema: fix Bug #1210120
2013-08-09 06:51:14 +00:00
SolderMaskClearance=0.254
Demos update
2020-01-01 10:19:36 +00:00
SolderMaskMinWidth=0.5
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=top_copper
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=0
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=0
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=bottom_copper
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.254
TrackWidth=0.4
ViaDiameter=1.4
ViaDrill=0.6
uViaDiameter=0.5
uViaDrill=0.127
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/1]
Name=Power
Clearance=0.254
TrackWidth=0.5
ViaDiameter=1.6
ViaDrill=0.6
uViaDiameter=0.5
uViaDrill=0.127
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25