2020-06-13 23:28:08 +00:00
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/*
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* This program source code file is part of KiCad, a free EDA CAD application.
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*
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* Copyright (C) 2020 KiCad Developers, see change_log.txt for contributors.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you may find one here:
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* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
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* or you may search the http://www.gnu.org website for the version 2 license,
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* or you may write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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#ifndef DRC_RULE_PROTO_H
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#define DRC_RULE_PROTO_H
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#include <core/typeinfo.h>
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#include <layers_id_colors_and_visibility.h>
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#include <netclass.h>
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#include <libeval_compiler/libeval_compiler.h>
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class BOARD_ITEM;
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namespace LIBEVAL
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{
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class UCODE;
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class ERROR_STATUS;
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2020-06-13 23:28:08 +00:00
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};
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2020-06-17 22:36:54 +00:00
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class PCB_EXPR_UCODE;
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2020-06-13 23:28:08 +00:00
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namespace test
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{
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2020-08-11 22:17:43 +00:00
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class DRC_RULE;
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class DRC_RULE_CONDITION;
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enum DRC_CONSTRAINT_TYPE_T
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{
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DRC_CONSTRAINT_TYPE_UNKNOWN = -1,
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DRC_CONSTRAINT_TYPE_CLEARANCE = 0,
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DRC_CONSTRAINT_TYPE_HOLE_CLEARANCE,
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DRC_CONSTRAINT_TYPE_EDGE_CLEARANCE,
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DRC_CONSTRAINT_TYPE_HOLE_SIZE,
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DRC_CONSTRAINT_TYPE_COURTYARD_CLEARANCE,
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DRC_CONSTRAINT_TYPE_SILK_TO_PAD,
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DRC_CONSTRAINT_TYPE_SILK_TO_SILK,
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DRC_CONSTRAINT_TYPE_TRACK_WIDTH,
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DRC_CONSTRAINT_TYPE_ANNULUS_WIDTH,
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DRC_CONSTRAINT_TYPE_DISALLOW,
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DRC_CONSTRAINT_TYPE_VIA_DIAMETER
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};
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enum DRC_DISALLOW_T
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{
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DRC_DISALLOW_VIAS = (1 << 0),
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DRC_DISALLOW_MICRO_VIAS = (1 << 1),
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DRC_DISALLOW_BB_VIAS = (1 << 2),
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DRC_DISALLOW_TRACKS = (1 << 3),
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DRC_DISALLOW_PADS = (1 << 4),
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DRC_DISALLOW_ZONES = (1 << 5),
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DRC_DISALLOW_TEXTS = (1 << 6),
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DRC_DISALLOW_GRAPHICS = (1 << 7),
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DRC_DISALLOW_HOLES = (1 << 8),
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DRC_DISALLOW_FOOTPRINTS = (1 << 9)
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};
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enum DRC_RULE_SEVERITY_T
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{
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DRC_SEVERITY_IGNORE = 0,
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DRC_SEVERITY_WARNING,
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DRC_SEVERITY_ERROR
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};
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template<class T=int>
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class MINOPTMAX
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{
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public:
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T Min() const { assert( m_hasMin ); return m_min; };
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T Max() const { assert( m_hasMax ); return m_max; };
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T Opt() const { assert( m_hasOpt ); return m_opt; };
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2020-06-30 08:44:12 +00:00
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bool HasMin() const { return m_hasMin; }
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bool HasMax() const { return m_hasMax; }
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bool HasOpt() const { return m_hasOpt; }
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void SetMin( T v ) { m_min = v; m_hasMin = true; }
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void SetMax( T v ) { m_max = v; m_hasMax = true; }
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void SetOpt( T v ) { m_opt = v; m_hasOpt = true; }
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private:
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T m_min;
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T m_opt;
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T m_max;
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bool m_hasMin = false;
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bool m_hasOpt = false;
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bool m_hasMax = false;
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};
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class DRC_CONSTRAINT
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{
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public:
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DRC_CONSTRAINT( DRC_CONSTRAINT_TYPE_T aType = DRC_CONSTRAINT_TYPE_T::DRC_CONSTRAINT_TYPE_UNKNOWN
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) :
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m_Type( aType ),
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m_DisallowFlags( 0 ),
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m_LayerCondition( LSET::AllLayersMask() ),
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m_parentRule( nullptr ) // fixme
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{
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}
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const MINOPTMAX<int>& GetValue() const { return m_Value; }
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MINOPTMAX<int>& Value() { return m_Value; }
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// fixme: needed?
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bool Allowed() const { return m_Allow; }
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void SetParentRule( DRC_RULE *aParentRule ) { m_parentRule = aParentRule; }
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DRC_RULE* GetParentRule() const { return m_parentRule; }
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DRC_CONSTRAINT_TYPE_T GetType() const { return m_Type; }
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const LSET& GetAllowedLayers() const { return m_LayerCondition; }
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public:
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DRC_CONSTRAINT_TYPE_T m_Type;
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int m_DisallowFlags;
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LSET m_LayerCondition;
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private:
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DRC_RULE *m_parentRule;
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MINOPTMAX<int> m_Value;
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bool m_Allow;
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};
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class DRC_RULE
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{
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public:
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DRC_RULE();
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virtual ~DRC_RULE();
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virtual bool IsImplicit() const { return false; };
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virtual bool AppliesTo( const BOARD_ITEM* a, const BOARD_ITEM* b = nullptr ) const { return true; };
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virtual bool IsEnabled() const { return m_Enabled; }
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virtual bool HasSpecificItemSet() const { return false; };
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virtual void FillSpecificItemSet( std::set<BOARD_ITEM*> specificItems ) { };
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void SetPriority( int aPriority ) { m_priority = aPriority; }
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int GetPriority() const { return m_priority; }
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DRC_RULE_SEVERITY_T GetSeverity() const { return m_Severity; }
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void SetName( const wxString& aName ) { m_name = aName; }
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const wxString GetName() const { return m_name; }
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std::vector<DRC_CONSTRAINT>& Constraints()
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{
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return m_constraints;
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}
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void AddConstraint( DRC_CONSTRAINT& aConstraint );
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bool IsConditional() const
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{
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return m_condition != nullptr;
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}
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void SetCondition( test::DRC_RULE_CONDITION* aCondition )
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{
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m_condition = aCondition;
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}
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test::DRC_RULE_CONDITION* Condition()
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{
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return m_condition;
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}
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void SetLayerCondition( LSET aLayerCondition )
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{
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m_layerCondition = aLayerCondition;
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}
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private:
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wxString m_name;
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int m_priority; // 0 indicates automatic priority generation fixme: use enum
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public:
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bool m_Unary;
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LSET m_layerCondition;
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DRC_RULE_CONDITION* m_condition; // fixme: consider unique_ptr
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std::vector<DRC_CONSTRAINT> m_constraints;
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DRC_RULE_SEVERITY_T m_Severity;
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bool m_Enabled;
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2020-08-11 22:15:50 +00:00
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};
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class DRC_RULE_CONDITION
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{
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public:
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DRC_RULE_CONDITION( const wxString& aExpression = "",
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const LSET aLayerCondition = LSET::AllLayersMask() );
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~DRC_RULE_CONDITION();
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2020-08-11 22:17:43 +00:00
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bool EvaluateFor( const BOARD_ITEM* aItemA, const BOARD_ITEM* aItemB,
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PCB_LAYER_ID aLayer );
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bool Compile( REPORTER* aReporter, int aSourceLine = 0, int aSourceOffset = 0 );
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void SetLayerCondition( LSET aLayerCondition )
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{
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m_layerCondition = aLayerCondition;
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}
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void SetExpression( const wxString& aExpression )
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{
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m_expression = aExpression;
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}
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const wxString& GetExpression() const
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{
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return m_expression;
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}
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private:
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LSET m_layerCondition;
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wxString m_expression;
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std::unique_ptr<PCB_EXPR_UCODE> m_ucode;
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};
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2020-08-11 22:15:50 +00:00
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//DRC_RULE* GetRule( const BOARD_ITEM* aItem, const BOARD_ITEM* bItem, int aConstraint );
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}; // namespace test
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#endif // DRC_RULE_H
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