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Pcbnew: First draft to use a new netlist format ( containing the same info as the intermediate netlist, but using S expressions) * Eeschema can generate this netlist format. * Pcbnew can use (automatic identification) the current format or the new format. * Cvpcb does not use yet the new format.
2012-01-26 09:37:36 +00:00
# EESchema Netlist Version 1.1 created 23/01/2012 08:38:24
Eeschema: fix bug 706429
2011-01-23 12:32:33 +00:00
(
Pcbnew: First draft to use a new netlist format ( containing the same info as the intermediate netlist, but using S expressions) * Eeschema can generate this netlist format. * Pcbnew can use (automatic identification) the current format or the new format. * Cvpcb does not use yet the new format.
2012-01-26 09:37:36 +00:00
( /4A087146 $noname U3 74LS541 {Lib=74LS541}
( 1 GND )
( 2 /PC-A1 )
( 3 /PC-A0 )
( 4 /PC-A2 )
( 5 /PC-A3 )
( 6 /PC-IOW )
( 7 /PC-IOR )
( 8 /PC-RST )
( 9 /PC-RST )
( 10 GND )
( 11 ? )
( 12 /RSTL )
( 13 /PC-RD )
( 14 /PC-WR )
( 15 N-000111 )
( 16 N-000110 )
( 17 N-000109 )
( 18 N-000108 )
( 19 GND )
( 20 VCC )
Eeschema: fix bug 706429
2011-01-23 12:32:33 +00:00
)
Pcbnew: First draft to use a new netlist format ( containing the same info as the intermediate netlist, but using S expressions) * Eeschema can generate this netlist format. * Pcbnew can use (automatic identification) the current format or the new format. * Cvpcb does not use yet the new format.
2012-01-26 09:37:36 +00:00
( /32568D1E pin_array_8x2 JP1 CONN_8X2 {Lib=CONN_8X2}
( 1 GND )
( 2 /REF10 )
( 3 GND )
( 4 /REF11 )
( 5 GND )
( 6 /REF7 )
( 7 GND )
( 8 /REF9 )
( 9 GND )
( 10 /REF6 )
( 11 GND )
( 12 /REF8 )
( 13 GND )
( 14 /REF4 )
( 15 GND )
( 16 /REF5 )
Eeschema: fix bug 706429
2011-01-23 12:32:33 +00:00
)
Pcbnew: First draft to use a new netlist format ( containing the same info as the intermediate netlist, but using S expressions) * Eeschema can generate this netlist format. * Pcbnew can use (automatic identification) the current format or the new format. * Cvpcb does not use yet the new format.
2012-01-26 09:37:36 +00:00
( /325679C1 r_pack9 RR1 9x1K {Lib=RR9}
( 1 VCC )
( 2 /REF5 )
( 3 /REF4 )
( 4 /REF8 )
( 5 /REF6 )
( 6 /REF9 )
( 7 /REF7 )
( 8 /REF11 )
( 9 /REF10 )
( 10 ? )
Eeschema: fix bug 706429
2011-01-23 12:32:33 +00:00
)
Pcbnew: First draft to use a new netlist format ( containing the same info as the intermediate netlist, but using S expressions) * Eeschema can generate this netlist format. * Pcbnew can use (automatic identification) the current format or the new format. * Cvpcb does not use yet the new format.
2012-01-26 09:37:36 +00:00
( /3256759C DB25FC P1 DB25FEMELLE {Lib=DB25}
( 1 /STROBE )
( 2 /BIT0 )
( 3 /BIT1 )
( 4 /BIT2 )
( 5 /BIT3 )
( 6 /BIT4 )
( 7 /BIT5 )
( 8 /BIT6 )
( 9 /BIT7 )
( 10 /ACK )
( 11 /BUST+ )
( 12 /PE+ )
( 13 /SLCT+ )
( 14 /AUTOFD- )
( 15 /ERROR- )
( 16 /INIT- )
( 17 /SLCTIN- )
( 18 GND )
( 19 GND )
( 20 GND )
( 21 GND )
( 22 GND )
( 23 GND )
( 24 GND )
( 25 GND )
Eeschema: fix bug 706429
2011-01-23 12:32:33 +00:00
)
Pcbnew: First draft to use a new netlist format ( containing the same info as the intermediate netlist, but using S expressions) * Eeschema can generate this netlist format. * Pcbnew can use (automatic identification) the current format or the new format. * Cvpcb does not use yet the new format.
2012-01-26 09:37:36 +00:00
( /324002E6 R3 R3 10K {Lib=R}
( 1 N-000072 )
( 2 VCC )
Eeschema: fix bug 706429
2011-01-23 12:32:33 +00:00
)
Pcbnew: First draft to use a new netlist format ( containing the same info as the intermediate netlist, but using S expressions) * Eeschema can generate this netlist format. * Pcbnew can use (automatic identification) the current format or the new format. * Cvpcb does not use yet the new format.
2012-01-26 09:37:36 +00:00
( /3240023F 32dip600 U5 628128 {Lib=628128}
( 2 /MA16 )
( 3 /MA14 )
( 4 /MA12 )
( 5 /MA7 )
( 6 /MA6 )
( 7 /MA5 )
( 8 /MA4 )
( 9 /MA3 )
( 10 /MA2 )
( 11 /MA1 )
( 12 /MA0 )
( 13 /MD0 )
( 14 /MD1 )
( 15 /MD2 )
( 16 GND )
( 17 /MD3 )
( 18 /MD4 )
( 19 /MD5 )
( 20 /MD6 )
( 21 /MD7 )
( 22 /CS1- )
( 23 /MA10 )
( 24 /OE- )
( 25 /MA11 )
( 26 /MA9 )
( 27 /MA8 )
( 28 /MA13 )
( 29 /WR- )
( 30 N-000072 )
( 31 /MA15 )
( 32 VCC )
Eeschema: fix bug 706429
2011-01-23 12:32:33 +00:00
)
Pcbnew: First draft to use a new netlist format ( containing the same info as the intermediate netlist, but using S expressions) * Eeschema can generate this netlist format. * Pcbnew can use (automatic identification) the current format or the new format. * Cvpcb does not use yet the new format.
2012-01-26 09:37:36 +00:00
( /32307ED4 C1 C3 47pF {Lib=C}
( 1 N-000146 )
( 2 GND )
Eeschema: fix bug 706429
2011-01-23 12:32:33 +00:00
)
Pcbnew: First draft to use a new netlist format ( containing the same info as the intermediate netlist, but using S expressions) * Eeschema can generate this netlist format. * Pcbnew can use (automatic identification) the current format or the new format. * Cvpcb does not use yet the new format.
2012-01-26 09:37:36 +00:00
( /32307ECF C1 C2 47pF {Lib=C}
( 1 N-000145 )
( 2 GND )
Eeschema: fix bug 706429
2011-01-23 12:32:33 +00:00
)
Pcbnew: First draft to use a new netlist format ( containing the same info as the intermediate netlist, but using S expressions) * Eeschema can generate this netlist format. * Pcbnew can use (automatic identification) the current format or the new format. * Cvpcb does not use yet the new format.
2012-01-26 09:37:36 +00:00
( /32307EC0 HC-18UH X1 8MHz {Lib=CRYSTAL}
( 1 N-000145 )
( 2 N-000146 )
Eeschema: fix bug 706429
2011-01-23 12:32:33 +00:00
)
Pcbnew: First draft to use a new netlist format ( containing the same info as the intermediate netlist, but using S expressions) * Eeschema can generate this netlist format. * Pcbnew can use (automatic identification) the current format or the new format. * Cvpcb does not use yet the new format.
2012-01-26 09:37:36 +00:00
( /32307EAA R3 R2 1K {Lib=R}
( 1 /8MH-OUT )
( 2 N-000146 )
Eeschema: fix bug 706429
2011-01-23 12:32:33 +00:00
)
Pcbnew: First draft to use a new netlist format ( containing the same info as the intermediate netlist, but using S expressions) * Eeschema can generate this netlist format. * Pcbnew can use (automatic identification) the current format or the new format. * Cvpcb does not use yet the new format.
2012-01-26 09:37:36 +00:00
( /32307EA1 R3 R1 100K {Lib=R}
( 1 N-000146 )
( 2 N-000145 )
Eeschema: fix bug 706429
2011-01-23 12:32:33 +00:00
)
Pcbnew: First draft to use a new netlist format ( containing the same info as the intermediate netlist, but using S expressions) * Eeschema can generate this netlist format. * Pcbnew can use (automatic identification) the current format or the new format. * Cvpcb does not use yet the new format.
2012-01-26 09:37:36 +00:00
( /32307DE2 CP6 C1 47uF {Lib=CP}
( 1 VCC )
( 2 GND )
Eeschema: fix bug 706429
2011-01-23 12:32:33 +00:00
)
Pcbnew: First draft to use a new netlist format ( containing the same info as the intermediate netlist, but using S expressions) * Eeschema can generate this netlist format. * Pcbnew can use (automatic identification) the current format or the new format. * Cvpcb does not use yet the new format.
2012-01-26 09:37:36 +00:00
( /32307DCF CP6 C4 47uF {Lib=CP}
( 1 VCC )
( 2 GND )
Eeschema: fix bug 706429
2011-01-23 12:32:33 +00:00
)
Pcbnew: First draft to use a new netlist format ( containing the same info as the intermediate netlist, but using S expressions) * Eeschema can generate this netlist format. * Pcbnew can use (automatic identification) the current format or the new format. * Cvpcb does not use yet the new format.
2012-01-26 09:37:36 +00:00
( /32307DCA CP6 C5 47uF {Lib=CP}
( 1 VCC )
( 2 GND )
Eeschema: fix bug 706429
2011-01-23 12:32:33 +00:00
)
Pcbnew: First draft to use a new netlist format ( containing the same info as the intermediate netlist, but using S expressions) * Eeschema can generate this netlist format. * Pcbnew can use (automatic identification) the current format or the new format. * Cvpcb does not use yet the new format.
2012-01-26 09:37:36 +00:00
( /32307DC0 CP6 C6 47uF {Lib=CP}
( 1 VCC )
( 2 GND )
Eeschema: fix bug 706429
2011-01-23 12:32:33 +00:00
)
Pcbnew: First draft to use a new netlist format ( containing the same info as the intermediate netlist, but using S expressions) * Eeschema can generate this netlist format. * Pcbnew can use (automatic identification) the current format or the new format. * Cvpcb does not use yet the new format.
2012-01-26 09:37:36 +00:00
( /322D35B4 20dip300 U2 74LS688 {Lib=74LS688}
( 1 /PC-AEN )
( 2 /PC-A5 )
( 3 /REF5 )
( 4 /PC-A8 )
( 5 /REF8 )
( 6 /PC-A9 )
( 7 /REF9 )
( 8 /PC-A11 )
( 9 /REF11 )
( 10 GND )
( 11 /PC-A10 )
( 12 /REF10 )
( 13 /PC-A7 )
( 14 /REF7 )
( 15 /PC-A6 )
( 16 /REF6 )
( 17 /PC-A4 )
( 18 /REF4 )
( 19 /MATCHL )
( 20 VCC )
Eeschema: fix bug 706429
2011-01-23 12:32:33 +00:00
)
Pcbnew: First draft to use a new netlist format ( containing the same info as the intermediate netlist, but using S expressions) * Eeschema can generate this netlist format. * Pcbnew can use (automatic identification) the current format or the new format. * Cvpcb does not use yet the new format.
2012-01-26 09:37:36 +00:00
( /322D32FA PGA120 U9 4003APG120 {Lib=4003APG120}
( A1 ? )
( A2 ? )
( A3 ? )
( A4 /MA9 )
( A5 /MD1 )
( A6 /MD3 )
( A7 /MD4 )
( A8 /MD5 )
( A9 /MD6 )
( A10 /CS1- )
( A11 /MA0 )
( A12 /STROBE )
( A13 /WR- )
( B1 ? )
( B2 /MA1 )
( B3 /MA7 )
( B4 ? )
( B5 ? )
( B6 /MD2 )
( B7 GND )
( B8 /MD7 )
( B9 /OE- )
( B10 ? )
( B11 VCC )
( B12 VCC )
( B13 ? )
( C1 /MA13 )
( C2 /MA3 )
( C3 VCC )
( C4 GND )
( C5 ? )
( C6 /MD0 )
( C8 /MA16 )
( C9 /MA10 )
( C10 GND )
( C11 VCC )
( C12 /AUTOFD- )
( C13 /MA5 )
( D1 /MA14 )
( D2 /MA11 )
( D3 /MA2 )
( D11 VCC )
( D12 /BIT0 )
( D13 /ERROR- )
( E1 /MA4 )
( E2 ? )
( E3 ? )
( E11 ? )
( E12 /INIT- )
( E13 /BIT1 )
( F1 /MA15 )
( F2 /MA6 )
( F3 /MA12 )
( F11 /SLCTIN- )
( F12 /BIT2 )
( F13 /LED2 )
( G1 /MA8 )
( G2 GND )
( G11 GND )
( G12 VCC )
( G13 /BIT3 )
( H1 /PC-A8 )
( H2 /PC-A7 )
( H3 /PC-A4 )
( H11 /BIT7 )
( H12 /BIT5 )
( H13 /BIT4 )
( J1 /PC-A6 )
( J2 /PC-A5 )
( J3 ? )
( J11 ? )
( J12 /BUST+ )
( J13 /BIT6 )
( K1 /8MH-OUT )
( K2 /PC-A3 )
( K3 GND )
( K11 GND )
( K12 ? )
( K13 /ACK )
( L1 N-000145 )
( L2 /SEL_LPT )
( L3 VCC )
( L4 /CLKLCA )
( L5 ? )
( L6 ? )
( L7 GND )
( L8 /PC-A10 )
( L9 ? )
( L10 VCC )
( L11 /DONE )
( L12 /D7 )
( L13 /PE+ )
( M1 ? )
( M2 ? )
( M3 /LED1 )
( M4 /CLKLCA )
( M5 /PC-A2 )
( M6 /PC-A0 )
( M7 VCC )
( M8 /PC-RD )
( M9 /D3 )
( M10 /D4 )
( M11 /D6 )
( M12 /PROG- )
( N1 ? )
( N2 /D0 )
( N3 ? )
( N4 /PC-A1 )
( N5 ? )
( N6 /PC-WR )
( N7 /PC-A9 )
( N8 /D1 )
( N9 /D2 )
( N10 /PC-AEN )
( N11 /D5 )
( N12 ? )
( N13 /SLCT+ )
Eeschema: fix bug 706429
2011-01-23 12:32:33 +00:00
)
Pcbnew: First draft to use a new netlist format ( containing the same info as the intermediate netlist, but using S expressions) * Eeschema can generate this netlist format. * Pcbnew can use (automatic identification) the current format or the new format. * Cvpcb does not use yet the new format.
2012-01-26 09:37:36 +00:00
( /322D32BE LEDV D2 LED {Lib=LED}
( 1 N-000103 )
( 2 GND )
Eeschema: fix bug 706429
2011-01-23 12:32:33 +00:00
)
Pcbnew: First draft to use a new netlist format ( containing the same info as the intermediate netlist, but using S expressions) * Eeschema can generate this netlist format. * Pcbnew can use (automatic identification) the current format or the new format. * Cvpcb does not use yet the new format.
2012-01-26 09:37:36 +00:00
( /322D32AC LEDV D1 LED {Lib=LED}
( 1 N-000107 )
( 2 GND )
Eeschema: fix bug 706429
2011-01-23 12:32:33 +00:00
)
Pcbnew: First draft to use a new netlist format ( containing the same info as the intermediate netlist, but using S expressions) * Eeschema can generate this netlist format. * Pcbnew can use (automatic identification) the current format or the new format. * Cvpcb does not use yet the new format.
2012-01-26 09:37:36 +00:00
( /322D32A0 R3 R5 330 {Lib=R}
( 1 N-000103 )
( 2 /LED2 )
Eeschema: fix bug 706429
2011-01-23 12:32:33 +00:00
)
Pcbnew: First draft to use a new netlist format ( containing the same info as the intermediate netlist, but using S expressions) * Eeschema can generate this netlist format. * Pcbnew can use (automatic identification) the current format or the new format. * Cvpcb does not use yet the new format.
2012-01-26 09:37:36 +00:00
( /322D3295 R3 R4 330 {Lib=R}
( 1 N-000107 )
( 2 /LED1 )
Eeschema: fix bug 706429
2011-01-23 12:32:33 +00:00
)
Pcbnew: First draft to use a new netlist format ( containing the same info as the intermediate netlist, but using S expressions) * Eeschema can generate this netlist format. * Pcbnew can use (automatic identification) the current format or the new format. * Cvpcb does not use yet the new format.
2012-01-26 09:37:36 +00:00
( /322D321C 24dip300 U8 EP600 {Lib=EP600}
( 1 GND )
( 2 /MATCHL )
( 3 N-000108 )
( 4 N-000109 )
( 5 N-000110 )
( 6 N-000111 )
( 7 /PC-WR )
( 8 ? )
( 9 ? )
( 10 ? )
( 11 /RSTL )
( 12 GND )
( 13 /WR_REG )
( 14 /PC-RD )
( 15 /WR_REG )
( 16 /CLKLCA )
( 17 /DIR )
( 18 /SEL_LPT )
( 19 /PROG- )
( 20 /DONE )
( 21 /D0 )
( 22 /ENBBUF )
( 23 VCC )
( 24 VCC )
Eeschema: fix bug 706429
2011-01-23 12:32:33 +00:00
)
Pcbnew: First draft to use a new netlist format ( containing the same info as the intermediate netlist, but using S expressions) * Eeschema can generate this netlist format. * Pcbnew can use (automatic identification) the current format or the new format. * Cvpcb does not use yet the new format.
2012-01-26 09:37:36 +00:00
( /322D31F4 20dip300 U1 74LS245 {Lib=74LS245}
( 1 /DIR )
( 2 /PC-DB0 )
( 3 /PC-DB1 )
( 4 /PC-DB2 )
( 5 /PC-DB3 )
( 6 /PC-DB4 )
( 7 /PC-DB5 )
( 8 /PC-DB6 )
( 9 /PC-DB7 )
( 10 GND )
( 11 /D7 )
( 12 /D6 )
( 13 /D5 )
( 14 /D4 )
( 15 /D3 )
( 16 /D2 )
( 17 /D1 )
( 18 /D0 )
( 19 /ENBBUF )
( 20 VCC )
Eeschema: fix bug 706429
2011-01-23 12:32:33 +00:00
)
Pcbnew: First draft to use a new netlist format ( containing the same info as the intermediate netlist, but using S expressions) * Eeschema can generate this netlist format. * Pcbnew can use (automatic identification) the current format or the new format. * Cvpcb does not use yet the new format.
2012-01-26 09:37:36 +00:00
( /322D3011 BUS_PC BUS1 BUSPC {Lib=BUSPC}
( 1 GND )
( 2 /PC-RST )
( 3 VCC )
( 4 ? )
( 5 ? )
( 6 ? )
( 7 ? )
( 8 ? )
( 9 ? )
( 10 ? )
( 11 ? )
( 12 ? )
( 13 /PC-IOW )
( 14 /PC-IOR )
( 15 ? )
( 16 ? )
( 17 ? )
( 18 ? )
( 19 ? )
( 20 ? )
( 21 ? )
( 22 ? )
( 23 ? )
( 24 ? )
( 25 ? )
( 26 ? )
( 27 ? )
( 28 ? )
( 29 VCC )
( 30 ? )
( 31 GND )
( 32 ? )
( 33 /PC-DB7 )
( 34 /PC-DB6 )
( 35 /PC-DB5 )
( 36 /PC-DB4 )
( 37 /PC-DB3 )
( 38 /PC-DB2 )
( 39 /PC-DB1 )
( 40 /PC-DB0 )
( 41 ? )
( 42 /PC-AEN )
( 43 ? )
( 44 ? )
( 45 ? )
( 46 ? )
( 47 ? )
( 48 ? )
( 49 ? )
( 50 ? )
( 51 /PC-A11 )
( 52 /PC-A10 )
( 53 /PC-A9 )
( 54 /PC-A8 )
( 55 /PC-A7 )
( 56 /PC-A6 )
( 57 /PC-A5 )
( 58 /PC-A4 )
( 59 /PC-A3 )
( 60 /PC-A2 )
( 61 /PC-A1 )
( 62 /PC-A0 )
Eeschema: fix bug 706429
2011-01-23 12:32:33 +00:00
)
)
*
{ Allowed footprints by component:
Pcbnew: First draft to use a new netlist format ( containing the same info as the intermediate netlist, but using S expressions) * Eeschema can generate this netlist format. * Pcbnew can use (automatic identification) the current format or the new format. * Cvpcb does not use yet the new format.
2012-01-26 09:37:36 +00:00
$component P1
DB25*
Eeschema: fix bug 706429
2011-01-23 12:32:33 +00:00
$endlist
Pcbnew: First draft to use a new netlist format ( containing the same info as the intermediate netlist, but using S expressions) * Eeschema can generate this netlist format. * Pcbnew can use (automatic identification) the current format or the new format. * Cvpcb does not use yet the new format.
2012-01-26 09:37:36 +00:00
$component R3
R?
SM0603
SM0805
R?-*
SM1206
$endlist
$component C3
Eeschema: fix bug 706429
2011-01-23 12:32:33 +00:00
SM*
C?
C1-1
$endlist
Pcbnew: First draft to use a new netlist format ( containing the same info as the intermediate netlist, but using S expressions) * Eeschema can generate this netlist format. * Pcbnew can use (automatic identification) the current format or the new format. * Cvpcb does not use yet the new format.
2012-01-26 09:37:36 +00:00
$component C2
CvPcb: Code cleanup. Rename WinEDA_CvpcbFrame to CVPCB_MAINFRAME, according to coding style policy. Change in CvPcb: CvPcb does not use now .dcm files, only .mod files to read modules keywords and doc
2011-02-05 16:15:48 +00:00
SM*
Cvpcb: code cleaning. Remove not used and useless files.
2011-02-21 18:27:47 +00:00
C?
C1-1
CvPcb: Code cleanup. Rename WinEDA_CvpcbFrame to CVPCB_MAINFRAME, according to coding style policy. Change in CvPcb: CvPcb does not use now .dcm files, only .mod files to read modules keywords and doc
2011-02-05 16:15:48 +00:00
$endlist
Pcbnew: First draft to use a new netlist format ( containing the same info as the intermediate netlist, but using S expressions) * Eeschema can generate this netlist format. * Pcbnew can use (automatic identification) the current format or the new format. * Cvpcb does not use yet the new format.
2012-01-26 09:37:36 +00:00
$component R2
R?
SM0603
SM0805
R?-*
SM1206
$endlist
$component R1
R?
SM0603
SM0805
R?-*
SM1206
$endlist
$component C1
CP*
SM*
$endlist
Eeschema: fix bug 706429
2011-01-23 12:32:33 +00:00
$component C4
CP*
SM*
$endlist
$component C5
CP*
SM*
$endlist
$component C6
CP*
SM*
$endlist
Pcbnew: First draft to use a new netlist format ( containing the same info as the intermediate netlist, but using S expressions) * Eeschema can generate this netlist format. * Pcbnew can use (automatic identification) the current format or the new format. * Cvpcb does not use yet the new format.
2012-01-26 09:37:36 +00:00
$component D2
Eeschema: fix bug 706429
2011-01-23 12:32:33 +00:00
LED-3MM
LED-5MM
LED-10MM
LED-0603
LED-0805
LED-1206
LEDV
$endlist
Pcbnew: First draft to use a new netlist format ( containing the same info as the intermediate netlist, but using S expressions) * Eeschema can generate this netlist format. * Pcbnew can use (automatic identification) the current format or the new format. * Cvpcb does not use yet the new format.
2012-01-26 09:37:36 +00:00
$component D1
Eeschema: fix bug 706429
2011-01-23 12:32:33 +00:00
LED-3MM
LED-5MM
LED-10MM
LED-0603
LED-0805
LED-1206
LEDV
$endlist
Pcbnew: First draft to use a new netlist format ( containing the same info as the intermediate netlist, but using S expressions) * Eeschema can generate this netlist format. * Pcbnew can use (automatic identification) the current format or the new format. * Cvpcb does not use yet the new format.
2012-01-26 09:37:36 +00:00
$component R5
Eeschema: fix bug 706429
2011-01-23 12:32:33 +00:00
R?
SM0603
SM0805
R?-*
SM1206
$endlist
$component R4
R?
SM0603
SM0805
R?-*
SM1206
$endlist
$endfootprintlist
}
Pcbnew: First draft to use a new netlist format ( containing the same info as the intermediate netlist, but using S expressions) * Eeschema can generate this netlist format. * Pcbnew can use (automatic identification) the current format or the new format. * Cvpcb does not use yet the new format.
2012-01-26 09:37:36 +00:00
{ Pin List by Nets
Net 15 "/PC-RST" "PC-RST"
BUS1 2
U3 8
U3 9
Net 16 "/PC-IOR" "PC-IOR"
BUS1 14
U3 7
Net 17 "/PC-IOW" "PC-IOW"
U3 6
BUS1 13
Net 19 "/PC-A1" "PC-A1"
BUS1 61
U9 N4
U3 2
Net 20 "/PC-A0" "PC-A0"
U9 M6
BUS1 62
U3 3
Net 21 "GND" "GND"
P1 18
U9 G11
U9 K11
U9 C10
U9 G2
BUS1 1
D2 2
U1 10
U9 C4
P1 20
D1 2
U9 K3
U8 1
U9 L7
U9 B7
JP1 13
JP1 11
P1 25
U5 16
P1 24
P1 23
JP1 15
U8 12
P1 22
P1 21
C1 2
C4 2
C5 2
C6 2
U2 10
C3 2
U3 10
U3 19
U3 1
JP1 7
JP1 5
JP1 3
JP1 1
C2 2
BUS1 31
P1 19
JP1 9
Net 22 "VCC" "VCC"
C1 1
C4 1
U8 24
C5 1
U8 23
C6 1
U2 20
U9 B12
U9 L3
U9 M7
U3 20
U9 D11
U1 20
U9 C11
U9 B11
R3 2
BUS1 3
BUS1 29
U9 G12
U5 32
U9 C3
U9 L10
RR1 1
Net 23 "/PC-AEN" "PC-AEN"
U9 N10
BUS1 42
U2 1
Net 52 "/MA8" "MA8"
U9 G1
U5 27
Net 53 "/MD4" "MD4"
U9 A7
U5 18
Net 54 "/MA13" "MA13"
U5 28
U9 C1
Net 55 "/MD5" "MD5"
U9 A8
U5 19
Net 56 "/WR-" "WR-"
U5 29
U9 A13
Net 57 "/MD3" "MD3"
U5 17
U9 A6
Net 61 "/RSTL" "RSTL"
U3 12
U8 11
Net 63 "/MA16" "MA16"
U9 C8
U5 2
Net 64 "/MA14" "MA14"
U5 3
U9 D1
Net 65 "/MA12" "MA12"
U9 F3
U5 4
Net 66 "/MA7" "MA7"
U5 5
U9 B3
Net 67 "/MA6" "MA6"
U9 F2
U5 6
Net 68 "/MA5" "MA5"
U9 C13
U5 7
Net 69 "/MA4" "MA4"
U9 E1
U5 8
Net 70 "/MA3" "MA3"
U5 9
U9 C2
Net 71 "/MD6" "MD6"
U9 A9
U5 20
Net 72 "" ""
R3 1
U5 30
Net 73 "/MD7" "MD7"
U5 21
U9 B8
Net 74 "/MA15" "MA15"
U5 31
U9 F1
Net 75 "/MA0" "MA0"
U5 12
U9 A11
Net 76 "/CS1-" "CS1-"
U9 A10
U5 22
Net 77 "/MD0" "MD0"
U9 C6
U5 13
Net 78 "/MA10" "MA10"
U5 23
U9 C9
Net 79 "/MD1" "MD1"
U5 14
U9 A5
Net 80 "/OE-" "OE-"
U5 24
U9 B9
Net 81 "/MD2" "MD2"
U5 15
U9 B6
Net 82 "/MA11" "MA11"
U5 25
U9 D2
Net 83 "/MA9" "MA9"
U5 26
U9 A4
Net 84 "/DIR" "DIR"
U8 17
U1 1
Net 85 "/ENBBUF" "ENBBUF"
U8 22
U1 19
Net 86 "/PC-RD" "PC-RD"
U8 14
U3 13
U9 M8
Net 87 "/SEL_LPT" "SEL_LPT"
U8 18
U9 L2
Net 88 "/PC-DB0" "PC-DB0"
U1 2
BUS1 40
Net 89 "/PC-DB1" "PC-DB1"
U1 3
BUS1 39
Net 90 "/PC-DB2" "PC-DB2"
U1 4
BUS1 38
Net 91 "/PC-DB3" "PC-DB3"
U1 5
BUS1 37
Net 92 "/PC-DB4" "PC-DB4"
BUS1 36
U1 6
Net 93 "/PC-DB5" "PC-DB5"
U1 7
BUS1 35
Net 94 "/PC-DB6" "PC-DB6"
U1 8
BUS1 34
Net 95 "/PC-DB7" "PC-DB7"
BUS1 33
U1 9
Net 96 "/D7" "D7"
U9 L12
U1 11
Net 97 "/D6" "D6"
U9 M11
U1 12
Net 98 "/D5" "D5"
U9 N11
U1 13
Net 99 "/D4" "D4"
U9 M10
U1 14
Net 100 "/D3" "D3"
U9 M9
U1 15
Net 101 "/D2" "D2"
U1 16
U9 N9
Net 102 "/D1" "D1"
U1 17
U9 N8
Net 103 "" ""
D2 1
R5 1
Net 105 "/LED2" "LED2"
R5 2
U9 F13
Net 106 "/D0" "D0"
U8 21
U9 N2
U1 18
Net 107 "" ""
D1 1
R4 1
Net 108 "" ""
U3 18
U8 3
Net 109 "" ""
U3 17
U8 4
Net 110 "" ""
U3 16
U8 5
Net 111 "" ""
U3 15
U8 6
Net 112 "/PC-WR" "PC-WR"
U8 7
U9 N6
U3 14
Net 113 "/PC-A6" "PC-A6"
U9 J1
BUS1 56
U2 15
Net 114 "/PC-A9" "PC-A9"
U9 N7
BUS1 53
U2 6
Net 115 "/PC-A8" "PC-A8"
U2 4
U9 H1
BUS1 54
Net 116 "/PC-A7" "PC-A7"
BUS1 55
U9 H2
U2 13
Net 117 "/PC-A5" "PC-A5"
BUS1 57
U2 2
U9 J2
Net 118 "/PC-A4" "PC-A4"
BUS1 58
U9 H3
U2 17
Net 119 "/PC-A3" "PC-A3"
U3 5
U9 K2
BUS1 59
Net 120 "/PC-A2" "PC-A2"
U3 4
U9 M5
BUS1 60
Net 121 "/PC-A11" "PC-A11"
U2 8
BUS1 51
Net 122 "/PC-A10" "PC-A10"
U9 L8
BUS1 52
U2 11
Net 123 "/LED1" "LED1"
U9 M3
R4 2
Net 125 "/MA2" "MA2"
U9 D3
U5 10
Net 128 "/CLKLCA" "CLKLCA"
U8 16
U9 L4
U9 M4
Net 131 "/MATCHL" "MATCHL"
U2 19
U8 2
Net 134 "/MA1" "MA1"
U5 11
U9 B2
Net 137 "/DONE" "DONE"
U8 20
U9 L11
Net 139 "/PROG-" "PROG-"
U8 19
U9 M12
Net 144 "/WR_REG" "WR_REG"
U8 13
U8 15
Net 145 "" ""
X1 1
C2 1
R1 2
U9 L1
Net 146 "" ""
X1 2
R1 1
C3 1
R2 2
Net 147 "/BIT6" "BIT6"
U9 J13
P1 8
Net 148 "/BIT7" "BIT7"
P1 9
U9 H11
Net 149 "/ACK" "ACK"
P1 10
U9 K13
Net 150 "/BUST+" "BUST+"
U9 J12
P1 11
Net 151 "/PE+" "PE+"
P1 12
U9 L13
Net 152 "/SLCT+" "SLCT+"
P1 13
U9 N13
Net 153 "/BIT5" "BIT5"
U9 H12
P1 7
Net 154 "/8MH-OUT" "8MH-OUT"
R2 1
U9 K1
Net 156 "/STROBE" "STROBE"
P1 1
U9 A12
Net 157 "/AUTOFD-" "AUTOFD-"
P1 14
U9 C12
Net 158 "/ERROR-" "ERROR-"
P1 15
U9 D13
Net 159 "/BIT2" "BIT2"
U9 F12
P1 4
Net 160 "/INIT-" "INIT-"
P1 16
U9 E12
Net 161 "/SLCTIN-" "SLCTIN-"
P1 17
U9 F11
Net 162 "/BIT0" "BIT0"
U9 D12
P1 2
Net 163 "/BIT1" "BIT1"
P1 3
U9 E13
Net 164 "/BIT3" "BIT3"
U9 G13
P1 5
Net 165 "/BIT4" "BIT4"
P1 6
U9 H13
Net 166 "/REF10" "REF10"
U2 12
JP1 2
RR1 9
Net 167 "/REF11" "REF11"
JP1 4
RR1 8
U2 9
Net 168 "/REF7" "REF7"
JP1 6
RR1 7
U2 14
Net 169 "/REF9" "REF9"
JP1 8
U2 7
RR1 6
Net 170 "/REF6" "REF6"
U2 16
RR1 5
JP1 10
Net 171 "/REF8" "REF8"
RR1 4
U2 5
JP1 12
Net 172 "/REF4" "REF4"
RR1 3
U2 18
JP1 14
Net 173 "/REF5" "REF5"
JP1 16
RR1 2
U2 3
}
#End