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kicad/demos/kit-dev-coldfire-xilinx_5213/kit-dev-coldfire-xilinx_521...

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Demos update
2020-01-01 10:19:36 +00:00
update=01/01/2020 11:13:44
Demos: make a private library for each demo, to avoid issues when using modified kicad new schematic libraries
2015-05-18 07:15:25 +00:00
last_client=kicad
add patch from Cirilo Bernardo, and minor fixes.
2014-01-25 12:23:29 +00:00
[general]
version=1
[cvpcb]
version=1
NetIExt=net
[cvpcb/libraries]
EquName1=devcms
update demo kit-dev-coldfire-xilinx_5213
2019-09-16 11:43:09 +00:00
[eeschema]
version=1
LibDir=
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=Pcbnew
SpiceAjustPassiveValues=0
LabSize=50
ERC_WriteFile=0
ERC_TestSimilarLabels=1
ERC_CheckUniqueGlobalLabels=1
ERC_CheckBusDriverConflicts=1
ERC_CheckBusEntryConflicts=1
ERC_CheckBusToBusConflicts=1
ERC_CheckBusToNetConflicts=1
Update demo files. A minor code cleaning.
2014-01-10 20:12:36 +00:00
[pcbnew]
version=1
add patch from Cirilo Bernardo, and minor fixes.
2014-01-25 12:23:29 +00:00
PageLayoutDescrFile=
Update demo files. A minor code cleaning.
2014-01-10 20:12:36 +00:00
LastNetListRead=
update demo kit-dev-coldfire-xilinx_5213
2019-09-16 11:43:09 +00:00
LastSTEPExportPath=
LastIDFExportPath=
LastVRMLExportPath=
LastSpecctraDSNExportPath=
LastGenCADExportPath=
CopperLayerCount=4
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=1
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.19812
MinViaDiameter=0.5
MinViaDrill=0.4
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
CopperEdgeClearance=0.01
TrackWidth1=0.2
Update demo
2019-11-16 14:37:24 +00:00
TrackWidth2=0.3
TrackWidth3=0.4
update demo kit-dev-coldfire-xilinx_5213
2019-09-16 11:43:09 +00:00
ViaDiameter1=0.6
ViaDrill1=0.4
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
demo update
2019-12-23 15:44:53 +00:00
SilkLineWidth=0.12
update demo kit-dev-coldfire-xilinx_5213
2019-09-16 11:43:09 +00:00
SilkTextSizeV=1
SilkTextSizeH=1
demo update
2019-12-23 15:44:53 +00:00
SilkTextSizeThickness=0.15
update demo kit-dev-coldfire-xilinx_5213
2019-09-16 11:43:09 +00:00
SilkTextItalic=0
demo update
2019-12-23 15:44:53 +00:00
SilkTextUpright=0
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
update demo kit-dev-coldfire-xilinx_5213
2019-09-16 11:43:09 +00:00
CopperTextItalic=0
demo update
2019-12-23 15:44:53 +00:00
CopperTextUpright=0
EdgeCutLineWidth=0.05
update demo kit-dev-coldfire-xilinx_5213
2019-09-16 11:43:09 +00:00
CourtyardLineWidth=0.05
OthersLineWidth=0.09999999999999999
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
demo update
2019-12-23 15:44:53 +00:00
OthersTextUpright=0
Update demo
2019-11-16 14:37:24 +00:00
DimensionUnits=0
DimensionPrecision=1
add patch from Cirilo Bernardo, and minor fixes.
2014-01-25 12:23:29 +00:00
SolderMaskClearance=0.2
SolderMaskMinWidth=0
update demo kit-dev-coldfire-xilinx_5213
2019-09-16 11:43:09 +00:00
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=Top_layer
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=GND_layer
Type=1
Enabled=1
[pcbnew/Layer.In2.Cu]
Name=VDD_layer
Type=1
Enabled=1
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=Bottom_layer
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=0
[pcbnew/Layer.Eco2.User]
Enabled=0
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.15
TrackWidth=0.2
ViaDiameter=0.6
ViaDrill=0.4
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/1]
Name=POWER
Clearance=0.15
TrackWidth=0.4
ViaDiameter=0.8
ViaDrill=0.4
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25