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kicad/qa/data/issue5320.kicad_pro

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Add zone filler tests. One test has pads of a bunch of different shapes and provokes some errors to make sure they're caught. The others are all past issues with the zone filler to make sure we don't suffer any regressions. (They should all just pass with no DRC errors.)
2021-07-30 16:08:12 +00:00
{
"board": {
"design_settings": {
"defaults": {
"board_outline_line_width": 0.09999999999999999,
"copper_line_width": 0.19999999999999998,
"copper_text_italic": false,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"copper_text_upright": true,
"courtyard_line_width": 0.049999999999999996,
"dimension_precision": 1,
"dimension_units": 0,
"fab_line_width": 0.09999999999999999,
"fab_text_italic": false,
"fab_text_size_h": 1.0,
"fab_text_size_v": 1.0,
"fab_text_thickness": 0.15,
"fab_text_upright": true,
"other_line_width": 0.09999999999999999,
"other_text_italic": false,
"other_text_size_h": 1.0,
"other_text_size_v": 1.0,
"other_text_thickness": 0.15,
"other_text_upright": true,
"pads": {
"drill": 0.0,
"height": 4.191,
"width": 2.667
},
"silk_line_width": 0.15,
"silk_text_italic": false,
"silk_text_size_h": 1.0,
"silk_text_size_v": 1.0,
"silk_text_thickness": 0.15,
"silk_text_upright": true,
"zones": {
"45_degree_only": false,
"min_clearance": 0.2794
}
},
"diff_pair_dimensions": [
{
"gap": 0.25,
"via_gap": 0.25,
"width": 0.2
}
],
"drc_exclusions": [],
"meta": {
"version": 0
},
"rule_severities": {
"clearance": "error",
"copper_edge_clearance": "error",
"courtyards_overlap": "error",
"drill_too_small": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"hole_near_hole": "error",
"invalid_outline": "error",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"keepout": "error",
"malformed_courtyard": "error",
"microvia_drill_too_small": "error",
"microvia_too_small": "error",
"missing_courtyard": "ignore",
"missing_footprint": "warning",
"npth_inside_courtyard": "ignore",
"padstack": "error",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"track_dangling": "warning",
"track_width": "error",
"tracks_crossing": "error",
"unconnected_items": "error",
"unresolved_variable": "error",
"via_annulus": "error",
"via_dangling": "warning",
"via_hole_larger_than_pad": "error",
"via_too_small": "error",
"zone_has_empty_net": "error",
"zones_intersect": "error"
},
"rules": {
"allow_blind_buried_vias": false,
"allow_microvias": false,
"max_error": 0.005,
"min_clearance": 0.127,
"min_copper_edge_clearance": 0.254,
"min_hole_to_hole": 0.254,
"min_microvia_diameter": 0.127,
"min_microvia_drill": 0.07619999999999999,
"min_through_hole_diameter": 0.254,
"min_track_width": 0.127,
"min_via_annulus": 0.127,
"min_via_diameter": 0.254,
"solder_mask_clearance": 0.0508,
"solder_mask_min_width": 0.1016,
"solder_paste_clearance": 0.0,
"solder_paste_margin_ratio": -0.0
},
"track_widths": [
0.127,
0.127,
0.1524,
0.254,
0.4318,
0.508,
0.762,
1.016,
1.27
],
"via_dimensions": [
{
"diameter": 0.508,
"drill": 0.254
},
{
"diameter": 0.508,
"drill": 0.254
},
{
"diameter": 0.762,
"drill": 0.381
},
{
"diameter": 1.016,
"drill": 0.508
},
{
"diameter": 1.27,
"drill": 0.635
}
],
"zones_use_no_outline": true
},
"layer_presets": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"erc": {
"meta": {
"version": 0
},
"pin_map": [
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],
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[
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[
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],
[
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2,
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]
],
"rule_severities": {
"bus_definition_conflict": "error",
"bus_label_syntax": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_sheet_names": "error",
"global_label_dangling": "error",
"hier_label_mismatch": "error",
"label_dangling": "error",
"multiple_net_names": "error",
"net_not_bus_member": "error",
"no_connect_connected": "error",
"no_connect_dangling": "error",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "warning",
"similar_labels": "error",
"unresolved_variable": "error"
}
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "VHF_Module.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 6.0,
"clearance": 0.127,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.127,
"microvia_drill": 0.762,
"name": "Default",
"track_width": 0.127,
"via_diameter": 0.508,
"via_drill": 0.254,
"wire_width": 6.0
}
],
"hidden_nets": [],
"meta": {
"version": 0
},
"net_colors": null
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "DC_DC_UAV_Converter.net",
"specctra_dsn": "",
"step": "../../../../Mechanical Design/JVAB/VHF Module/Rev 1.0A/VHF_Module_PCB.step",
"vmrl": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"drawing": {
"default_bus_thickness": 12.0,
"default_junction_size": 40.0,
"default_line_thickness": 6.0,
"default_text_size": 50.0,
"default_wire_thickness": 6.0,
"field_names": [],
"pin_symbol_size": 25.0,
"text_offset_ratio": 0.3
},
"legacy_lib_dir": "",
"legacy_lib_list": [],
"meta": {
"version": 0
},
"net_format_name": "",
"page_layout_descr_file": "",
"plot_directory": "C:/Temp/",
"spice_adjust_passive_values": false,
"spice_external_command": "spice \"%I\"",
"subpart_first_id": 65,
"subpart_id_separator": 0
},
"sheets": [
[
"4b2c37f4-6e30-41af-bed4-d50bb6c159d5",
""
]
],
"text_variables": {}
}