80 lines
968 B
Prolog
80 lines
968 B
Prolog
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update=18/4/2006-09:31:05
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last_client=pcbnew
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[general]
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version=1
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RootSch=pic_programmer.sch
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BoardNm=pic_programmer.brd
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[cvpcb]
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version=1
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NetITyp=0
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NetIExt=.net
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PkgIExt=.pkg
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NetType=0
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[cvpcb/libraries]
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EquName1=devcms
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[common]
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NetDir=
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[pcbnew]
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version=1
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PadDril=400
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PadDimH=700
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PadDimV=700
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PadForm=1
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PadMask=14745599
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ViaDiam=650
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ViaDril=250
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Isol=100
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Countlayer=2
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Lpiste=250
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RouteTo=15
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RouteBo=0
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TypeVia=3
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Segm45=1
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Racc45=1
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Unite=0
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SegFill=1
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SegAffG=0
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NewAffG=1
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PadFill=1
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PadAffG=1
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PadSNum=1
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ModAffC=1
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ModAffT=1
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PcbAffT=1
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SgPcb45=1
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TxtPcbV=800
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TxtPcbH=600
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TxtModV=600
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TxtModH=600
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TxtModW=120
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HPGLnum=1
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HPGdiam=15
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HPGLSpd=20
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HPGLrec=2
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HPGLorg=0
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GERBmin=15
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VEgarde=100
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DrawLar=150
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EdgeLar=150
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TxtLar=120
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MSegLar=150
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ForPlot=1
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WpenSer=10
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UserGrX=0,01
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UserGrY=0,01
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UserGrU=1
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DivGrPc=1
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TimeOut=600
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MaxLnkS=3
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ShowRat=0
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ShowMRa=1
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[pcbnew/libraries]
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LibDir=
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LibName1=supports
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LibName2=connect
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LibName3=discret
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LibName4=pin_array
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LibName5=divers
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LibName6=libcms
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LibName7=display
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