kicad/pcbnew/board_connected_item.cpp

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/*
* This program source code file is part of KiCad, a free EDA CAD application.
*
* Copyright (C) 2015 Jean-Pierre Charras, jp.charras at wanadoo.fr
* Copyright (C) 2012 SoftPLC Corporation, Dick Hollenbeck <dick@softplc.com>
* Copyright (C) 1992-2020 KiCad Developers, see AUTHORS.txt for contributors.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you may find one here:
* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
* or you may search the http://www.gnu.org website for the version 2 license,
* or you may write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
*/
#include <fctsys.h>
#include <class_board.h>
#include <class_board_item.h>
#include <connectivity/connectivity_data.h>
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using namespace std::placeholders;
BOARD_CONNECTED_ITEM::BOARD_CONNECTED_ITEM( BOARD_ITEM* aParent, KICAD_T idtype ) :
BOARD_ITEM( aParent, idtype ), m_netinfo( NETINFO_LIST::OrphanedItem() )
{
m_localRatsnestVisible = true;
}
bool BOARD_CONNECTED_ITEM::SetNetCode( int aNetCode, bool aNoAssert )
{
if( !IsOnCopperLayer() )
aNetCode = 0;
// if aNetCode < 0 ( typically NETINFO_LIST::FORCE_ORPHANED )
// or no parent board,
// set the m_netinfo to the dummy NETINFO_LIST::ORPHANED
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BOARD* board = GetBoard();
if( ( aNetCode >= 0 ) && board )
m_netinfo = board->FindNet( aNetCode );
Added NETINFO_MAPPING, to ease saving nets with consecutive net codes (without modifying the net codes during the run time). Now, nets are saved with consecutive net codes (both modern & legacy plugins). Zones are saved together with their nets, without depending on the fact if there are any pads with such net. Therefore validation of zone net names was removed (pcbnew/class_board.cpp). Performed tests: - Changed a pad's net name from empty to existent - ok, name was changed. - Changed a pad's net name from empty to nonexistent - ok, error message is displayed, net name stays empty. - Changed a pad's net name from existent to empty - ok, net name became empty - Changed a pad's net name from existent to nonexistent - ok, error message is displayed, net name is not changed. - Drawn a zone that belongs to a net, then modified schematics so the net does not exist anymore. After reloading the net list, all pads/tracks are updated. Zones still belongs to the net that does not exist in the schematic (but still exists in .kicad_pcb file). After running DRC, the zone becomes not filled. - Undo & redo affects assignment of a polygon to a specific net (you may change net of a polygon, refill it and undo/redo the changes). - KiCad s-expr & legacy, Eagle, P-CAD boards seem to load without any problem (they also contain correct net names assigned to the appropriate pads). All types of board file formats were loaded, then saved in sexpr format and reopened with a KiCad built from the master branch (without my modifications). - A few boards were also saved using the legacy format and were opened with the master KiCad without any issues. - Change a net name for a pad, restore with undo/redo - ok - Remove everything, restore with undo - ok - Remove everything, reload netlist - ok Differences observed between files saved by the master branch KiCad and this one: - list of nets are not saved in any particular order, so net codes may differ - the default net class does not contain the unconnected net
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else
m_netinfo = NETINFO_LIST::OrphanedItem();
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if( !aNoAssert )
wxASSERT( m_netinfo );
return ( m_netinfo != NULL );
}
// This method returns the Default netclass for nets which don't have their own.
NETCLASS* BOARD_CONNECTED_ITEM::GetEffectiveNetclass() const
{
// NB: we must check the net first, as when it is 0 GetNetClass() will return the
// orphaned net netclass, not the default netclass.
if( m_netinfo->GetNet() == 0 )
return GetBoard()->GetDesignSettings().GetDefault();
else
return GetNetClass();
}
/*
* Clearances exist in a hiearchy. If a given level is specified then the remaining levels
* are NOT consulted.
*
* LEVEL 1: (highest priority) local overrides (pad, footprint, etc.)
* LEVEL 2: Rules
* LEVEL 3: Accumulated local settings, netclass settings, & board design settings
*/
int BOARD_CONNECTED_ITEM::GetClearance( PCB_LAYER_ID aLayer, BOARD_ITEM* aItem,
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wxString* aSource, REPORTER* aReporter ) const
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{
BOARD* board = GetBoard();
int clearance = 0;
wxString source;
wxString* localSource = aSource ? &source : nullptr;
BOARD_CONNECTED_ITEM* second = dynamic_cast<BOARD_CONNECTED_ITEM*>( aItem );
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// No clearance if "this" is not (yet) linked to a board therefore no available netclass
if( !board )
return clearance;
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// LEVEL 1: local overrides (pad, footprint, etc.)
//
if( GetLocalClearanceOverrides( nullptr ) > clearance )
clearance = GetLocalClearanceOverrides( localSource );
if( second && second->GetLocalClearanceOverrides( nullptr ) > clearance )
clearance = second->GetLocalClearanceOverrides( localSource );
if( clearance )
{
if( aSource )
*aSource = *localSource;
return clearance;
}
// LEVEL 2: Rules
//
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if( GetRuleClearance( aItem, aLayer, &clearance, aSource, aReporter ) )
return clearance;
// LEVEL 3: Accumulated local settings, netclass settings, & board design settings
//
BOARD_DESIGN_SETTINGS& bds = board->GetDesignSettings();
NETCLASS* netclass = GetEffectiveNetclass();
NETCLASS* secondNetclass = second ? second->GetEffectiveNetclass() : nullptr;
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if( bds.m_MinClearance > clearance )
{
if( aSource )
*aSource = _( "board minimum" );
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clearance = bds.m_MinClearance;
}
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if( netclass && netclass->GetClearance() > clearance )
clearance = netclass->GetClearance( aSource );
if( secondNetclass && secondNetclass->GetClearance() > clearance )
clearance = secondNetclass->GetClearance( aSource );
if( aItem && aItem->GetLayer() == Edge_Cuts && bds.m_CopperEdgeClearance > clearance )
{
if( aSource )
*aSource = _( "board edge" );
clearance = bds.m_CopperEdgeClearance;
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}
if( GetLocalClearance( nullptr ) > clearance )
clearance = GetLocalClearance( aSource );
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if( second && second->GetLocalClearance( nullptr ) > clearance )
clearance = second->GetLocalClearance( aSource );
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return clearance;
}
bool BOARD_CONNECTED_ITEM::GetRuleClearance( BOARD_ITEM* aItem, PCB_LAYER_ID aLayer,
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int* aClearance, wxString* aSource,
REPORTER* aReporter ) const
{
const DRC_CONSTRAINT* constraint = GetConstraint( this, aItem, DRC_RULE_ID_CLEARANCE, aLayer,
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aSource, aReporter );
if( constraint )
{
if( aSource )
*aSource = wxString::Format( _( "'%s' rule" ), *aSource );
*aClearance = constraint->m_Value.Min();
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if( aReporter )
{
wxString clearance = StringFromValue( aReporter->GetUnits(), *aClearance, true );
aReporter->Report( wxString::Format( _( "Clearance: %s." ), clearance ) );
}
return true;
}
return false;
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}
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// Note: do NOT return a std::shared_ptr from this. It is used heavily in DRC, and the
// std::shared_ptr stuff shows up large in performance profiling.
NETCLASS* BOARD_CONNECTED_ITEM::GetNetClass() const
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{
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NETCLASS* netclass = m_netinfo->GetNetClass();
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if( netclass )
return netclass;
else
return GetBoard()->GetDesignSettings().GetDefault();
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}
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wxString BOARD_CONNECTED_ITEM::GetNetClassName() const
{
return m_netinfo->GetClassName();
}
static struct BOARD_CONNECTED_ITEM_DESC
{
BOARD_CONNECTED_ITEM_DESC()
{
ENUM_MAP<PCB_LAYER_ID>& layerEnum = ENUM_MAP<PCB_LAYER_ID>::Instance();
if( layerEnum.Choices().GetCount() == 0 )
{
layerEnum.Undefined( UNDEFINED_LAYER );
for( LSEQ seq = LSET::AllLayersMask().Seq(); seq; ++seq )
layerEnum.Map( *seq, LSET::Name( *seq ) );
}
PROPERTY_MANAGER& propMgr = PROPERTY_MANAGER::Instance();
REGISTER_TYPE( BOARD_CONNECTED_ITEM );
propMgr.InheritsAfter( TYPE_HASH( BOARD_CONNECTED_ITEM ), TYPE_HASH( BOARD_ITEM ) );
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propMgr.ReplaceProperty( TYPE_HASH( BOARD_ITEM ), _( "Layer" ),
new PROPERTY_ENUM<BOARD_CONNECTED_ITEM, PCB_LAYER_ID, BOARD_ITEM>( _( "Layer" ),
&BOARD_CONNECTED_ITEM::SetLayer, &BOARD_CONNECTED_ITEM::GetLayer ) );
propMgr.AddProperty( new PROPERTY_ENUM<BOARD_CONNECTED_ITEM, int>( _( "Net" ),
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&BOARD_CONNECTED_ITEM::SetNetCode, &BOARD_CONNECTED_ITEM::GetNetCode ) );
propMgr.AddProperty( new PROPERTY<BOARD_CONNECTED_ITEM, wxString>( _( "NetName" ),
NO_SETTER( BOARD_CONNECTED_ITEM, wxString ), &BOARD_CONNECTED_ITEM::GetNetname ) );
propMgr.AddProperty( new PROPERTY<BOARD_CONNECTED_ITEM, wxString>( _( "NetClass" ),
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NO_SETTER( BOARD_CONNECTED_ITEM, wxString ), &BOARD_CONNECTED_ITEM::GetNetClassName ) );
}
} _BOARD_CONNECTED_ITEM_DESC;