kicad/demos/pic_programmer/pic_programmer.pro

update=21/11/2017 20:47:02
last_client=kicad
[common]
NetDir=
[cvpcb]
version=1
NetIExt=net
[cvpcb/libraries]
EquName1=devcms
[general]
version=1
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=pic_programmer.net
UseCmpFile=0
PadDrill=0.8128
PadDrillOvalY=0.8128
PadSizeH=1.5748
PadSizeV=2.794
PcbTextSizeV=2.032
PcbTextSizeH=1.524
PcbTextThickness=0.3048
ModuleTextSizeV=1.524
ModuleTextSizeH=1.524
ModuleTextSizeThickness=0.3048
SolderMaskClearance=0.09999999999999999
SolderMaskMinWidth=0
DrawSegmentWidth=0.381
BoardOutlineThickness=0.381
ModuleOutlineThickness=0.381
[eeschema]
version=1
LibDir=
Update demos 2017-11-21 20:26:06 +00:00			`update=21/11/2017 20:47:02`
Update demos. Fix pspice netlist issues when using ( and ) in net names ( parenthesis are replaced by underscore) . 2014-01-07 19:42:34 +00:00			`last_client=kicad`
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending. 2013-05-26 04:36:44 +00:00			`[common]`
			`NetDir=`
Update demos. Fix pspice netlist issues when using ( and ) in net names ( parenthesis are replaced by underscore) . 2014-01-07 19:42:34 +00:00			`[cvpcb]`
			`version=1`
			`NetIExt=net`
			`[cvpcb/libraries]`
			`EquName1=devcms`
			`[general]`
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending. 2013-05-26 04:36:44 +00:00			`version=1`
Minor fixes: specctra export: skip malformed circles (having a radius = 0) in board outline creation, which can crash 3d-viewer or vrml export. dialog_fp_lib_table: remember during a session the last open table (global or local). drawing_tool: fix compil warning Update demos. 2014-09-22 07:51:06 +00:00			`[pcbnew]`
			`version=1`
			`PageLayoutDescrFile=`
			`LastNetListRead=pic_programmer.net`
			`UseCmpFile=0`
			`PadDrill=0.8128`
			`PadDrillOvalY=0.8128`
			`PadSizeH=1.5748`
			`PadSizeV=2.794`
			`PcbTextSizeV=2.032`
			`PcbTextSizeH=1.524`
			`PcbTextThickness=0.3048`
			`ModuleTextSizeV=1.524`
			`ModuleTextSizeH=1.524`
			`ModuleTextSizeThickness=0.3048`
			`SolderMaskClearance=0.09999999999999999`
			`SolderMaskMinWidth=0`
			`DrawSegmentWidth=0.381`
			`BoardOutlineThickness=0.381`
			`ModuleOutlineThickness=0.381`
Demos: make a private library for each demo, to avoid issues when using modified kicad new schematic libraries 2015-05-18 07:15:25 +00:00			`[eeschema]`
			`version=1`
			`LibDir=`