kicad/pcbnew/class_netinfo.h

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/*
* This program source code file is part of KiCad, a free EDA CAD application.
*
* Copyright (C) 2009 Jean-Pierre Charras, jaen-pierre.charras@gipsa-lab.inpg.com
* Copyright (C) 1992-2012 KiCad Developers, see AUTHORS.txt for contributors.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you may find one here:
* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
* or you may search the http://www.gnu.org website for the version 2 license,
* or you may write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
*/
/**
* @file class_netinfo.h
*/
/*
* Classes to handle info on nets
*/
#ifndef __CLASSES_NETINFO__
#define __CLASSES_NETINFO__
#include <vector>
#include <gr_basic.h>
#include <class_netclass.h>
Changed the way of looking up NETINFO_ITEM using net names (using boost::unordered_map). Added a hash function (wxString) for that. Introduced NETINFO_ITEM::GetNetItem( wxString ). BOARD::FindNet() uses the map. Net codes are updated upon net list update. (BOARD::ReplaceNetlist()) Added in some places (mostly class_board.cpp) pad->SetNet() calls to synchronize net codes. On creation of NETINFO_LIST, the first NETINFO_ITEM is added (the unconnected items net). Removed COMPONENT_NET::m_netNumber, as it was not used anywhere. Added an assert to D_PAD::GetNetname(), checking if net code and net name is consistent for unconnected pads. Added an assert for NETINFO_LIST::AppendNet() to assure that appended nets are unique. It seems that at this point: - Updating net lists works fine. The only difference between the file ouput is that after changes it contains empty nets as well. - Nets are not saved in the lexical order. Still, net names and net codes are properly assigned to all items in the .kicad_pcb file. It is going to be addressed in the next commit. I believe it should not create any problems, as pads are sorted by their net names anyway (NETINFO_LIST::buildPadsFullList()) Performed tests: - Created a blank PCB, saved as pic_programmer.kicad_pcb (from demos folder). Updated net lists. .kicad_pcb file (comparing to the results from master branch) differ with net order (as mentioned before), net codes and timestamps. - Removed some of components from the above .kicad_pcb file and updated net lists. Modules reappeared. .kicad_pcb file differs in the same way as described above. - Trying to change a pad net name (via properties dialog) results in assert being fired. It is done on purpose (as there is a call to GetNetname() and net name and net code do not match). This will not happen after the next commit. - Prepared a simple project (starting with schematics). Imported net list, changed schematic, reimported net list - changes are applied. - Eagle & KiCad legacy boards seem to load without any problem.
2014-01-10 17:04:07 +00:00
#include <boost/unordered_map.hpp>
#include <hashtables.h>
class wxDC;
class wxPoint;
class LINE_READER;
class EDA_DRAW_PANEL;
class EDA_DRAW_FRAME;
class NETINFO_ITEM;
class D_PAD;
class BOARD;
class BOARD_ITEM;
class MSG_PANEL_ITEM;
/*****************************/
/* flags for a RATSNEST_ITEM */
/*****************************/
#define CH_VISIBLE 1 /* Visible */
#define CH_UNROUTABLE 2 /* Don't use autorouter. */
#define CH_ROUTE_REQ 4 /* Must be routed by the autorouter. */
#define CH_ACTIF 8 /* Not routed. */
#define LOCAL_RATSNEST_ITEM 0x8000 /* Line between two pads of a single module. */
/**
* Class RATSNEST_ITEM
* describes a ratsnest line: a straight line connecting 2 pads
*/
class RATSNEST_ITEM
{
private:
int m_NetCode; // netcode ( = 1.. n , 0 is the value used for not connected items)
public:
int m_Status; // State: see previous defines (CH_ ...)
D_PAD* m_PadStart; // pointer to the starting pad
D_PAD* m_PadEnd; // pointer to ending pad
int m_Lenght; // length of the line (used in some calculations)
RATSNEST_ITEM();
/**
* Function GetNet
* @return int - the net code.
*/
int GetNet() const
{
return m_NetCode;
}
void SetNet( int aNetCode )
{
m_NetCode = aNetCode;
}
bool IsVisible()
{
return (m_Status & CH_VISIBLE) != 0;
}
bool IsActive()
{
return (m_Status & CH_ACTIF) != 0;
}
bool IsLocal()
{
return (m_Status & LOCAL_RATSNEST_ITEM) != 0;
}
/**
* Function Draw
*/
void Draw( EDA_DRAW_PANEL* panel, wxDC* DC, GR_DRAWMODE aDrawMode,
const wxPoint& offset );
};
/**
* Class NETINFO
* is a container class for NETINFO_ITEM elements, which are the nets. That makes
* this class a container for the nets.
*/
class NETINFO_LIST
{
friend class BOARD;
public:
NETINFO_LIST( BOARD* aParent );
~NETINFO_LIST();
/**
* Function GetItem
* @param aNetcode = netcode to identify a given NETINFO_ITEM
* @return NETINFO_ITEM* - by \a aNetcode, or NULL if not found
*/
NETINFO_ITEM* GetNetItem( int aNetcode ) const
{
if( unsigned( aNetcode ) >= GetNetCount() ) // catches < 0 too
return NULL;
return m_NetBuffer[aNetcode];
}
Changed the way of looking up NETINFO_ITEM using net names (using boost::unordered_map). Added a hash function (wxString) for that. Introduced NETINFO_ITEM::GetNetItem( wxString ). BOARD::FindNet() uses the map. Net codes are updated upon net list update. (BOARD::ReplaceNetlist()) Added in some places (mostly class_board.cpp) pad->SetNet() calls to synchronize net codes. On creation of NETINFO_LIST, the first NETINFO_ITEM is added (the unconnected items net). Removed COMPONENT_NET::m_netNumber, as it was not used anywhere. Added an assert to D_PAD::GetNetname(), checking if net code and net name is consistent for unconnected pads. Added an assert for NETINFO_LIST::AppendNet() to assure that appended nets are unique. It seems that at this point: - Updating net lists works fine. The only difference between the file ouput is that after changes it contains empty nets as well. - Nets are not saved in the lexical order. Still, net names and net codes are properly assigned to all items in the .kicad_pcb file. It is going to be addressed in the next commit. I believe it should not create any problems, as pads are sorted by their net names anyway (NETINFO_LIST::buildPadsFullList()) Performed tests: - Created a blank PCB, saved as pic_programmer.kicad_pcb (from demos folder). Updated net lists. .kicad_pcb file (comparing to the results from master branch) differ with net order (as mentioned before), net codes and timestamps. - Removed some of components from the above .kicad_pcb file and updated net lists. Modules reappeared. .kicad_pcb file differs in the same way as described above. - Trying to change a pad net name (via properties dialog) results in assert being fired. It is done on purpose (as there is a call to GetNetname() and net name and net code do not match). This will not happen after the next commit. - Prepared a simple project (starting with schematics). Imported net list, changed schematic, reimported net list - changes are applied. - Eagle & KiCad legacy boards seem to load without any problem.
2014-01-10 17:04:07 +00:00
/**
* Function GetItem
* @param aNetName = net name to identify a given NETINFO_ITEM
* @return NETINFO_ITEM* - by \a aNetName, or NULL if not found
*/
NETINFO_ITEM* GetNetItem( const wxString& aNetName ) const
{
NETNAMES_MAP::const_iterator result = m_netNames.find( aNetName );
if( result != m_netNames.end() )
return (*result).second;
return NULL;
}
/**
* Function GetNetCount
* @return the number of nets ( always >= 1 )
* because the first net is the "not connected" net and always exists
*/
unsigned GetNetCount() const { return m_NetBuffer.size(); }
/**
* Function Append
* adds \a aNewElement to the end of the list.
*/
void AppendNet( NETINFO_ITEM* aNewElement );
/**
* Function GetPadCount
* @return the number of pads in board
*/
unsigned GetPadCount() const { return m_PadsFullList.size(); }
/**
* Function GetPads
* returns a list of all the pads. The returned list is not
* sorted and contains pointers to PADS, but those pointers do not convey
* ownership of the respective PADs.
* @return std::vector<D_PAD*>& - a full list of pads
std::vector<D_PAD*>& GetPads()
{
return m_PadsFullList;
}
*/
/**
* Function GetPad
* @return the pad idx from m_PadsFullList
*/
D_PAD* GetPad( unsigned aIdx ) const
{
if( aIdx < m_PadsFullList.size() )
return m_PadsFullList[aIdx];
else
return NULL;
}
#if defined(DEBUG)
void Show() const;
#endif
Changed the way of looking up NETINFO_ITEM using net names (using boost::unordered_map). Added a hash function (wxString) for that. Introduced NETINFO_ITEM::GetNetItem( wxString ). BOARD::FindNet() uses the map. Net codes are updated upon net list update. (BOARD::ReplaceNetlist()) Added in some places (mostly class_board.cpp) pad->SetNet() calls to synchronize net codes. On creation of NETINFO_LIST, the first NETINFO_ITEM is added (the unconnected items net). Removed COMPONENT_NET::m_netNumber, as it was not used anywhere. Added an assert to D_PAD::GetNetname(), checking if net code and net name is consistent for unconnected pads. Added an assert for NETINFO_LIST::AppendNet() to assure that appended nets are unique. It seems that at this point: - Updating net lists works fine. The only difference between the file ouput is that after changes it contains empty nets as well. - Nets are not saved in the lexical order. Still, net names and net codes are properly assigned to all items in the .kicad_pcb file. It is going to be addressed in the next commit. I believe it should not create any problems, as pads are sorted by their net names anyway (NETINFO_LIST::buildPadsFullList()) Performed tests: - Created a blank PCB, saved as pic_programmer.kicad_pcb (from demos folder). Updated net lists. .kicad_pcb file (comparing to the results from master branch) differ with net order (as mentioned before), net codes and timestamps. - Removed some of components from the above .kicad_pcb file and updated net lists. Modules reappeared. .kicad_pcb file differs in the same way as described above. - Trying to change a pad net name (via properties dialog) results in assert being fired. It is done on purpose (as there is a call to GetNetname() and net name and net code do not match). This will not happen after the next commit. - Prepared a simple project (starting with schematics). Imported net list, changed schematic, reimported net list - changes are applied. - Eagle & KiCad legacy boards seem to load without any problem.
2014-01-10 17:04:07 +00:00
typedef boost::unordered_map<const wxString, NETINFO_ITEM*, WXSTRING_HASH> NETNAMES_MAP;
private:
/**
* Function DeleteData
* deletes the list of nets (and free memory)
*/
void clear();
/**
* Function buildListOfNets
* builds or rebuilds the list of NETINFO_ITEMs
* The list is sorted by names.
*/
void buildListOfNets();
/**
* Function buildPadsFullList
* creates the pad list, and initializes:
* m_Pads (list of pads)
* set m_Status_Pcb = LISTE_PAD_OK;
* and clear for all pads in list the m_SubRatsnest member;
* clear m_Pcb->m_FullRatsnest
*/
void buildPadsFullList();
BOARD* m_Parent;
Changed the way of looking up NETINFO_ITEM using net names (using boost::unordered_map). Added a hash function (wxString) for that. Introduced NETINFO_ITEM::GetNetItem( wxString ). BOARD::FindNet() uses the map. Net codes are updated upon net list update. (BOARD::ReplaceNetlist()) Added in some places (mostly class_board.cpp) pad->SetNet() calls to synchronize net codes. On creation of NETINFO_LIST, the first NETINFO_ITEM is added (the unconnected items net). Removed COMPONENT_NET::m_netNumber, as it was not used anywhere. Added an assert to D_PAD::GetNetname(), checking if net code and net name is consistent for unconnected pads. Added an assert for NETINFO_LIST::AppendNet() to assure that appended nets are unique. It seems that at this point: - Updating net lists works fine. The only difference between the file ouput is that after changes it contains empty nets as well. - Nets are not saved in the lexical order. Still, net names and net codes are properly assigned to all items in the .kicad_pcb file. It is going to be addressed in the next commit. I believe it should not create any problems, as pads are sorted by their net names anyway (NETINFO_LIST::buildPadsFullList()) Performed tests: - Created a blank PCB, saved as pic_programmer.kicad_pcb (from demos folder). Updated net lists. .kicad_pcb file (comparing to the results from master branch) differ with net order (as mentioned before), net codes and timestamps. - Removed some of components from the above .kicad_pcb file and updated net lists. Modules reappeared. .kicad_pcb file differs in the same way as described above. - Trying to change a pad net name (via properties dialog) results in assert being fired. It is done on purpose (as there is a call to GetNetname() and net name and net code do not match). This will not happen after the next commit. - Prepared a simple project (starting with schematics). Imported net list, changed schematic, reimported net list - changes are applied. - Eagle & KiCad legacy boards seem to load without any problem.
2014-01-10 17:04:07 +00:00
NETNAMES_MAP m_netNames; ///< map for a fast look up by net names
std::vector<NETINFO_ITEM*> m_NetBuffer; ///< net list (name, design constraints ..)
std::vector<D_PAD*> m_PadsFullList; ///< contains all pads, sorted by pad's netname.
///< can be used in ratsnest calculations.
};
/**
* Class NETINFO_ITEM
* handles the data for a net
*/
class NETINFO_ITEM
{
private:
const int m_NetCode; ///< A number equivalent to the net name.
///< Used for fast comparisons in ratsnest and DRC computations.
const wxString m_Netname; ///< Full net name like /mysheet/mysubsheet/vout
///< used by Eeschema
const wxString m_ShortNetname; // short net name, like vout from
// /mysheet/mysubsheet/vout
wxString m_NetClassName; // Net Class name. if void this is equivalent
// to "default" (the first
// item of the net classes list
NETCLASS* m_NetClass;
BOARD_ITEM* m_parent; ///< The parent board item object the net belongs to.
public:
int m_NbNodes; // Pads count for this net
int m_NbLink; // Ratsnets count for this net
int m_NbNoconn; // Ratsnets remaining to route count
int m_Flag; // used in some calculations. Had no
// special meaning
std::vector <D_PAD*> m_PadInNetList; // List of pads connected to this net
unsigned m_RatsnestStartIdx; /* Starting point of ratsnests of this
* net (included) in a general buffer of
* ratsnest (a vector<RATSNEST_ITEM*>
* buffer) */
unsigned m_RatsnestEndIdx; // Ending point of ratsnests of this net
// (excluded) in this buffer
2012-05-21 18:50:46 +00:00
NETINFO_ITEM( BOARD_ITEM* aParent, const wxString& aNetName = wxEmptyString, int aNetCode = 0 );
~NETINFO_ITEM();
/**
* Function SetClass
* sets \a aNetclass into this NET
*/
void SetClass( const NETCLASS* aNetClass )
{
m_NetClass = (NETCLASS*) aNetClass;
if( aNetClass )
m_NetClassName = aNetClass->GetName();
else
m_NetClassName = NETCLASS::Default;
}
NETCLASS* GetNetClass()
{
return m_NetClass;
}
/**
* Function GetClassName
* returns the class name
*/
const wxString& GetClassName() const
{
return m_NetClassName;
}
#if 1
/**
* Function GetTrackWidth
* returns the width of tracks used to route this net.
*/
int GetTrackWidth()
{
wxASSERT( m_NetClass );
return m_NetClass->GetTrackWidth();
}
/**
* Function GetViaSize
* returns the size of vias used to route this net
*/
int GetViaSize()
{
wxASSERT( m_NetClass );
return m_NetClass->GetViaDiameter();
}
/**
* Function GetMicroViaSize
* returns the size of vias used to route this net
*/
int GetMicroViaSize()
{
wxASSERT( m_NetClass );
return m_NetClass->GetuViaDiameter();
}
/**
* Function GetViaDrillSize
* returns the size of via drills used to route this net
*/
int GetViaDrillSize()
{
wxASSERT( m_NetClass );
return m_NetClass->GetViaDrill();
}
/**
* Function GetViaDrillSize
* returns the size of via drills used to route this net
*/
int GetMicroViaDrillSize()
{
wxASSERT( m_NetClass );
return m_NetClass->GetuViaDrill();
}
#if 0
/**
* Function GetViaMinSize
* returns the Minimum value for via sizes (used in DRC)
*/
int GetViaMinSize()
{
wxASSERT( m_NetClass );
return m_NetClass->GetViaMinSize();
}
#endif
/**
* Function GetClearance
* returns the clearance when routing near aBoardItem
*/
int GetClearance( BOARD_ITEM* aBoardItem )
{
wxASSERT( m_NetClass );
return m_NetClass->GetClearance();
}
#endif
/**
* Function Draw
* @todo we actually could show a NET, simply show all the tracks and
* a pads or net name on pad and vias
*/
void Draw( EDA_DRAW_PANEL* panel, wxDC* DC, GR_DRAWMODE aDrawMode,
const wxPoint& offset );
/**
* Function GetNet
* @return int - the netcode
*/
int GetNet() const { return m_NetCode; }
/**
* Function GetNodesCount
* @return int - number of nodes in the net
*/
int GetNodesCount() const { return m_PadInNetList.size(); }
/**
* Function GetNetname
Changed the way of looking up NETINFO_ITEM using net names (using boost::unordered_map). Added a hash function (wxString) for that. Introduced NETINFO_ITEM::GetNetItem( wxString ). BOARD::FindNet() uses the map. Net codes are updated upon net list update. (BOARD::ReplaceNetlist()) Added in some places (mostly class_board.cpp) pad->SetNet() calls to synchronize net codes. On creation of NETINFO_LIST, the first NETINFO_ITEM is added (the unconnected items net). Removed COMPONENT_NET::m_netNumber, as it was not used anywhere. Added an assert to D_PAD::GetNetname(), checking if net code and net name is consistent for unconnected pads. Added an assert for NETINFO_LIST::AppendNet() to assure that appended nets are unique. It seems that at this point: - Updating net lists works fine. The only difference between the file ouput is that after changes it contains empty nets as well. - Nets are not saved in the lexical order. Still, net names and net codes are properly assigned to all items in the .kicad_pcb file. It is going to be addressed in the next commit. I believe it should not create any problems, as pads are sorted by their net names anyway (NETINFO_LIST::buildPadsFullList()) Performed tests: - Created a blank PCB, saved as pic_programmer.kicad_pcb (from demos folder). Updated net lists. .kicad_pcb file (comparing to the results from master branch) differ with net order (as mentioned before), net codes and timestamps. - Removed some of components from the above .kicad_pcb file and updated net lists. Modules reappeared. .kicad_pcb file differs in the same way as described above. - Trying to change a pad net name (via properties dialog) results in assert being fired. It is done on purpose (as there is a call to GetNetname() and net name and net code do not match). This will not happen after the next commit. - Prepared a simple project (starting with schematics). Imported net list, changed schematic, reimported net list - changes are applied. - Eagle & KiCad legacy boards seem to load without any problem.
2014-01-10 17:04:07 +00:00
* @return const wxString&, a reference to the full netname
*/
Changed the way of looking up NETINFO_ITEM using net names (using boost::unordered_map). Added a hash function (wxString) for that. Introduced NETINFO_ITEM::GetNetItem( wxString ). BOARD::FindNet() uses the map. Net codes are updated upon net list update. (BOARD::ReplaceNetlist()) Added in some places (mostly class_board.cpp) pad->SetNet() calls to synchronize net codes. On creation of NETINFO_LIST, the first NETINFO_ITEM is added (the unconnected items net). Removed COMPONENT_NET::m_netNumber, as it was not used anywhere. Added an assert to D_PAD::GetNetname(), checking if net code and net name is consistent for unconnected pads. Added an assert for NETINFO_LIST::AppendNet() to assure that appended nets are unique. It seems that at this point: - Updating net lists works fine. The only difference between the file ouput is that after changes it contains empty nets as well. - Nets are not saved in the lexical order. Still, net names and net codes are properly assigned to all items in the .kicad_pcb file. It is going to be addressed in the next commit. I believe it should not create any problems, as pads are sorted by their net names anyway (NETINFO_LIST::buildPadsFullList()) Performed tests: - Created a blank PCB, saved as pic_programmer.kicad_pcb (from demos folder). Updated net lists. .kicad_pcb file (comparing to the results from master branch) differ with net order (as mentioned before), net codes and timestamps. - Removed some of components from the above .kicad_pcb file and updated net lists. Modules reappeared. .kicad_pcb file differs in the same way as described above. - Trying to change a pad net name (via properties dialog) results in assert being fired. It is done on purpose (as there is a call to GetNetname() and net name and net code do not match). This will not happen after the next commit. - Prepared a simple project (starting with schematics). Imported net list, changed schematic, reimported net list - changes are applied. - Eagle & KiCad legacy boards seem to load without any problem.
2014-01-10 17:04:07 +00:00
const wxString& GetNetname() const { return m_Netname; }
/**
* Function GetShortNetname
Changed the way of looking up NETINFO_ITEM using net names (using boost::unordered_map). Added a hash function (wxString) for that. Introduced NETINFO_ITEM::GetNetItem( wxString ). BOARD::FindNet() uses the map. Net codes are updated upon net list update. (BOARD::ReplaceNetlist()) Added in some places (mostly class_board.cpp) pad->SetNet() calls to synchronize net codes. On creation of NETINFO_LIST, the first NETINFO_ITEM is added (the unconnected items net). Removed COMPONENT_NET::m_netNumber, as it was not used anywhere. Added an assert to D_PAD::GetNetname(), checking if net code and net name is consistent for unconnected pads. Added an assert for NETINFO_LIST::AppendNet() to assure that appended nets are unique. It seems that at this point: - Updating net lists works fine. The only difference between the file ouput is that after changes it contains empty nets as well. - Nets are not saved in the lexical order. Still, net names and net codes are properly assigned to all items in the .kicad_pcb file. It is going to be addressed in the next commit. I believe it should not create any problems, as pads are sorted by their net names anyway (NETINFO_LIST::buildPadsFullList()) Performed tests: - Created a blank PCB, saved as pic_programmer.kicad_pcb (from demos folder). Updated net lists. .kicad_pcb file (comparing to the results from master branch) differ with net order (as mentioned before), net codes and timestamps. - Removed some of components from the above .kicad_pcb file and updated net lists. Modules reappeared. .kicad_pcb file differs in the same way as described above. - Trying to change a pad net name (via properties dialog) results in assert being fired. It is done on purpose (as there is a call to GetNetname() and net name and net code do not match). This will not happen after the next commit. - Prepared a simple project (starting with schematics). Imported net list, changed schematic, reimported net list - changes are applied. - Eagle & KiCad legacy boards seem to load without any problem.
2014-01-10 17:04:07 +00:00
* @return const wxString &, a reference to the short netname
*/
Changed the way of looking up NETINFO_ITEM using net names (using boost::unordered_map). Added a hash function (wxString) for that. Introduced NETINFO_ITEM::GetNetItem( wxString ). BOARD::FindNet() uses the map. Net codes are updated upon net list update. (BOARD::ReplaceNetlist()) Added in some places (mostly class_board.cpp) pad->SetNet() calls to synchronize net codes. On creation of NETINFO_LIST, the first NETINFO_ITEM is added (the unconnected items net). Removed COMPONENT_NET::m_netNumber, as it was not used anywhere. Added an assert to D_PAD::GetNetname(), checking if net code and net name is consistent for unconnected pads. Added an assert for NETINFO_LIST::AppendNet() to assure that appended nets are unique. It seems that at this point: - Updating net lists works fine. The only difference between the file ouput is that after changes it contains empty nets as well. - Nets are not saved in the lexical order. Still, net names and net codes are properly assigned to all items in the .kicad_pcb file. It is going to be addressed in the next commit. I believe it should not create any problems, as pads are sorted by their net names anyway (NETINFO_LIST::buildPadsFullList()) Performed tests: - Created a blank PCB, saved as pic_programmer.kicad_pcb (from demos folder). Updated net lists. .kicad_pcb file (comparing to the results from master branch) differ with net order (as mentioned before), net codes and timestamps. - Removed some of components from the above .kicad_pcb file and updated net lists. Modules reappeared. .kicad_pcb file differs in the same way as described above. - Trying to change a pad net name (via properties dialog) results in assert being fired. It is done on purpose (as there is a call to GetNetname() and net name and net code do not match). This will not happen after the next commit. - Prepared a simple project (starting with schematics). Imported net list, changed schematic, reimported net list - changes are applied. - Eagle & KiCad legacy boards seem to load without any problem.
2014-01-10 17:04:07 +00:00
const wxString& GetShortNetname() const { return m_ShortNetname; }
/**
* Function GetMsgPanelInfo
* returns the information about the #NETINFO_ITEM in \a aList to display in the
* message panel.
*
* @param aList is the list in which to place the status information.
*/
void GetMsgPanelInfo( std::vector< MSG_PANEL_ITEM >& aList );
/**
* Function Clear
* sets all fields to their defaults values.
*/
void Clear()
{
m_PadInNetList.clear();
m_NbNodes = 0;
m_NbLink = 0;
m_NbNoconn = 0;
m_Flag = 0;
m_RatsnestStartIdx = 0; // Starting point of ratsnests of this net in a
// general buffer of ratsnest
m_RatsnestEndIdx = 0; // Ending point of ratsnests of this net
SetClass( NULL );
}
};
/***********************************************************/
/* Description of a trace point for monitoring connections */
/***********************************************************/
#define START_ON_PAD 0x10
#define END_ON_PAD 0x20
#define START_ON_TRACK 0x40
#define END_ON_TRACK 0x80
/* Status bit (OR'ed bits) for class BOARD member .m_Status_Pcb */
enum StatusPcbFlags {
LISTE_PAD_OK = 1, /* Pad list is Ok */
LISTE_RATSNEST_ITEM_OK = 2, /* General Ratsnest is Ok */
RATSNEST_ITEM_LOCAL_OK = 4, /* current MODULE ratsnest is Ok */
CONNEXION_OK = 8, /* List of connections exists. */
NET_CODES_OK = 0x10, /* Bit indicating that Netcode is OK,
* do not change net name. */
DO_NOT_SHOW_GENERAL_RASTNEST = 0x20 /* Do not display the general
* ratsnest (used in module moves) */
};
#endif // __CLASSES_NETINFO__