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kicad/demos/sonde xilinx/sonde xilinx.kicad_pcb

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Update demos
2018-02-01 12:25:56 +00:00
(kicad_pcb (version 20171130) (host pcbnew "(2018-01-31 revision c758e72)-master")
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(general
(thickness 1.6002)
Update demos. Fix pspice netlist issues when using ( and ) in net names ( parenthesis are replaced by underscore) .
2014-01-07 19:42:34 +00:00
(drawings 19)
Update demos
2018-02-01 12:25:56 +00:00
(tracks 269)
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(zones 0)
Update demos. Fix pspice netlist issues when using ( and ) in net names ( parenthesis are replaced by underscore) .
2014-01-07 19:42:34 +00:00
(modules 25)
Update demo
2018-01-10 15:41:40 +00:00
(nets 43)
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
)
(page A4)
Update demos. Fix pspice netlist issues when using ( and ) in net names ( parenthesis are replaced by underscore) .
2014-01-07 19:42:34 +00:00
(title_block
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(rev 1)
(company "Kicad Demo")
)
(layers
Corrected a few pads layer settings in 'sonde xilinx' demo.
2015-04-16 07:33:33 +00:00
(0 Dessus signal)
(31 Dessous signal)
(32 B.Adhes user)
(33 F.Adhes user)
(34 B.Paste user)
(35 F.Paste user)
(36 B.SilkS user)
(37 F.SilkS user)
(38 B.Mask user)
(39 F.Mask user)
(40 Dwgs.User user)
(41 Cmts.User user)
(42 Eco1.User user)
(43 Eco2.User user)
(44 Edge.Cuts user)
Update demos
2018-01-12 20:30:07 +00:00
(45 Margin user)
(46 B.CrtYd user)
(47 F.CrtYd user)
(48 B.Fab user)
(49 F.Fab user)
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
)
(setup
(last_trace_width 0.635)
Update demos. Fix pspice netlist issues when using ( and ) in net names ( parenthesis are replaced by underscore) .
2014-01-07 19:42:34 +00:00
(user_trace_width 0.4)
(user_trace_width 1)
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(trace_clearance 0.254)
(zone_clearance 0.508)
(zone_45_only no)
(trace_min 0.2032)
Update demos. Fix pspice netlist issues when using ( and ) in net names ( parenthesis are replaced by underscore) .
2014-01-07 19:42:34 +00:00
(segment_width 0.3)
(edge_width 0.1)
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(via_size 1.651)
(via_drill 0.635)
(via_min_size 0.889)
(via_min_drill 0.508)
(uvia_size 0.508)
(uvia_drill 0.127)
(uvias_allowed no)
(uvia_min_size 0.508)
(uvia_min_drill 0.127)
(pcb_text_width 0.3048)
Update demos. Fix pspice netlist issues when using ( and ) in net names ( parenthesis are replaced by underscore) .
2014-01-07 19:42:34 +00:00
(pcb_text_size 1.5 1.5)
(mod_edge_width 0.3)
(mod_text_size 0.3 1.5)
(mod_text_width 0.3)
Corrected a few pads layer settings in 'sonde xilinx' demo.
2015-04-16 07:33:33 +00:00
(pad_size 1.778 5.08)
(pad_drill 0)
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(pad_to_mask_clearance 0.254)
(aux_axis_origin 0 0)
Update demos. Fix pspice netlist issues when using ( and ) in net names ( parenthesis are replaced by underscore) .
2014-01-07 19:42:34 +00:00
(visible_elements 7FFFFFFF)
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(pcbplotparams
Corrected a few pads layer settings in 'sonde xilinx' demo.
2015-04-16 07:33:33 +00:00
(layerselection 0x00030_80000001)
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(usegerberextensions false)
Update demo
2018-01-10 15:41:40 +00:00
(usegerberattributes false)
(usegerberadvancedattributes false)
(creategerberjobfile false)
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(excludeedgelayer false)
Update demos. Fix pspice netlist issues when using ( and ) in net names ( parenthesis are replaced by underscore) .
2014-01-07 19:42:34 +00:00
(linewidth 0.150000)
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
(plotinvisibletext false)
(padsonsilk false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 1)
(scaleselection 1)
(outputdirectory ""))
)
(net 0 "")
(net 1 /CLK-D1)
(net 2 /CTRL-D3)
(net 3 /DONE-SELECT*)
(net 4 /PWR_3,3-5V)
(net 5 /TCK-CCLK)
(net 6 /TD0-DONE)
(net 7 /TD0-PROG-D4)
(net 8 /TDI-DIN)
(net 9 /TDI-DIN-D0)
(net 10 /TMS-PROG)
(net 11 /TMS-PROG-D2)
(net 12 /VCC_SENSE-ERROR*)
(net 13 GND)
Update demo
2018-01-10 15:41:40 +00:00
(net 14 VCC)
(net 15 "Net-(C3-Pad1)")
(net 16 "Net-(R4-Pad1)")
(net 17 "Net-(U2-Pad6)")
(net 18 "Net-(U2-Pad8)")
(net 19 "Net-(U2-Pad11)")
(net 20 "Net-(R6-Pad1)")
(net 21 "Net-(R8-Pad1)")
(net 22 "Net-(R7-Pad1)")
(net 23 "Net-(C2-Pad1)")
(net 24 "Net-(C5-Pad1)")
(net 25 "Net-(R10-Pad1)")
(net 26 "Net-(C4-Pad1)")
(net 27 "Net-(R9-Pad1)")
(net 28 "Net-(D1-Pad2)")
(net 29 "Net-(J1-Pad11)")
(net 30 "Net-(J1-Pad10)")
(net 31 "Net-(J1-Pad9)")
(net 32 "Net-(J1-Pad7)")
(net 33 "Net-(J1-Pad1)")
(net 34 "Net-(J1-Pad24)")
(net 35 "Net-(J1-Pad23)")
(net 36 "Net-(J1-Pad22)")
(net 37 "Net-(J1-Pad21)")
(net 38 "Net-(J1-Pad19)")
(net 39 "Net-(J1-Pad18)")
(net 40 "Net-(J1-Pad17)")
(net 41 "Net-(J1-Pad16)")
(net 42 "Net-(J1-Pad14)")
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(net_class Default "Ceci est la Netclass par défaut"
(clearance 0.254)
(trace_width 0.635)
(via_dia 1.651)
(via_drill 0.635)
(uvia_dia 0.508)
(uvia_drill 0.127)
(add_net /CLK-D1)
(add_net /CTRL-D3)
(add_net /DONE-SELECT*)
(add_net /PWR_3,3-5V)
(add_net /TCK-CCLK)
(add_net /TD0-DONE)
(add_net /TD0-PROG-D4)
(add_net /TDI-DIN)
(add_net /TDI-DIN-D0)
(add_net /TMS-PROG)
(add_net /TMS-PROG-D2)
(add_net /VCC_SENSE-ERROR*)
(add_net GND)
Update demo
2018-01-10 15:41:40 +00:00
(add_net "Net-(C2-Pad1)")
(add_net "Net-(C3-Pad1)")
(add_net "Net-(C4-Pad1)")
(add_net "Net-(C5-Pad1)")
(add_net "Net-(D1-Pad2)")
(add_net "Net-(J1-Pad1)")
(add_net "Net-(J1-Pad10)")
(add_net "Net-(J1-Pad11)")
(add_net "Net-(J1-Pad14)")
(add_net "Net-(J1-Pad16)")
(add_net "Net-(J1-Pad17)")
(add_net "Net-(J1-Pad18)")
(add_net "Net-(J1-Pad19)")
(add_net "Net-(J1-Pad21)")
(add_net "Net-(J1-Pad22)")
(add_net "Net-(J1-Pad23)")
(add_net "Net-(J1-Pad24)")
(add_net "Net-(J1-Pad7)")
(add_net "Net-(J1-Pad9)")
(add_net "Net-(R10-Pad1)")
(add_net "Net-(R4-Pad1)")
(add_net "Net-(R6-Pad1)")
(add_net "Net-(R7-Pad1)")
(add_net "Net-(R8-Pad1)")
(add_net "Net-(R9-Pad1)")
(add_net "Net-(U2-Pad11)")
(add_net "Net-(U2-Pad6)")
(add_net "Net-(U2-Pad8)")
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(add_net VCC)
)
Update demos
2018-02-01 12:25:56 +00:00
(module Connector_Dsub:DSUB-25_Male_EdgeMount_P2.77mm (layer Dessus) (tedit 59FEDEE2) (tstamp 5A73AC29)
(at 105.5116 89.1032 270)
(descr "25-pin D-Sub connector, solder-cups edge-mounted, male, x-pin-pitch 2.77mm, distance of mounting holes 47.1mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf")
(tags "25-pin D-Sub connector edge mount solder cup male x-pin-pitch 2.77mm mounting holes distance 47.1mm")
(path /3EBF7D04)
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(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user "PCB edge" (at -21.55 1.323333 270) (layer Dwgs.User)
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(pad 1 smd rect (at -16.62 0 270) (size 1.846667 3.48) (layers Dessus F.Paste F.Mask)
(net 33 "Net-(J1-Pad1)"))
(pad 2 smd rect (at -13.85 0 270) (size 1.846667 3.48) (layers Dessus F.Paste F.Mask)
(net 9 /TDI-DIN-D0))
(pad 3 smd rect (at -11.08 0 270) (size 1.846667 3.48) (layers Dessus F.Paste F.Mask)
(net 1 /CLK-D1))
(pad 4 smd rect (at -8.31 0 270) (size 1.846667 3.48) (layers Dessus F.Paste F.Mask)
(net 11 /TMS-PROG-D2))
(pad 5 smd rect (at -5.54 0 270) (size 1.846667 3.48) (layers Dessus F.Paste F.Mask)
(net 2 /CTRL-D3))
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(net 31 "Net-(J1-Pad9)"))
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(net 29 "Net-(J1-Pad11)"))
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(net 29 "Net-(J1-Pad11)"))
(pad 13 smd rect (at 16.62 0 270) (size 1.846667 3.48) (layers Dessus F.Paste F.Mask)
(net 3 /DONE-SELECT*))
(pad 14 smd rect (at -15.235 0 270) (size 1.846667 3.48) (layers Dessous B.Paste B.Mask)
(net 42 "Net-(J1-Pad14)"))
(pad 15 smd rect (at -12.465 0 270) (size 1.846667 3.48) (layers Dessous B.Paste B.Mask)
(net 12 /VCC_SENSE-ERROR*))
(pad 16 smd rect (at -9.695 0 270) (size 1.846667 3.48) (layers Dessous B.Paste B.Mask)
(net 41 "Net-(J1-Pad16)"))
(pad 17 smd rect (at -6.925 0 270) (size 1.846667 3.48) (layers Dessous B.Paste B.Mask)
(net 40 "Net-(J1-Pad17)"))
(pad 18 smd rect (at -4.155 0 270) (size 1.846667 3.48) (layers Dessous B.Paste B.Mask)
(net 39 "Net-(J1-Pad18)"))
(pad 19 smd rect (at -1.385 0 270) (size 1.846667 3.48) (layers Dessous B.Paste B.Mask)
(net 38 "Net-(J1-Pad19)"))
(pad 20 smd rect (at 1.385 0 270) (size 1.846667 3.48) (layers Dessous B.Paste B.Mask)
(net 13 GND))
(pad 21 smd rect (at 4.155 0 270) (size 1.846667 3.48) (layers Dessous B.Paste B.Mask)
(net 37 "Net-(J1-Pad21)"))
(pad 22 smd rect (at 6.925 0 270) (size 1.846667 3.48) (layers Dessous B.Paste B.Mask)
(net 36 "Net-(J1-Pad22)"))
(pad 23 smd rect (at 9.695 0 270) (size 1.846667 3.48) (layers Dessous B.Paste B.Mask)
(net 35 "Net-(J1-Pad23)"))
(pad 24 smd rect (at 12.465 0 270) (size 1.846667 3.48) (layers Dessous B.Paste B.Mask)
(net 34 "Net-(J1-Pad24)"))
(pad 25 smd rect (at 15.235 0 270) (size 1.846667 3.48) (layers Dessous B.Paste B.Mask)
(net 13 GND))
(model ${KISYS3DMOD}/Connector_Dsub.3dshapes/DSUB-25_Male_EdgeMount_P2.77mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Connector_Dsub:DSUB-9_Male_EdgeMount_P2.77mm (layer Dessous) (tedit 59FEDEE2) (tstamp 5A73B143)
(at 181.61 90.1192 270)
(descr "9-pin D-Sub connector, solder-cups edge-mounted, male, x-pin-pitch 2.77mm, distance of mounting holes 25mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf")
(tags "9-pin D-Sub connector edge mount solder cup male x-pin-pitch 2.77mm mounting holes distance 25mm")
(path /3ECDE5C8)
(attr smd)
(fp_text reference J2 (at -9.463333 0 270) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value DB9MALE (at 0 -16.69 270) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -6.14 0.91) (end -6.14 -1.99) (layer B.Fab) (width 0.1))
(fp_line (start -6.14 -1.99) (end -4.94 -1.99) (layer B.Fab) (width 0.1))
(fp_line (start -4.94 -1.99) (end -4.94 0.91) (layer B.Fab) (width 0.1))
(fp_line (start -4.94 0.91) (end -6.14 0.91) (layer B.Fab) (width 0.1))
(fp_line (start -3.37 0.91) (end -3.37 -1.99) (layer B.Fab) (width 0.1))
(fp_line (start -3.37 -1.99) (end -2.17 -1.99) (layer B.Fab) (width 0.1))
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(fp_line (start 0.6 -1.99) (end 0.6 0.91) (layer B.Fab) (width 0.1))
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(fp_line (start -8.05 -1.5) (end -7 -1.5) (layer B.CrtYd) (width 0.05))
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(fp_line (start 6.723333 -1.74) (end 6.723333 2) (layer B.SilkS) (width 0.12))
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(fp_line (start -15.425 -1.99) (end 15.425 -1.99) (layer Dwgs.User) (width 0.05))
(fp_text user %R (at 0 -3.39 270) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text user "PCB edge" (at -10.425 -1.323333 270) (layer Dwgs.User)
(effects (font (size 0.5 0.5) (thickness 0.075)))
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(pad 1 smd rect (at -5.54 0 270) (size 1.846667 3.48) (layers Dessous B.Paste B.Mask)
(net 4 /PWR_3,3-5V))
(pad 2 smd rect (at -2.77 0 270) (size 1.846667 3.48) (layers Dessous B.Paste B.Mask)
(net 6 /TD0-DONE))
(pad 3 smd rect (at 0 0 270) (size 1.846667 3.48) (layers Dessous B.Paste B.Mask)
(net 8 /TDI-DIN))
(pad 4 smd rect (at 2.77 0 270) (size 1.846667 3.48) (layers Dessous B.Paste B.Mask)
(net 5 /TCK-CCLK))
(pad 5 smd rect (at 5.54 0 270) (size 1.846667 3.48) (layers Dessous B.Paste B.Mask)
(net 10 /TMS-PROG))
(pad 6 smd rect (at -4.155 0 270) (size 1.846667 3.48) (layers Dessus F.Paste F.Mask)
(net 13 GND))
(pad 7 smd rect (at -1.385 0 270) (size 1.846667 3.48) (layers Dessus F.Paste F.Mask)
(net 13 GND))
(pad 8 smd rect (at 1.385 0 270) (size 1.846667 3.48) (layers Dessus F.Paste F.Mask)
(net 13 GND))
(pad 9 smd rect (at 4.155 0 270) (size 1.846667 3.48) (layers Dessus F.Paste F.Mask)
(net 13 GND))
(model ${KISYS3DMOD}/Connector_Dsub.3dshapes/DSUB-9_Male_EdgeMount_P2.77mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Update demos
2018-01-11 13:21:58 +00:00
(module Connector_PinHeader_2.54mm:PinHeader_1x06_P2.54mm_Vertical (layer Dessus) (tedit 59FED5CC) (tstamp 5A583D55)
(at 169.672 80.137)
(descr "Through hole straight pin header, 1x06, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x06 2.54mm single row")
(path /3EBF830C)
(fp_text reference P1 (at 0 -2.33) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
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(effects (font (size 1 1) (thickness 0.15)))
)
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(fp_line (start 1.27 13.97) (end -1.27 13.97) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 13.97) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.33 14.03) (end 1.33 14.03) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 14.03) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 14.03) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.8 -1.8) (end -1.8 14.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 14.5) (end 1.8 14.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 14.5) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 6.35 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 4 /PWR_3,3-5V))
(pad 2 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 13 GND))
(pad 3 thru_hole oval (at 0 5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 6 /TD0-DONE))
(pad 4 thru_hole oval (at 0 7.62) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 8 /TDI-DIN))
(pad 5 thru_hole oval (at 0 10.16) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 5 /TCK-CCLK))
(pad 6 thru_hole oval (at 0 12.7) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 10 /TMS-PROG))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x06_P2.54mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Update demo
2018-01-10 15:41:40 +00:00
(module Capacitor_THT:C_Disc_D5.1mm_W3.2mm_P5.00mm (layer Dessus) (tedit 5A142A3B) (tstamp 5A59B9B3)
(at 140.97 102.87 270)
(descr "C, Disc series, Radial, pin pitch=5.00mm, diameter*width=5.1*3.2mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf")
(tags "C Disc series Radial pin pitch 5.00mm diameter 5.1mm width 3.2mm Capacitor")
(path /4D528085)
(fp_text reference C2 (at 2.5 -2.91 270) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 100pF (at 2.5 2.91 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 2.5 0 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 6.05 -1.95) (end -1.05 -1.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.05 1.95) (end 6.05 -1.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.95) (end 6.05 1.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.95) (end -1.05 1.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 5.11 0.996) (end 5.11 1.66) (layer F.SilkS) (width 0.12))
(fp_line (start 5.11 -1.66) (end 5.11 -0.996) (layer F.SilkS) (width 0.12))
(fp_line (start -0.11 0.996) (end -0.11 1.66) (layer F.SilkS) (width 0.12))
(fp_line (start -0.11 -1.66) (end -0.11 -0.996) (layer F.SilkS) (width 0.12))
(fp_line (start -0.11 1.66) (end 5.11 1.66) (layer F.SilkS) (width 0.12))
(fp_line (start -0.11 -1.66) (end 5.11 -1.66) (layer F.SilkS) (width 0.12))
(fp_line (start 5.05 -1.6) (end -0.05 -1.6) (layer F.Fab) (width 0.1))
(fp_line (start 5.05 1.6) (end 5.05 -1.6) (layer F.Fab) (width 0.1))
(fp_line (start -0.05 1.6) (end 5.05 1.6) (layer F.Fab) (width 0.1))
(fp_line (start -0.05 -1.6) (end -0.05 1.6) (layer F.Fab) (width 0.1))
(pad 2 thru_hole circle (at 5 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update demos. Fix pspice netlist issues when using ( and ) in net names ( parenthesis are replaced by underscore) .
2014-01-07 19:42:34 +00:00
(net 13 GND))
Update demo
2018-01-10 15:41:40 +00:00
(pad 1 thru_hole circle (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 23 "Net-(C2-Pad1)"))
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Disc_D5.1mm_W3.2mm_P5.00mm.wrl
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Update demo
2018-01-10 15:41:40 +00:00
(module Capacitor_THT:C_Disc_D5.1mm_W3.2mm_P5.00mm (layer Dessus) (tedit 5A142A3B) (tstamp 5A59B99F)
(at 151.13 69.85)
(descr "C, Disc series, Radial, pin pitch=5.00mm, diameter*width=5.1*3.2mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf")
(tags "C Disc series Radial pin pitch 5.00mm diameter 5.1mm width 3.2mm Capacitor")
(path /4D528084)
(fp_text reference C3 (at 2.5 -2.91) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 100pF (at 2.5 2.91) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.05 -1.6) (end -0.05 1.6) (layer F.Fab) (width 0.1))
(fp_line (start -0.05 1.6) (end 5.05 1.6) (layer F.Fab) (width 0.1))
(fp_line (start 5.05 1.6) (end 5.05 -1.6) (layer F.Fab) (width 0.1))
(fp_line (start 5.05 -1.6) (end -0.05 -1.6) (layer F.Fab) (width 0.1))
(fp_line (start -0.11 -1.66) (end 5.11 -1.66) (layer F.SilkS) (width 0.12))
(fp_line (start -0.11 1.66) (end 5.11 1.66) (layer F.SilkS) (width 0.12))
(fp_line (start -0.11 -1.66) (end -0.11 -0.996) (layer F.SilkS) (width 0.12))
(fp_line (start -0.11 0.996) (end -0.11 1.66) (layer F.SilkS) (width 0.12))
(fp_line (start 5.11 -1.66) (end 5.11 -0.996) (layer F.SilkS) (width 0.12))
(fp_line (start 5.11 0.996) (end 5.11 1.66) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.95) (end -1.05 1.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.95) (end 6.05 1.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.05 1.95) (end 6.05 -1.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.05 -1.95) (end -1.05 -1.95) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 2.5 0) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 15 "Net-(C3-Pad1)"))
(pad 2 thru_hole circle (at 5 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 13 GND))
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Disc_D5.1mm_W3.2mm_P5.00mm.wrl
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(at (xyz 0 0 0))
Update demo
2018-01-10 15:41:40 +00:00
(scale (xyz 1 1 1))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(rotate (xyz 0 0 0))
)
)
Update demo
2018-01-10 15:41:40 +00:00
(module Capacitor_THT:C_Disc_D5.1mm_W3.2mm_P5.00mm (layer Dessus) (tedit 5A142A3B) (tstamp 5A59B98B)
Update demos
2018-02-01 12:25:56 +00:00
(at 149 102.87 270)
Update demo
2018-01-10 15:41:40 +00:00
(descr "C, Disc series, Radial, pin pitch=5.00mm, diameter*width=5.1*3.2mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf")
(tags "C Disc series Radial pin pitch 5.00mm diameter 5.1mm width 3.2mm Capacitor")
(path /3EBF81A7)
(fp_text reference C4 (at 2.5 -2.91 270) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 100pF (at 2.5 2.91 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 2.5 0 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 6.05 -1.95) (end -1.05 -1.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.05 1.95) (end 6.05 -1.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.95) (end 6.05 1.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.95) (end -1.05 1.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 5.11 0.996) (end 5.11 1.66) (layer F.SilkS) (width 0.12))
(fp_line (start 5.11 -1.66) (end 5.11 -0.996) (layer F.SilkS) (width 0.12))
(fp_line (start -0.11 0.996) (end -0.11 1.66) (layer F.SilkS) (width 0.12))
(fp_line (start -0.11 -1.66) (end -0.11 -0.996) (layer F.SilkS) (width 0.12))
(fp_line (start -0.11 1.66) (end 5.11 1.66) (layer F.SilkS) (width 0.12))
(fp_line (start -0.11 -1.66) (end 5.11 -1.66) (layer F.SilkS) (width 0.12))
(fp_line (start 5.05 -1.6) (end -0.05 -1.6) (layer F.Fab) (width 0.1))
(fp_line (start 5.05 1.6) (end 5.05 -1.6) (layer F.Fab) (width 0.1))
(fp_line (start -0.05 1.6) (end 5.05 1.6) (layer F.Fab) (width 0.1))
(fp_line (start -0.05 -1.6) (end -0.05 1.6) (layer F.Fab) (width 0.1))
(pad 2 thru_hole circle (at 5 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 13 GND))
(pad 1 thru_hole circle (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 26 "Net-(C4-Pad1)"))
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Disc_D5.1mm_W3.2mm_P5.00mm.wrl
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(at (xyz 0 0 0))
Update demo
2018-01-10 15:41:40 +00:00
(scale (xyz 1 1 1))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(rotate (xyz 0 0 0))
)
)
Update demo
2018-01-10 15:41:40 +00:00
(module Capacitor_THT:C_Disc_D5.1mm_W3.2mm_P5.00mm (layer Dessus) (tedit 5A142A3B) (tstamp 5A59B977)
Update demos
2018-02-01 12:25:56 +00:00
(at 145 102.87 270)
Update demo
2018-01-10 15:41:40 +00:00
(descr "C, Disc series, Radial, pin pitch=5.00mm, diameter*width=5.1*3.2mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf")
(tags "C Disc series Radial pin pitch 5.00mm diameter 5.1mm width 3.2mm Capacitor")
(path /4D528086)
(fp_text reference C5 (at 2.5 -2.91 270) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 100pF (at 2.5 2.91 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.05 -1.6) (end -0.05 1.6) (layer F.Fab) (width 0.1))
(fp_line (start -0.05 1.6) (end 5.05 1.6) (layer F.Fab) (width 0.1))
(fp_line (start 5.05 1.6) (end 5.05 -1.6) (layer F.Fab) (width 0.1))
(fp_line (start 5.05 -1.6) (end -0.05 -1.6) (layer F.Fab) (width 0.1))
(fp_line (start -0.11 -1.66) (end 5.11 -1.66) (layer F.SilkS) (width 0.12))
(fp_line (start -0.11 1.66) (end 5.11 1.66) (layer F.SilkS) (width 0.12))
(fp_line (start -0.11 -1.66) (end -0.11 -0.996) (layer F.SilkS) (width 0.12))
(fp_line (start -0.11 0.996) (end -0.11 1.66) (layer F.SilkS) (width 0.12))
(fp_line (start 5.11 -1.66) (end 5.11 -0.996) (layer F.SilkS) (width 0.12))
(fp_line (start 5.11 0.996) (end 5.11 1.66) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.95) (end -1.05 1.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.95) (end 6.05 1.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.05 1.95) (end 6.05 -1.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.05 -1.95) (end -1.05 -1.95) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 2.5 0 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole circle (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 24 "Net-(C5-Pad1)"))
(pad 2 thru_hole circle (at 5 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 13 GND))
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Disc_D5.1mm_W3.2mm_P5.00mm.wrl
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(at (xyz 0 0 0))
Update demo
2018-01-10 15:41:40 +00:00
(scale (xyz 1 1 1))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(rotate (xyz 0 0 0))
)
)
Update demo
2018-01-10 15:41:40 +00:00
(module Package_DIP:DIP-14_W7.62mm_LongPads (layer Dessus) (tedit 5A02E8C5) (tstamp 5A58F5AD)
(at 127 82.55)
(descr "14-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads")
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads")
(path /3EBF7DBD)
(fp_text reference U1 (at 3.81 -2.33) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 74LS125 (at 3.81 17.57) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 3.81 7.62) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 9.1 -1.55) (end -1.45 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.1 16.8) (end 9.1 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.45 16.8) (end 9.1 16.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.45 -1.55) (end -1.45 16.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.06 -1.33) (end 4.81 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 6.06 16.57) (end 6.06 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.56 16.57) (end 6.06 16.57) (layer F.SilkS) (width 0.12))
(fp_line (start 1.56 -1.33) (end 1.56 16.57) (layer F.SilkS) (width 0.12))
(fp_line (start 2.81 -1.33) (end 1.56 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 0.635 -0.27) (end 1.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 16.51) (end 0.635 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 16.51) (end 0.635 16.51) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 -1.27) (end 6.985 16.51) (layer F.Fab) (width 0.1))
(fp_line (start 1.635 -1.27) (end 6.985 -1.27) (layer F.Fab) (width 0.1))
(fp_arc (start 3.81 -1.33) (end 2.81 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
(pad 14 thru_hole oval (at 7.62 0) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 14 VCC))
(pad 7 thru_hole oval (at 0 15.24) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update demos. Fix pspice netlist issues when using ( and ) in net names ( parenthesis are replaced by underscore) .
2014-01-07 19:42:34 +00:00
(net 13 GND))
Update demo
2018-01-10 15:41:40 +00:00
(pad 13 thru_hole oval (at 7.62 2.54) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 21 "Net-(R8-Pad1)"))
(pad 6 thru_hole oval (at 0 12.7) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 23 "Net-(C2-Pad1)"))
(pad 12 thru_hole oval (at 7.62 5.08) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 27 "Net-(R9-Pad1)"))
(pad 5 thru_hole oval (at 0 10.16) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 22 "Net-(R7-Pad1)"))
(pad 11 thru_hole oval (at 7.62 7.62) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 26 "Net-(C4-Pad1)"))
(pad 4 thru_hole oval (at 0 7.62) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 21 "Net-(R8-Pad1)"))
(pad 10 thru_hole oval (at 7.62 10.16) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 21 "Net-(R8-Pad1)"))
(pad 3 thru_hole oval (at 0 5.08) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 15 "Net-(C3-Pad1)"))
(pad 9 thru_hole oval (at 7.62 12.7) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 25 "Net-(R10-Pad1)"))
(pad 2 thru_hole oval (at 0 2.54) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 13 GND))
(pad 8 thru_hole oval (at 7.62 15.24) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 24 "Net-(C5-Pad1)"))
(pad 1 thru_hole rect (at 0 0) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 20 "Net-(R6-Pad1)"))
(model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-14_W7.62mm.wrl
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(at (xyz 0 0 0))
Update demo
2018-01-10 15:41:40 +00:00
(scale (xyz 1 1 1))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(rotate (xyz 0 0 0))
)
)
Update demo
2018-01-10 15:41:40 +00:00
(module Package_DIP:DIP-14_W7.62mm_LongPads (layer Dessus) (tedit 5A02E8C5) (tstamp 5A58F58C)
(at 140.97 82.55)
(descr "14-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads")
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads")
(path /3EBF7EEC)
(fp_text reference U2 (at 3.81 -2.33) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 74LS125 (at 3.81 17.57) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_arc (start 3.81 -1.33) (end 2.81 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
(fp_line (start 1.635 -1.27) (end 6.985 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 -1.27) (end 6.985 16.51) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 16.51) (end 0.635 16.51) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 16.51) (end 0.635 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 -0.27) (end 1.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 2.81 -1.33) (end 1.56 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.56 -1.33) (end 1.56 16.57) (layer F.SilkS) (width 0.12))
(fp_line (start 1.56 16.57) (end 6.06 16.57) (layer F.SilkS) (width 0.12))
(fp_line (start 6.06 16.57) (end 6.06 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 6.06 -1.33) (end 4.81 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.45 -1.55) (end -1.45 16.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.45 16.8) (end 9.1 16.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.1 16.8) (end 9.1 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.1 -1.55) (end -1.45 -1.55) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 3.81 7.62) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 13 GND))
(pad 8 thru_hole oval (at 7.62 15.24) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 18 "Net-(U2-Pad8)"))
(pad 2 thru_hole oval (at 0 2.54) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 15 "Net-(C3-Pad1)"))
(pad 9 thru_hole oval (at 7.62 12.7) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 13 GND))
(pad 3 thru_hole oval (at 0 5.08) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 16 "Net-(R4-Pad1)"))
(pad 10 thru_hole oval (at 7.62 10.16) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 13 GND))
(pad 4 thru_hole oval (at 0 7.62) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 13 GND))
(pad 11 thru_hole oval (at 7.62 7.62) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 19 "Net-(U2-Pad11)"))
(pad 5 thru_hole oval (at 0 10.16) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 13 GND))
(pad 12 thru_hole oval (at 7.62 5.08) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 13 GND))
(pad 6 thru_hole oval (at 0 12.7) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 17 "Net-(U2-Pad6)"))
(pad 13 thru_hole oval (at 7.62 2.54) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 13 GND))
(pad 7 thru_hole oval (at 0 15.24) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 13 GND))
(pad 14 thru_hole oval (at 7.62 0) (size 2.4 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 14 VCC))
(model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-14_W7.62mm.wrl
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(at (xyz 0 0 0))
Update demo
2018-01-10 15:41:40 +00:00
(scale (xyz 1 1 1))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(rotate (xyz 0 0 0))
)
)
Update demo
2018-01-10 15:41:40 +00:00
(module Capacitor_THT:C_Axial_L5.1mm_D3.1mm_P12.50mm_Horizontal (layer Dessus) (tedit 5A142A3B) (tstamp 5A5834A9)
(at 134.62 76.2)
(descr "C, Axial series, Axial, Horizontal, pin pitch=12.5mm, http://www.vishay.com/docs/45231/arseries.pdf")
(tags "C Axial series Axial Horizontal pin pitch 12.5mm length 5.1mm diameter 3.1mm")
(path /3EBF82C6)
(fp_text reference C1 (at 6.25 -2.61) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1uF (at 6.25 2.61) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 3.7 -1.55) (end 3.7 1.55) (layer F.Fab) (width 0.1))
(fp_line (start 3.7 1.55) (end 8.8 1.55) (layer F.Fab) (width 0.1))
(fp_line (start 8.8 1.55) (end 8.8 -1.55) (layer F.Fab) (width 0.1))
(fp_line (start 8.8 -1.55) (end 3.7 -1.55) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 3.7 0) (layer F.Fab) (width 0.1))
(fp_line (start 12.5 0) (end 8.8 0) (layer F.Fab) (width 0.1))
(fp_line (start 3.64 -1.61) (end 3.64 1.61) (layer F.SilkS) (width 0.12))
(fp_line (start 3.64 1.61) (end 8.86 1.61) (layer F.SilkS) (width 0.12))
(fp_line (start 8.86 1.61) (end 8.86 -1.61) (layer F.SilkS) (width 0.12))
(fp_line (start 8.86 -1.61) (end 3.64 -1.61) (layer F.SilkS) (width 0.12))
(fp_line (start 0.98 0) (end 3.64 0) (layer F.SilkS) (width 0.12))
(fp_line (start 11.52 0) (end 8.86 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.9) (end -1.05 1.9) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.9) (end 13.55 1.9) (layer F.CrtYd) (width 0.05))
(fp_line (start 13.55 1.9) (end 13.55 -1.9) (layer F.CrtYd) (width 0.05))
(fp_line (start 13.55 -1.9) (end -1.05 -1.9) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 6.25 0) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 14 VCC))
(pad 2 thru_hole oval (at 12.5 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 13 GND))
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Axial_L5.1mm_D3.1mm_P12.50mm_Horizontal.wrl
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(at (xyz 0 0 0))
Update demo
2018-01-10 15:41:40 +00:00
(scale (xyz 1 1 1))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(rotate (xyz 0 0 0))
)
)
Update demo
2018-01-10 15:41:40 +00:00
(module Diode_THT:D_A-405_P7.62mm_Horizontal (layer Dessus) (tedit 5A195B5A) (tstamp 5A56D054)
(at 134.62 72.39 180)
(descr "D, A-405 series, Axial, Horizontal, pin pitch=7.62mm, , length*diameter=5.2*2.7mm^2, , http://www.diodes.com/_files/packages/A-405.pdf")
(tags "D A-405 series Axial Horizontal pin pitch 7.62mm length 5.2mm diameter 2.7mm")
(path /3EBF815E)
(fp_text reference D1 (at 3.81 -2.47 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value BAT46 (at 3.81 2.47 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user K (at 0 -1.9 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user K (at 0 -1.9 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 4.2 0 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 8.8 -1.75) (end -1.15 -1.75) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.8 1.75) (end 8.8 -1.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.15 1.75) (end 8.8 1.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.15 -1.75) (end -1.15 1.75) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.87 -1.47) (end 1.87 1.47) (layer F.SilkS) (width 0.12))
(fp_line (start 2.11 -1.47) (end 2.11 1.47) (layer F.SilkS) (width 0.12))
(fp_line (start 1.99 -1.47) (end 1.99 1.47) (layer F.SilkS) (width 0.12))
(fp_line (start 6.53 1.47) (end 6.53 1.14) (layer F.SilkS) (width 0.12))
(fp_line (start 1.09 1.47) (end 6.53 1.47) (layer F.SilkS) (width 0.12))
(fp_line (start 1.09 1.14) (end 1.09 1.47) (layer F.SilkS) (width 0.12))
(fp_line (start 6.53 -1.47) (end 6.53 -1.14) (layer F.SilkS) (width 0.12))
(fp_line (start 1.09 -1.47) (end 6.53 -1.47) (layer F.SilkS) (width 0.12))
(fp_line (start 1.09 -1.14) (end 1.09 -1.47) (layer F.SilkS) (width 0.12))
(fp_line (start 1.89 -1.35) (end 1.89 1.35) (layer F.Fab) (width 0.1))
(fp_line (start 2.09 -1.35) (end 2.09 1.35) (layer F.Fab) (width 0.1))
(fp_line (start 1.99 -1.35) (end 1.99 1.35) (layer F.Fab) (width 0.1))
(fp_line (start 7.62 0) (end 6.41 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.21 0) (layer F.Fab) (width 0.1))
(fp_line (start 6.41 -1.35) (end 1.21 -1.35) (layer F.Fab) (width 0.1))
(fp_line (start 6.41 1.35) (end 6.41 -1.35) (layer F.Fab) (width 0.1))
(fp_line (start 1.21 1.35) (end 6.41 1.35) (layer F.Fab) (width 0.1))
(fp_line (start 1.21 -1.35) (end 1.21 1.35) (layer F.Fab) (width 0.1))
(pad 2 thru_hole oval (at 7.62 0 180) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
(net 28 "Net-(D1-Pad2)"))
(pad 1 thru_hole rect (at 0 0 180) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
(net 14 VCC))
(model ${KISYS3DMOD}/Diode_THT.3dshapes/D_A-405_P7.62mm_Horizontal.wrl
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(at (xyz 0 0 0))
Update demo
2018-01-10 15:41:40 +00:00
(scale (xyz 1 1 1))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(rotate (xyz 0 0 0))
)
)
Update demo
2018-01-10 15:41:40 +00:00
(module Diode_THT:D_A-405_P7.62mm_Horizontal (layer Dessus) (tedit 5A195B5A) (tstamp 5A56D036)
(at 160.02 78.74 180)
(descr "D, A-405 series, Axial, Horizontal, pin pitch=7.62mm, , length*diameter=5.2*2.7mm^2, , http://www.diodes.com/_files/packages/A-405.pdf")
(tags "D A-405 series Axial Horizontal pin pitch 7.62mm length 5.2mm diameter 2.7mm")
(path /3EBF8176)
(fp_text reference D2 (at 3.81 -2.47 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value BAT46 (at 3.81 2.47 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.21 -1.35) (end 1.21 1.35) (layer F.Fab) (width 0.1))
(fp_line (start 1.21 1.35) (end 6.41 1.35) (layer F.Fab) (width 0.1))
(fp_line (start 6.41 1.35) (end 6.41 -1.35) (layer F.Fab) (width 0.1))
(fp_line (start 6.41 -1.35) (end 1.21 -1.35) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.21 0) (layer F.Fab) (width 0.1))
(fp_line (start 7.62 0) (end 6.41 0) (layer F.Fab) (width 0.1))
(fp_line (start 1.99 -1.35) (end 1.99 1.35) (layer F.Fab) (width 0.1))
(fp_line (start 2.09 -1.35) (end 2.09 1.35) (layer F.Fab) (width 0.1))
(fp_line (start 1.89 -1.35) (end 1.89 1.35) (layer F.Fab) (width 0.1))
(fp_line (start 1.09 -1.14) (end 1.09 -1.47) (layer F.SilkS) (width 0.12))
(fp_line (start 1.09 -1.47) (end 6.53 -1.47) (layer F.SilkS) (width 0.12))
(fp_line (start 6.53 -1.47) (end 6.53 -1.14) (layer F.SilkS) (width 0.12))
(fp_line (start 1.09 1.14) (end 1.09 1.47) (layer F.SilkS) (width 0.12))
(fp_line (start 1.09 1.47) (end 6.53 1.47) (layer F.SilkS) (width 0.12))
(fp_line (start 6.53 1.47) (end 6.53 1.14) (layer F.SilkS) (width 0.12))
(fp_line (start 1.99 -1.47) (end 1.99 1.47) (layer F.SilkS) (width 0.12))
(fp_line (start 2.11 -1.47) (end 2.11 1.47) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 -1.47) (end 1.87 1.47) (layer F.SilkS) (width 0.12))
(fp_line (start -1.15 -1.75) (end -1.15 1.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.15 1.75) (end 8.8 1.75) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.8 1.75) (end 8.8 -1.75) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.8 -1.75) (end -1.15 -1.75) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 4.2 0 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user K (at 0 -1.9 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user K (at 0 -1.9 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0 180) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
(net 4 /PWR_3,3-5V))
(pad 2 thru_hole oval (at 7.62 0 180) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
(net 14 VCC))
(model ${KISYS3DMOD}/Diode_THT.3dshapes/D_A-405_P7.62mm_Horizontal.wrl
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(at (xyz 0 0 0))
Update demo
2018-01-10 15:41:40 +00:00
(scale (xyz 1 1 1))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(rotate (xyz 0 0 0))
)
)
Update demo
2018-01-10 15:41:40 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer Dessus) (tedit 5A14249F) (tstamp 5A56CFDE)
Update demos
2018-02-01 12:25:56 +00:00
(at 121.92 77.216 180)
Update demo
2018-01-10 15:41:40 +00:00
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(path /3EBF7D31)
Update demo
2018-01-10 15:41:40 +00:00
(fp_text reference R10 (at 5.08 -2.31 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 100 (at 5.08 2.31 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 5.08 0 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 1.87 -1.31) (end 1.87 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 1.31) (end 8.29 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 1.31) (end 8.29 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 -1.31) (end 1.87 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 0.98 0) (end 1.87 0) (layer F.SilkS) (width 0.12))
(fp_line (start 9.18 0) (end 8.29 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.6) (end -1.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.6) (end 11.25 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.25 1.6) (end 11.25 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.25 -1.6) (end -1.05 -1.6) (layer F.CrtYd) (width 0.05))
(pad 1 thru_hole circle (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 25 "Net-(R10-Pad1)"))
(pad 2 thru_hole oval (at 10.16 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update demos. Fix pspice netlist issues when using ( and ) in net names ( parenthesis are replaced by underscore) .
2014-01-07 19:42:34 +00:00
(net 1 /CLK-D1))
Update demo
2018-01-10 15:41:40 +00:00
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(at (xyz 0 0 0))
Update demo
2018-01-10 15:41:40 +00:00
(scale (xyz 1 1 1))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(rotate (xyz 0 0 0))
)
)
Update demo
2018-01-10 15:41:40 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer Dessus) (tedit 5A14249F) (tstamp 5A56CFC8)
(at 151.13 73.66)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /3EBF818E)
(fp_text reference R5 (at 5.08 -2.31) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1K (at 5.08 2.31) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 11.25 -1.6) (end -1.05 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.25 1.6) (end 11.25 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.6) (end 11.25 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.6) (end -1.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.18 0) (end 8.29 0) (layer F.SilkS) (width 0.12))
(fp_line (start 0.98 0) (end 1.87 0) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 -1.31) (end 1.87 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 1.31) (end 8.29 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 1.31) (end 8.29 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 -1.31) (end 1.87 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
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(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_text user %R (at 5.08 0) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 2 thru_hole oval (at 10.16 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 13 GND))
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 14 VCC))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(at (xyz 0 0 0))
Update demo
2018-01-10 15:41:40 +00:00
(scale (xyz 1 1 1))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(rotate (xyz 0 0 0))
)
)
Update demo
2018-01-10 15:41:40 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer Dessus) (tedit 5A14249F) (tstamp 5A56D255)
Update demos
2018-02-01 12:25:56 +00:00
(at 121.92 73.8632 180)
Update demo
2018-01-10 15:41:40 +00:00
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /3EBF7D16)
(fp_text reference R1 (at 5.08 -2.31 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 100 (at 5.08 2.31 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 5.08 0 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 1.87 -1.31) (end 1.87 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 1.31) (end 8.29 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 1.31) (end 8.29 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 -1.31) (end 1.87 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 0.98 0) (end 1.87 0) (layer F.SilkS) (width 0.12))
(fp_line (start 9.18 0) (end 8.29 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.6) (end -1.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.6) (end 11.25 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.25 1.6) (end 11.25 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.25 -1.6) (end -1.05 -1.6) (layer F.CrtYd) (width 0.05))
(pad 1 thru_hole circle (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 28 "Net-(D1-Pad2)"))
(pad 2 thru_hole oval (at 10.16 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 12 /VCC_SENSE-ERROR*))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(at (xyz 0 0 0))
Update demo
2018-01-10 15:41:40 +00:00
(scale (xyz 1 1 1))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(rotate (xyz 0 0 0))
)
)
Update demo
2018-01-10 15:41:40 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer Dessus) (tedit 5A14249F) (tstamp 5A56CF9C)
(at 137.16 72.39)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /3EBF8187)
(fp_text reference R2 (at 5.08 -2.31) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 5,1K (at 5.08 2.31) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 11.25 -1.6) (end -1.05 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.25 1.6) (end 11.25 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.6) (end 11.25 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.6) (end -1.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.18 0) (end 8.29 0) (layer F.SilkS) (width 0.12))
(fp_line (start 0.98 0) (end 1.87 0) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 -1.31) (end 1.87 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 1.31) (end 8.29 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 1.31) (end 8.29 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 -1.31) (end 1.87 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_text user %R (at 5.08 0) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 2 thru_hole oval (at 10.16 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 15 "Net-(C3-Pad1)"))
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 14 VCC))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(at (xyz 0 0 0))
Update demo
2018-01-10 15:41:40 +00:00
(scale (xyz 1 1 1))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(rotate (xyz 0 0 0))
)
)
Update demo
2018-01-10 15:41:40 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer Dessus) (tedit 5A14249F) (tstamp 5A56CF86)
(at 121.9327 83.82 180)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /3EBF7D26)
(fp_text reference R6 (at 5.08 -2.31 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 100 (at 5.08 2.31 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 5.08 0 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 1.87 -1.31) (end 1.87 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 1.31) (end 8.29 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 1.31) (end 8.29 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 -1.31) (end 1.87 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 0.98 0) (end 1.87 0) (layer F.SilkS) (width 0.12))
(fp_line (start 9.18 0) (end 8.29 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.6) (end -1.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.6) (end 11.25 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.25 1.6) (end 11.25 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.25 -1.6) (end -1.05 -1.6) (layer F.CrtYd) (width 0.05))
(pad 1 thru_hole circle (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 20 "Net-(R6-Pad1)"))
(pad 2 thru_hole oval (at 10.16 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 7 /TD0-PROG-D4))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(at (xyz 0 0 0))
Update demo
2018-01-10 15:41:40 +00:00
(scale (xyz 1 1 1))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(rotate (xyz 0 0 0))
)
)
Update demo
2018-01-10 15:41:40 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer Dessus) (tedit 5A14249F) (tstamp 5A56CF70)
(at 121.92 92.71 180)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /4D52807F)
(fp_text reference R7 (at 5.08 -2.31 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 100 (at 5.08 2.31 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 11.25 -1.6) (end -1.05 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.25 1.6) (end 11.25 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.6) (end 11.25 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.6) (end -1.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.18 0) (end 8.29 0) (layer F.SilkS) (width 0.12))
(fp_line (start 0.98 0) (end 1.87 0) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 -1.31) (end 1.87 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 1.31) (end 8.29 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 1.31) (end 8.29 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 -1.31) (end 1.87 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_text user %R (at 5.08 0 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 2 thru_hole oval (at 10.16 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 9 /TDI-DIN-D0))
(pad 1 thru_hole circle (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 22 "Net-(R7-Pad1)"))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(at (xyz 0 0 0))
Update demo
2018-01-10 15:41:40 +00:00
(scale (xyz 1 1 1))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(rotate (xyz 0 0 0))
)
)
Update demo
2018-01-10 15:41:40 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer Dessus) (tedit 5A14249F) (tstamp 5A56CF5A)
Update demos
2018-02-01 12:25:56 +00:00
(at 121.92 87.63 180)
Update demo
2018-01-10 15:41:40 +00:00
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /4D528080)
(fp_text reference R8 (at 5.08 -2.31 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 100 (at 5.08 2.31 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 5.08 0 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 1.87 -1.31) (end 1.87 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 1.31) (end 8.29 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 1.31) (end 8.29 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 -1.31) (end 1.87 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 0.98 0) (end 1.87 0) (layer F.SilkS) (width 0.12))
(fp_line (start 9.18 0) (end 8.29 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.6) (end -1.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.6) (end 11.25 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.25 1.6) (end 11.25 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.25 -1.6) (end -1.05 -1.6) (layer F.CrtYd) (width 0.05))
(pad 1 thru_hole circle (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 21 "Net-(R8-Pad1)"))
(pad 2 thru_hole oval (at 10.16 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 2 /CTRL-D3))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(at (xyz 0 0 0))
Update demo
2018-01-10 15:41:40 +00:00
(scale (xyz 1 1 1))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(rotate (xyz 0 0 0))
)
)
Update demo
2018-01-10 15:41:40 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer Dessus) (tedit 5A14249F) (tstamp 5A56CF44)
(at 162.56 93.98 180)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /4D527316)
(fp_text reference R11 (at 5.08 -2.31 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 100 (at 5.08 2.31 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 11.25 -1.6) (end -1.05 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.25 1.6) (end 11.25 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.6) (end 11.25 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.6) (end -1.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.18 0) (end 8.29 0) (layer F.SilkS) (width 0.12))
(fp_line (start 0.98 0) (end 1.87 0) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 -1.31) (end 1.87 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 1.31) (end 8.29 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 1.31) (end 8.29 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 -1.31) (end 1.87 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_text user %R (at 5.08 0 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 2 thru_hole oval (at 10.16 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 23 "Net-(C2-Pad1)"))
(pad 1 thru_hole circle (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 8 /TDI-DIN))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(at (xyz 0 0 0))
Update demo
2018-01-10 15:41:40 +00:00
(scale (xyz 1 1 1))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(rotate (xyz 0 0 0))
)
)
Update demo
2018-01-10 15:41:40 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer Dessus) (tedit 5A14249F) (tstamp 5A56CF2E)
(at 162.56 99.06 180)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /4D528083)
(fp_text reference R12 (at 5.08 -2.31 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 100 (at 5.08 2.31 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 5.08 0 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 1.87 -1.31) (end 1.87 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 1.31) (end 8.29 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 1.31) (end 8.29 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 -1.31) (end 1.87 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 0.98 0) (end 1.87 0) (layer F.SilkS) (width 0.12))
(fp_line (start 9.18 0) (end 8.29 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.6) (end -1.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.6) (end 11.25 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.25 1.6) (end 11.25 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.25 -1.6) (end -1.05 -1.6) (layer F.CrtYd) (width 0.05))
(pad 1 thru_hole circle (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 5 /TCK-CCLK))
(pad 2 thru_hole oval (at 10.16 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 24 "Net-(C5-Pad1)"))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Update demo
2018-01-10 15:41:40 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer Dessus) (tedit 5A14249F) (tstamp 5A56CF18)
(at 162.56 105.41 180)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /4D528082)
(fp_text reference R13 (at 5.08 -2.31 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 100 (at 5.08 2.31 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 11.25 -1.6) (end -1.05 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.25 1.6) (end 11.25 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.6) (end 11.25 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.6) (end -1.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.18 0) (end 8.29 0) (layer F.SilkS) (width 0.12))
(fp_line (start 0.98 0) (end 1.87 0) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 -1.31) (end 1.87 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 1.31) (end 8.29 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 1.31) (end 8.29 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 -1.31) (end 1.87 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_text user %R (at 5.08 0 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 2 thru_hole oval (at 10.16 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 26 "Net-(C4-Pad1)"))
(pad 1 thru_hole circle (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 10 /TMS-PROG))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Update demo
2018-01-10 15:41:40 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer Dessus) (tedit 5A14249F) (tstamp 5A56CF02)
(at 121.92 104.14 180)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /3EBF7D22)
(fp_text reference R4 (at 5.08 -2.31 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 47 (at 5.08 2.31 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 5.08 0 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 1.87 -1.31) (end 1.87 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 1.31) (end 8.29 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 1.31) (end 8.29 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 -1.31) (end 1.87 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 0.98 0) (end 1.87 0) (layer F.SilkS) (width 0.12))
(fp_line (start 9.18 0) (end 8.29 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.6) (end -1.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.6) (end 11.25 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.25 1.6) (end 11.25 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.25 -1.6) (end -1.05 -1.6) (layer F.CrtYd) (width 0.05))
(pad 1 thru_hole circle (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 16 "Net-(R4-Pad1)"))
(pad 2 thru_hole oval (at 10.16 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 3 /DONE-SELECT*))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Update demo
2018-01-10 15:41:40 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer Dessus) (tedit 5A14249F) (tstamp 5A56CEEC)
Update demos
2018-02-01 12:25:56 +00:00
(at 121.92 80.518 180)
Update demo
2018-01-10 15:41:40 +00:00
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /3EBF7D33)
(fp_text reference R9 (at 5.08 -2.31 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 100 (at 5.08 2.31 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 11.25 -1.6) (end -1.05 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.25 1.6) (end 11.25 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.6) (end 11.25 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.6) (end -1.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.18 0) (end 8.29 0) (layer F.SilkS) (width 0.12))
(fp_line (start 0.98 0) (end 1.87 0) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 -1.31) (end 1.87 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 1.31) (end 8.29 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 1.31) (end 8.29 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 -1.31) (end 1.87 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_text user %R (at 5.08 0 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 2 thru_hole oval (at 10.16 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 11 /TMS-PROG-D2))
(pad 1 thru_hole circle (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 27 "Net-(R9-Pad1)"))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Update demo
2018-01-10 15:41:40 +00:00
(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal (layer Dessus) (tedit 5A14249F) (tstamp 5A56CED6)
(at 162.56 88.9 180)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /3EBF819B)
(fp_text reference R14 (at 5.08 -2.31 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 100 (at 5.08 2.31 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 5.08 0 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1))
(fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1))
(fp_line (start 1.87 -1.31) (end 1.87 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 1.87 1.31) (end 8.29 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 1.31) (end 8.29 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 8.29 -1.31) (end 1.87 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 0.98 0) (end 1.87 0) (layer F.SilkS) (width 0.12))
(fp_line (start 9.18 0) (end 8.29 0) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.6) (end -1.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.6) (end 11.25 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.25 1.6) (end 11.25 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.25 -1.6) (end -1.05 -1.6) (layer F.CrtYd) (width 0.05))
(pad 1 thru_hole circle (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 6 /TD0-DONE))
(pad 2 thru_hole oval (at 10.16 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 15 "Net-(C3-Pad1)"))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Update demos. Fix pspice netlist issues when using ( and ) in net names ( parenthesis are replaced by underscore) .
2014-01-07 19:42:34 +00:00
(gr_line (start 184.15 83.185) (end 184.15 97.79) (angle 90) (layer Edge.Cuts) (width 0.1))
(gr_line (start 102.87 71.12) (end 102.87 106.68) (angle 90) (layer Edge.Cuts) (width 0.1))
(dimension 81.28 (width 0.3048) (layer Dwgs.User)
Update demos
2018-02-01 12:25:56 +00:00
(gr_text "3.2000 " (at 143.149793 114.033596) (layer Dwgs.User) (tstamp 5A7306E8)
Update demo
2018-01-10 15:41:40 +00:00
(effects (font (size 1.524 1.524) (thickness 0.3048)))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
)
Update demos
2018-02-01 12:25:56 +00:00
(feature1 (pts (xy 184.043793 110.350596) (xy 184.043793 118.173796)))
(feature2 (pts (xy 102.763793 110.350596) (xy 102.763793 118.173796)))
(crossbar (pts (xy 102.763793 115.430596) (xy 184.043793 115.430596)))
(arrow1a (pts (xy 184.043793 115.430596) (xy 182.918573 116.014796)))
(arrow1b (pts (xy 184.043793 115.430596) (xy 182.918573 114.846396)))
(arrow2a (pts (xy 102.763793 115.430596) (xy 103.889013 116.014796)))
(arrow2b (pts (xy 102.763793 115.430596) (xy 103.889013 114.846396)))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
)
Update demos. Fix pspice netlist issues when using ( and ) in net names ( parenthesis are replaced by underscore) .
2014-01-07 19:42:34 +00:00
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1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
(gr_text TMS-PROG (at 158.115 102.235) (layer Dessus)
Update demo
2018-01-10 15:41:40 +00:00
(effects (font (size 1.524 1.524) (thickness 0.381)))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
)
(gr_text TCK-CCL (at 158.115 96.52) (layer Dessus)
Update demo
2018-01-10 15:41:40 +00:00
(effects (font (size 1.524 1.524) (thickness 0.381)))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
)
(gr_text TDI-TIN (at 158.115 91.44) (layer Dessus)
Update demo
2018-01-10 15:41:40 +00:00
(effects (font (size 1.524 1.524) (thickness 0.381)))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
)
(gr_text TDO-DONE (at 158.115 86.36) (layer Dessus)
Update demo
2018-01-10 15:41:40 +00:00
(effects (font (size 1.524 1.524) (thickness 0.381)))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
)
(gr_text VCC (at 162.56 76.2) (layer Dessus)
Update demo
2018-01-10 15:41:40 +00:00
(effects (font (size 1.524 1.524) (thickness 0.381)))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
)
(gr_text GND (at 162.56 81.28) (layer Dessus)
Update demo
2018-01-10 15:41:40 +00:00
(effects (font (size 1.524 1.524) (thickness 0.381)))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
)
(gr_text "Component Side" (at 121.92 69.85) (layer Dessus)
Update demo
2018-01-10 15:41:40 +00:00
(effects (font (size 1.524 1.524) (thickness 0.3048)))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
)
(gr_text "Copper layer" (at 119.38 68.58) (layer Dessous)
Update demo
2018-01-10 15:41:40 +00:00
(effects (font (size 1.524 1.524) (thickness 0.3048)) (justify mirror))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
)
Update demos. Fix pspice netlist issues when using ( and ) in net names ( parenthesis are replaced by underscore) .
2014-01-07 19:42:34 +00:00
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1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
Update demos
2018-02-01 12:25:56 +00:00
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Corrected a few pads layer settings in 'sonde xilinx' demo.
2015-04-16 07:33:33 +00:00
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Update demos
2018-02-01 12:25:56 +00:00
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Corrected a few pads layer settings in 'sonde xilinx' demo.
2015-04-16 07:33:33 +00:00
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2018-02-01 12:25:56 +00:00
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2018-01-11 13:21:58 +00:00
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2018-02-01 12:25:56 +00:00
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2018-02-01 12:25:56 +00:00
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Update demos
2018-01-11 13:21:58 +00:00
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2018-02-01 12:25:56 +00:00
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2018-01-11 13:21:58 +00:00
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2018-02-01 12:25:56 +00:00
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Corrected a few pads layer settings in 'sonde xilinx' demo.
2015-04-16 07:33:33 +00:00
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Update demos
2018-02-01 12:25:56 +00:00
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2018-01-11 13:21:58 +00:00
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Update demos
2018-02-01 12:25:56 +00:00
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Update demos
2018-01-11 13:21:58 +00:00
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2018-02-01 12:25:56 +00:00
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1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
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Update demos
2018-02-01 12:25:56 +00:00
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2018-01-11 13:21:58 +00:00
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2018-01-11 13:21:58 +00:00
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Corrected a few pads layer settings in 'sonde xilinx' demo.
2015-04-16 07:33:33 +00:00
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2018-02-01 12:25:56 +00:00
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Corrected a few pads layer settings in 'sonde xilinx' demo.
2015-04-16 07:33:33 +00:00
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Corrected a few pads layer settings in 'sonde xilinx' demo.
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Corrected a few pads layer settings in 'sonde xilinx' demo.
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Corrected a few pads layer settings in 'sonde xilinx' demo.
2015-04-16 07:33:33 +00:00
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Corrected a few pads layer settings in 'sonde xilinx' demo.
2015-04-16 07:33:33 +00:00
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2015-04-16 07:33:33 +00:00
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Update demos
2018-02-01 12:25:56 +00:00
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Corrected a few pads layer settings in 'sonde xilinx' demo.
2015-04-16 07:33:33 +00:00
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2018-02-01 12:25:56 +00:00
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2018-02-01 12:25:56 +00:00
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2018-02-01 12:25:56 +00:00
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Update demos
2018-02-01 12:25:56 +00:00
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Update demo
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2015-04-16 07:33:33 +00:00
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2015-04-16 07:33:33 +00:00
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1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
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Corrected a few pads layer settings in 'sonde xilinx' demo.
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2018-02-01 12:25:56 +00:00
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2015-04-16 07:33:33 +00:00
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Update demos
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Update demo
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Update demos
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2018-02-01 12:25:56 +00:00
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Update demo
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2018-02-01 12:25:56 +00:00
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2018-01-10 15:41:40 +00:00
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Update demos
2018-02-01 12:25:56 +00:00
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1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
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Update demo
2018-01-10 15:41:40 +00:00
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
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2018-02-01 12:25:56 +00:00
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Update demos
2018-01-11 13:21:58 +00:00
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Update demos
2018-02-01 12:25:56 +00:00
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1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
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