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kicad/demos/sonde xilinx/sonde xilinx.pro

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Update demos
2017-11-21 20:26:06 +00:00
update=21/11/2017 20:57:10
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
version=1
Demos: make a private library for each demo, to avoid issues when using modified kicad new schematic libraries
2015-05-18 07:15:25 +00:00
last_client=kicad
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
[cvpcb]
NetITyp=0
NetIExt=.net
PkgIExt=.pkg
NetDir=
LibDir=
NetType=0
[pcbnew]
version=1
PadDrlX=320
PadDimH=620
PadDimV=900
BoardThickness=630
TxtPcbV=600
TxtPcbH=600
TxtModV=600
TxtModH=120
TxtModW=120
VEgarde=100
DrawLar=120
EdgeLar=120
TxtLar=120
MSegLar=120
LastNetListRead=sonde xilinx.net
[pcbnew/libraries]
LibDir=
LibName1=supports
LibName2=connect
LibName3=discret
LibName4=pin_array
LibName5=divers
LibName6=libcms
LibName7=display
LibName8=valves
Update demos. Fix pspice netlist issues when using ( and ) in net names ( parenthesis are replaced by underscore) .
2014-01-07 19:42:34 +00:00
[general]
version=1
[eeschema]
version=1
LibDir=