2020-08-25 17:42:52 +00:00
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/*
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* This program source code file is part of KiCad, a free EDA CAD application.
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*
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2022-03-13 12:27:43 +00:00
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* Copyright (C) 2004-2022 KiCad Developers.
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2020-08-25 17:42:52 +00:00
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you may find one here:
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* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
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* or you may search the http://www.gnu.org website for the version 2 license,
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* or you may write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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#include <common.h>
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2020-09-11 15:04:11 +00:00
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#include <drc/drc_engine.h>
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#include <drc/drc_item.h>
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#include <drc/drc_rule.h>
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#include <drc/drc_test_provider.h>
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2021-06-06 19:03:10 +00:00
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#include <pad.h>
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2021-06-03 18:05:43 +00:00
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#include <zone.h>
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2020-08-25 17:42:52 +00:00
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/*
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"Disallow" test. Goes through all items, matching types/conditions drop errors.
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Errors generated:
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- DRCE_ALLOWED_ITEMS
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2021-05-24 18:53:19 +00:00
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- DRCE_TEXT_ON_EDGECUTS
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2020-08-25 17:42:52 +00:00
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*/
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class DRC_TEST_PROVIDER_DISALLOW : public DRC_TEST_PROVIDER
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{
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public:
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DRC_TEST_PROVIDER_DISALLOW()
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{
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}
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virtual ~DRC_TEST_PROVIDER_DISALLOW()
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{
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}
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virtual bool Run() override;
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virtual const wxString GetName() const override
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{
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2022-03-13 12:27:43 +00:00
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return wxT( "disallow" );
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2020-08-25 17:42:52 +00:00
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};
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virtual const wxString GetDescription() const override
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{
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2022-03-13 12:27:43 +00:00
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return wxT( "Tests for disallowed items (e.g. keepouts)" );
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2020-08-25 17:42:52 +00:00
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}
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2021-01-01 22:29:15 +00:00
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virtual std::set<DRC_CONSTRAINT_T> GetConstraintTypes() const override;
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2020-09-14 17:54:14 +00:00
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int GetNumPhases() const override;
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2020-08-25 17:42:52 +00:00
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};
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2020-09-11 21:50:53 +00:00
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bool DRC_TEST_PROVIDER_DISALLOW::Run()
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2020-08-25 17:42:52 +00:00
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{
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2020-09-18 19:57:54 +00:00
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if( !reportPhase( _( "Checking keepouts & disallow constraints..." ) ) )
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2021-02-27 13:43:41 +00:00
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return false; // DRC cancelled
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2020-08-25 17:42:52 +00:00
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2021-06-02 13:00:11 +00:00
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// Zones can be expensive (particularly when multi-layer), so we run the progress bar on them
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BOARD* board = m_drcEngine->GetBoard();
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int boardZoneCount = board->Zones().size();
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int delta = std::max( 1, boardZoneCount / board->GetCopperLayerCount() );
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int ii = 0;
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2020-10-21 23:59:40 +00:00
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auto doCheckItem =
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[&]( BOARD_ITEM* item )
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{
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2021-02-08 14:53:49 +00:00
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auto constraint = m_drcEngine->EvalRules( DISALLOW_CONSTRAINT, item, nullptr,
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2021-02-16 15:50:43 +00:00
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UNDEFINED_LAYER );
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2020-12-04 19:29:04 +00:00
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2020-10-21 23:59:40 +00:00
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if( constraint.m_DisallowFlags )
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{
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_ALLOWED_ITEMS );
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2022-06-15 23:42:34 +00:00
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wxString msg;
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2020-10-21 23:59:40 +00:00
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2022-06-15 23:42:34 +00:00
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msg.Printf( drcItem->GetErrorText() + wxS( " (%s)" ),
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2020-10-21 23:59:40 +00:00
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constraint.GetName() );
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2022-06-15 23:42:34 +00:00
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drcItem->SetErrorMessage( msg );
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2020-10-21 23:59:40 +00:00
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drcItem->SetItems( item );
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drcItem->SetViolatingRule( constraint.GetParentRule() );
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2020-11-24 22:16:41 +00:00
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reportViolation( drcItem, item->GetPosition() );
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2020-10-21 23:59:40 +00:00
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}
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};
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auto checkItem =
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[&]( BOARD_ITEM* item ) -> bool
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{
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2021-05-24 18:53:19 +00:00
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if( !m_drcEngine->IsErrorLimitExceeded( DRCE_TEXT_ON_EDGECUTS )
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&& item->GetLayer() == Edge_Cuts )
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{
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switch( item->Type() )
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{
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case PCB_TEXT_T:
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case PCB_DIM_ALIGNED_T:
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case PCB_DIM_CENTER_T:
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case PCB_DIM_ORTHOGONAL_T:
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case PCB_DIM_LEADER_T:
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{
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std::shared_ptr<DRC_ITEM> drc = DRC_ITEM::Create( DRCE_TEXT_ON_EDGECUTS );
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drc->SetItems( item );
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reportViolation( drc, item->GetPosition() );
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}
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break;
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default:
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break;
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}
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}
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2020-10-21 23:59:40 +00:00
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if( m_drcEngine->IsErrorLimitExceeded( DRCE_ALLOWED_ITEMS ) )
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return false;
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2021-03-07 17:54:49 +00:00
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if( item->Type() == PCB_ZONE_T || item->Type() == PCB_FP_ZONE_T )
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{
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ZONE* zone = static_cast<ZONE*>( item );
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if( zone->GetIsRuleArea() )
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return true;
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2021-06-02 13:00:11 +00:00
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if( item->Type() == PCB_ZONE_T )
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{
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if( !reportProgress( ii++, boardZoneCount, delta ) )
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return false; // DRC cancelled
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}
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2021-03-07 17:54:49 +00:00
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}
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2020-10-21 23:59:40 +00:00
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item->ClearFlags( HOLE_PROXY );
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doCheckItem( item );
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2021-02-17 10:19:59 +00:00
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bool hasHole;
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switch( item->Type() )
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{
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case PCB_VIA_T: hasHole = true; break;
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case PCB_PAD_T: hasHole = static_cast<PAD*>( item )->GetDrillSizeX() > 0; break;
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default: hasHole = false; break;
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}
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if( hasHole )
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2020-10-21 23:59:40 +00:00
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{
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item->SetFlags( HOLE_PROXY );
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doCheckItem( item );
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2020-12-05 19:43:11 +00:00
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item->ClearFlags( HOLE_PROXY );
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2020-10-21 23:59:40 +00:00
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}
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return true;
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};
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2020-08-25 17:42:52 +00:00
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forEachGeometryItem( {}, LSET::AllLayersMask(), checkItem );
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reportRuleStatistics();
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return true;
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}
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2020-09-14 17:54:14 +00:00
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int DRC_TEST_PROVIDER_DISALLOW::GetNumPhases() const
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{
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return 1;
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}
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2021-01-01 22:29:15 +00:00
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std::set<DRC_CONSTRAINT_T> DRC_TEST_PROVIDER_DISALLOW::GetConstraintTypes() const
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2020-08-25 17:42:52 +00:00
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{
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2020-11-02 16:20:00 +00:00
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return { DISALLOW_CONSTRAINT };
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2020-08-25 17:42:52 +00:00
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}
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namespace detail
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{
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2020-09-11 21:50:53 +00:00
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static DRC_REGISTER_TEST_PROVIDER<DRC_TEST_PROVIDER_DISALLOW> dummy;
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2020-09-07 12:31:19 +00:00
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}
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