kicad/qa/data/issue5320.kicad_pro

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{
"board": {
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"dimensions": {
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"pads": {
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},
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"silk_text_italic": false,
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"diff_pair_dimensions": [
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}
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"drc_exclusions": [],
"meta": {
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},
"rule_severities": {
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"clearance": "error",
"copper_edge_clearance": "error",
"copper_sliver": "warning",
"courtyards_overlap": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"hole_clearance": "error",
"hole_near_hole": "error",
"invalid_outline": "error",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
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"microvia_drill_out_of_range": "error",
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"npth_inside_courtyard": "ignore",
"padstack": "error",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_over_copper": "warning",
"silk_overlap": "warning",
"skew_out_of_range": "error",
"solder_mask_bridge": "error",
"starved_thermal": "error",
"text_height": "warning",
"text_thickness": "warning",
"too_many_vias": "error",
"track_dangling": "warning",
"track_width": "error",
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"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zone_has_empty_net": "error",
"zones_intersect": "error"
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"zones_allow_external_fillets": false,
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"layer_presets": []
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"boards": [],
"cvpcb": {
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"rule_severities": {
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"bus_label_syntax": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_sheet_names": "error",
"global_label_dangling": "error",
"hier_label_mismatch": "error",
"label_dangling": "error",
"multiple_net_names": "error",
"net_not_bus_member": "error",
"no_connect_connected": "error",
"no_connect_dangling": "error",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "warning",
"similar_labels": "error",
"unresolved_variable": "error"
}
},
"libraries": {
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"pinned_symbol_libs": []
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"meta": {
"filename": "issue5320.kicad_pro",
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},
"net_settings": {
"classes": [
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"clearance": 0.127,
"diff_pair_gap": 0.25,
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"microvia_diameter": 0.127,
"microvia_drill": 0.762,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.127,
"via_diameter": 0.508,
"via_drill": 0.254,
"wire_width": 6.0
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"hidden_nets": [],
"meta": {
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"net_colors": null
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"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "DC_DC_UAV_Converter.net",
"specctra_dsn": "",
"step": "../../../../Mechanical Design/JVAB/VHF Module/Rev 1.0A/VHF_Module_PCB.step",
"vmrl": "",
"vrml": ""
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"page_layout_descr_file": ""
},
"schematic": {
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"default_junction_size": 40.0,
"default_line_thickness": 6.0,
"default_text_size": 50.0,
"default_wire_thickness": 6.0,
"field_names": [],
"pin_symbol_size": 25.0,
"text_offset_ratio": 0.3
},
"legacy_lib_dir": "",
"legacy_lib_list": [],
"meta": {
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"net_format_name": "",
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"plot_directory": "C:/Temp/",
"spice_adjust_passive_values": false,
"spice_external_command": "spice \"%I\"",
"subpart_first_id": 65,
"subpart_id_separator": 0
},
"sheets": [
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]
],
"text_variables": {}
}