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kicad/demos/interf_u/interf_u.pro

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Eeschema: fix Bug #1210120
2013-08-09 06:51:14 +00:00
update=07/08/2013 15:44:03
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
version=1
last_client=pcbnew
[common]
NetDir=
[general]
version=1
RootSch=interf_u.sch
BoardNm=interf_u.brd
[cvpcb]
version=1
NetIExt=net
[cvpcb/libraries]
EquName1=devcms
[eeschema]
version=1
Eeschema: fix Bug #1210120
2013-08-09 06:51:14 +00:00
PageLayoutDescrFile=pagelayout_logo.kicad_wks
SubpartIdSeparator=0
SubpartFirstId=65
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
LibDir=
Eeschema: fix Bug #1210120
2013-08-09 06:51:14 +00:00
NetFmtName=
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
RptD_X=0
RptD_Y=100
RptLab=1
LabSize=60
[eeschema/libraries]
LibName1=power
LibName2=device
LibName3=conn
LibName4=linear
LibName5=regul
LibName6=74xx
LibName7=cmos4000
LibName8=adc-dac
LibName9=memory
LibName10=xilinx
LibName11=special
LibName12=image
[pcbnew]
version=1
Eeschema: fix Bug #1210120
2013-08-09 06:51:14 +00:00
PageLayoutDescrFile=pagelayout_logo.kicad_wks
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
LastNetListRead=interf_u.net
Eeschema: fix Bug #1210120
2013-08-09 06:51:14 +00:00
UseCmpFile=1
PadDrill=0.89916
PadDrillOvalY=0.89916
PadSizeH=1.397
PadSizeV=1.397
PcbTextSizeV=2.032
PcbTextSizeH=1.524
PcbTextThickness=0.4318
ModuleTextSizeV=1.524
ModuleTextSizeH=1.524
ModuleTextSizeThickness=0.3048
SolderMaskClearance=0.254
SolderMaskMinWidth=0
DrawSegmentWidth=0.381
BoardOutlineThickness=0.127
ModuleOutlineThickness=0.381
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.
2013-05-26 04:36:44 +00:00
[pcbnew/libraries]
LibDir=
LibName1=connect
LibName2=discret
LibName3=led
LibName4=sockets
LibName5=dip_sockets
LibName6=pin_array
LibName7=divers
LibName8=libcms
LibName9=display