haskal
/
kicad
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

SNR.

This commit is contained in:
Jeff Young 2021-01-01 22:29:15 +00:00
parent 8ee72853fb
commit 018c17399d
25 changed files with 80 additions and 86 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

39
pcbnew/drc/drc_engine.cpp
View File

@ -73,11 +73,10 @@ DRC_ENGINE::~DRC_ENGINE()
for( DRC_RULE* rule : m_rules )
delete rule;
for( std::pair< DRC_CONSTRAINT_TYPE_T,
std::vector<CONSTRAINT_WITH_CONDITIONS*>* > pair : m_constraintMap )
for( std::pair<DRC_CONSTRAINT_T, std::vector<DRC_ENGINE_CONSTRAINT*>*> pair : m_constraintMap )
{
for( CONSTRAINT_WITH_CONDITIONS* constraintWithCondition : *pair.second )
delete constraintWithCondition;
for( DRC_ENGINE_CONSTRAINT* constraint : *pair.second )
delete constraint;
delete pair.second;
}
@ -432,7 +431,7 @@ static wxString formatConstraint( const DRC_CONSTRAINT& constraint )
{
struct FORMATTER
{
DRC_CONSTRAINT_TYPE_T type;
DRC_CONSTRAINT_T type;
wxString name;
std::function<wxString(const DRC_CONSTRAINT&)> formatter;
};
@ -526,12 +525,12 @@ void DRC_ENGINE::compileRules()
ReportAux( wxString::Format( "- Provider: '%s': ", provider->GetName() ) );
drc_dbg( 7, "do prov %s", provider->GetName() );
for( DRC_CONSTRAINT_TYPE_T id : provider->GetConstraintTypes() )
for( DRC_CONSTRAINT_T id : provider->GetConstraintTypes() )
{
drc_dbg( 7, "do id %d", id );
if( m_constraintMap.find( id ) == m_constraintMap.end() )
m_constraintMap[ id ] = new std::vector<CONSTRAINT_WITH_CONDITIONS*>();
m_constraintMap[ id ] = new std::vector<DRC_ENGINE_CONSTRAINT*>();
for( DRC_RULE* rule : m_rules )
{
@ -553,7 +552,7 @@ void DRC_ENGINE::compileRules()
if( constraint.m_Type != id )
continue;
CONSTRAINT_WITH_CONDITIONS* rcons = new CONSTRAINT_WITH_CONDITIONS;
DRC_ENGINE_CONSTRAINT* rcons = new DRC_ENGINE_CONSTRAINT;
rcons->layerTest = rule->m_LayerCondition;
rcons->condition = condition;
@ -608,11 +607,10 @@ void DRC_ENGINE::InitEngine( const wxFileName& aRulePath )
m_rules.clear();
m_rulesValid = false;
for( std::pair< DRC_CONSTRAINT_TYPE_T,
std::vector<CONSTRAINT_WITH_CONDITIONS*>* > pair : m_constraintMap )
for( std::pair<DRC_CONSTRAINT_T, std::vector<DRC_ENGINE_CONSTRAINT*>*> pair : m_constraintMap )
{
for( CONSTRAINT_WITH_CONDITIONS* constraintWithCondition : *pair.second )
delete constraintWithCondition;
for( DRC_ENGINE_CONSTRAINT* constraint : *pair.second )
delete constraint;
delete pair.second;
}
@ -708,7 +706,7 @@ void DRC_ENGINE::RunTests( EDA_UNITS aUnits, bool aReportAllTrackErrors, bool aT
}
DRC_CONSTRAINT DRC_ENGINE::EvalRulesForItems( DRC_CONSTRAINT_TYPE_T aConstraintId,
DRC_CONSTRAINT DRC_ENGINE::EvalRulesForItems( DRC_CONSTRAINT_T aConstraintId,
const BOARD_ITEM* a, const BOARD_ITEM* b,
PCB_LAYER_ID aLayer, REPORTER* aReporter )
{
@ -778,7 +776,7 @@ DRC_CONSTRAINT DRC_ENGINE::EvalRulesForItems( DRC_CONSTRAINT_TYPE_T aConstraintI
}
auto processConstraint =
[&]( const CONSTRAINT_WITH_CONDITIONS* c ) -> bool
[&]( const DRC_ENGINE_CONSTRAINT* c ) -> bool
{
implicit = c->parentRule && c->parentRule->m_Implicit;
@ -961,7 +959,7 @@ DRC_CONSTRAINT DRC_ENGINE::EvalRulesForItems( DRC_CONSTRAINT_TYPE_T aConstraintI
if( m_constraintMap.count( aConstraintId ) )
{
std::vector<CONSTRAINT_WITH_CONDITIONS*>* ruleset = m_constraintMap[ aConstraintId ];
std::vector<DRC_ENGINE_CONSTRAINT*>* ruleset = m_constraintMap[ aConstraintId ];
if( aReporter )
{
@ -1100,7 +1098,7 @@ bool DRC_ENGINE::ReportPhase( const wxString& aMessage )
#if 0
DRC_CONSTRAINT DRC_ENGINE::GetWorstGlobalConstraint( DRC_CONSTRAINT_TYPE_T ruleID )
DRC_CONSTRAINT DRC_ENGINE::GetWorstGlobalConstraint( DRC_CONSTRAINT_T ruleID )
{
DRC_CONSTRAINT rv;
@ -1120,13 +1118,13 @@ DRC_CONSTRAINT DRC_ENGINE::GetWorstGlobalConstraint( DRC_CONSTRAINT_TYPE_T ruleI
#endif
std::vector<DRC_CONSTRAINT> DRC_ENGINE::QueryConstraintsById( DRC_CONSTRAINT_TYPE_T constraintID )
std::vector<DRC_CONSTRAINT> DRC_ENGINE::QueryConstraintsById( DRC_CONSTRAINT_T constraintID )
{
std::vector<DRC_CONSTRAINT> rv;
if( m_constraintMap.count( constraintID ) )
{
for ( CONSTRAINT_WITH_CONDITIONS* c : *m_constraintMap[constraintID] )
for ( DRC_ENGINE_CONSTRAINT* c : *m_constraintMap[constraintID] )
rv.push_back( c->constraint );
}
@ -1134,7 +1132,7 @@ std::vector<DRC_CONSTRAINT> DRC_ENGINE::QueryConstraintsById( DRC_CONSTRAINT_TYP
}
bool DRC_ENGINE::HasRulesForConstraintType( DRC_CONSTRAINT_TYPE_T constraintID )
bool DRC_ENGINE::HasRulesForConstraintType( DRC_CONSTRAINT_T constraintID )
{
//drc_dbg(10,"hascorrect id %d size %d\n", ruleID, m_ruleMap[ruleID]->sortedRules.size( ) );
if( m_constraintMap.count( constraintID ) )
@ -1144,8 +1142,7 @@ bool DRC_ENGINE::HasRulesForConstraintType( DRC_CONSTRAINT_TYPE_T constraintID )
}
bool DRC_ENGINE::QueryWorstConstraint( DRC_CONSTRAINT_TYPE_T aConstraintId,
DRC_CONSTRAINT& aConstraint )
bool DRC_ENGINE::QueryWorstConstraint( DRC_CONSTRAINT_T aConstraintId, DRC_CONSTRAINT& aConstraint )
{
int worst = 0;

14
pcbnew/drc/drc_engine.h
View File

@ -140,14 +140,14 @@ public:
bool IsErrorLimitExceeded( int error_code );
DRC_CONSTRAINT EvalRulesForItems( DRC_CONSTRAINT_TYPE_T ruleID, const BOARD_ITEM* a,
DRC_CONSTRAINT EvalRulesForItems( DRC_CONSTRAINT_T ruleID, const BOARD_ITEM* a,
const BOARD_ITEM* b = nullptr,
PCB_LAYER_ID aLayer = UNDEFINED_LAYER,
REPORTER* aReporter = nullptr );
std::vector<DRC_CONSTRAINT> QueryConstraintsById( DRC_CONSTRAINT_TYPE_T ruleID );
std::vector<DRC_CONSTRAINT> QueryConstraintsById( DRC_CONSTRAINT_T ruleID );
bool HasRulesForConstraintType( DRC_CONSTRAINT_TYPE_T constraintID );
bool HasRulesForConstraintType( DRC_CONSTRAINT_T constraintID );
EDA_UNITS UserUnits() const { return m_userUnits; }
bool GetReportAllTrackErrors() const { return m_reportAllTrackErrors; }
@ -160,7 +160,7 @@ public:
bool ReportPhase( const wxString& aMessage );
void ReportAux( const wxString& aStr );
bool QueryWorstConstraint( DRC_CONSTRAINT_TYPE_T aRuleId, DRC_CONSTRAINT& aConstraint );
bool QueryWorstConstraint( DRC_CONSTRAINT_T aRuleId, DRC_CONSTRAINT& aConstraint );
std::vector<DRC_TEST_PROVIDER* > GetTestProviders() const { return m_testProviders; };
@ -183,7 +183,7 @@ private:
void compileRules();
struct CONSTRAINT_WITH_CONDITIONS
struct DRC_ENGINE_CONSTRAINT
{
LSET layerTest;
DRC_RULE_CONDITION* condition;
@ -192,7 +192,6 @@ private:
};
void loadImplicitRules();
void loadTestProviders();
DRC_RULE* createImplicitRule( const wxString& name );
protected:
@ -211,8 +210,7 @@ protected:
bool m_testFootprints;
// constraint -> rule -> provider
std::unordered_map< DRC_CONSTRAINT_TYPE_T,
std::vector<CONSTRAINT_WITH_CONDITIONS*>* > m_constraintMap;
std::unordered_map<DRC_CONSTRAINT_T, std::vector<DRC_ENGINE_CONSTRAINT*>*> m_constraintMap;
DRC_VIOLATION_HANDLER m_violationHandler;
REPORTER* m_reporter;

2
pcbnew/drc/drc_rule.cpp
View File

@ -49,7 +49,7 @@ void DRC_RULE::AddConstraint( DRC_CONSTRAINT& aConstraint )
m_Constraints.push_back( aConstraint );
}
OPT<DRC_CONSTRAINT> DRC_RULE::FindConstraint( DRC_CONSTRAINT_TYPE_T aType )
OPT<DRC_CONSTRAINT> DRC_RULE::FindConstraint( DRC_CONSTRAINT_T aType )
{
for( auto &c : m_Constraints)
if( c.m_Type == aType )

8
pcbnew/drc/drc_rule.h
View File

@ -38,7 +38,7 @@ class DRC_CONSTRAINT;
class DRC_RULE_CONDITION;
enum DRC_CONSTRAINT_TYPE_T
enum DRC_CONSTRAINT_T
{
NULL_CONSTRAINT = 0,
CLEARANCE_CONSTRAINT,
@ -88,7 +88,7 @@ public:
};
void AddConstraint( DRC_CONSTRAINT& aConstraint );
OPT<DRC_CONSTRAINT> FindConstraint( DRC_CONSTRAINT_TYPE_T aType );
OPT<DRC_CONSTRAINT> FindConstraint( DRC_CONSTRAINT_T aType );
public:
bool m_Unary;
@ -104,7 +104,7 @@ public:
class DRC_CONSTRAINT
{
public:
DRC_CONSTRAINT( DRC_CONSTRAINT_TYPE_T aType = NULL_CONSTRAINT,
DRC_CONSTRAINT( DRC_CONSTRAINT_T aType = NULL_CONSTRAINT,
const wxString& aName = wxEmptyString ) :
m_Type( aType ),
m_DisallowFlags( 0 ),
@ -138,7 +138,7 @@ class DRC_CONSTRAINT
}
public:
DRC_CONSTRAINT_TYPE_T m_Type;
DRC_CONSTRAINT_T m_Type;
MINOPTMAX<int> m_Value;
int m_DisallowFlags;

2
pcbnew/drc/drc_test_provider.h
View File

@ -89,7 +89,7 @@ public:
virtual const wxString GetName() const;
virtual const wxString GetDescription() const;
virtual std::set<DRC_CONSTRAINT_TYPE_T> GetConstraintTypes() const = 0;
virtual std::set<DRC_CONSTRAINT_T> GetConstraintTypes() const = 0;
virtual int GetNumPhases() const = 0;

4
pcbnew/drc/drc_test_provider_annulus.cpp
View File

@ -61,7 +61,7 @@ public:
return "Tests pad/via annular rings";
}
virtual std::set<DRC_CONSTRAINT_TYPE_T> GetConstraintTypes() const override;
virtual std::set<DRC_CONSTRAINT_T> GetConstraintTypes() const override;
int GetNumPhases() const override;
};
@ -163,7 +163,7 @@ int DRC_TEST_PROVIDER_ANNULUS::GetNumPhases() const
}
std::set<DRC_CONSTRAINT_TYPE_T> DRC_TEST_PROVIDER_ANNULUS::GetConstraintTypes() const
std::set<DRC_CONSTRAINT_T> DRC_TEST_PROVIDER_ANNULUS::GetConstraintTypes() const
{
return { ANNULAR_WIDTH_CONSTRAINT };
}

4
pcbnew/drc/drc_test_provider_connectivity.cpp
View File

@ -63,7 +63,7 @@ public:
return "Tests board connectivity";
}
virtual std::set<DRC_CONSTRAINT_TYPE_T> GetConstraintTypes() const override;
virtual std::set<DRC_CONSTRAINT_T> GetConstraintTypes() const override;
int GetNumPhases() const override;
};
@ -178,7 +178,7 @@ int DRC_TEST_PROVIDER_CONNECTIVITY::GetNumPhases() const
}
std::set<DRC_CONSTRAINT_TYPE_T> DRC_TEST_PROVIDER_CONNECTIVITY::GetConstraintTypes() const
std::set<DRC_CONSTRAINT_T> DRC_TEST_PROVIDER_CONNECTIVITY::GetConstraintTypes() const
{
return {};
}

4
pcbnew/drc/drc_test_provider_copper_clearance.cpp
View File

@ -73,7 +73,7 @@ public:
return "Tests copper item clearance";
}
virtual std::set<DRC_CONSTRAINT_TYPE_T> GetConstraintTypes() const override;
virtual std::set<DRC_CONSTRAINT_T> GetConstraintTypes() const override;
int GetNumPhases() const override;
@ -896,7 +896,7 @@ int DRC_TEST_PROVIDER_COPPER_CLEARANCE::GetNumPhases() const
}
std::set<DRC_CONSTRAINT_TYPE_T> DRC_TEST_PROVIDER_COPPER_CLEARANCE::GetConstraintTypes() const
std::set<DRC_CONSTRAINT_T> DRC_TEST_PROVIDER_COPPER_CLEARANCE::GetConstraintTypes() const
{
return { CLEARANCE_CONSTRAINT, HOLE_CLEARANCE_CONSTRAINT };
}

4
pcbnew/drc/drc_test_provider_courtyard_clearance.cpp
View File

@ -61,7 +61,7 @@ public:
return "Tests footprints' courtyard clearance";
}
virtual std::set<DRC_CONSTRAINT_TYPE_T> GetConstraintTypes() const override;
virtual std::set<DRC_CONSTRAINT_T> GetConstraintTypes() const override;
int GetNumPhases() const override;
@ -245,7 +245,7 @@ int DRC_TEST_PROVIDER_COURTYARD_CLEARANCE::GetNumPhases() const
}
std::set<DRC_CONSTRAINT_TYPE_T> DRC_TEST_PROVIDER_COURTYARD_CLEARANCE::GetConstraintTypes() const
std::set<DRC_CONSTRAINT_T> DRC_TEST_PROVIDER_COURTYARD_CLEARANCE::GetConstraintTypes() const
{
return { COURTYARD_CLEARANCE_CONSTRAINT };
}

6
pcbnew/drc/drc_test_provider_diff_pair_coupling.cpp
View File

@ -78,7 +78,7 @@ public:
return 1;
}
virtual std::set<DRC_CONSTRAINT_TYPE_T> GetConstraintTypes() const override;
virtual std::set<DRC_CONSTRAINT_T> GetConstraintTypes() const override;
private:
@ -289,7 +289,7 @@ bool test::DRC_TEST_PROVIDER_DIFF_PAIR_COUPLING::Run()
{
drc_dbg( 10, "eval dp %p\n", item );
const DRC_CONSTRAINT_TYPE_T constraintsToCheck[] = {
const DRC_CONSTRAINT_T constraintsToCheck[] = {
DIFF_PAIR_GAP_CONSTRAINT,
DIFF_PAIR_MAX_UNCOUPLED_CONSTRAINT
};
@ -507,7 +507,7 @@ bool test::DRC_TEST_PROVIDER_DIFF_PAIR_COUPLING::Run()
}
std::set<DRC_CONSTRAINT_TYPE_T> test::DRC_TEST_PROVIDER_DIFF_PAIR_COUPLING::GetConstraintTypes() const
std::set<DRC_CONSTRAINT_T> test::DRC_TEST_PROVIDER_DIFF_PAIR_COUPLING::GetConstraintTypes() const
{
return { DIFF_PAIR_GAP_CONSTRAINT, DIFF_PAIR_MAX_UNCOUPLED_CONSTRAINT };
}

4
pcbnew/drc/drc_test_provider_disallow.cpp
View File

@ -56,7 +56,7 @@ public:
return "Tests for disallowed items (e.g. keepouts)";
}
virtual std::set<DRC_CONSTRAINT_TYPE_T> GetConstraintTypes() const override;
virtual std::set<DRC_CONSTRAINT_T> GetConstraintTypes() const override;
int GetNumPhases() const override;
};
@ -126,7 +126,7 @@ int DRC_TEST_PROVIDER_DISALLOW::GetNumPhases() const
}
std::set<DRC_CONSTRAINT_TYPE_T> DRC_TEST_PROVIDER_DISALLOW::GetConstraintTypes() const
std::set<DRC_CONSTRAINT_T> DRC_TEST_PROVIDER_DISALLOW::GetConstraintTypes() const
{
return { DISALLOW_CONSTRAINT };
}

8
pcbnew/drc/drc_test_provider_edge_clearance.cpp
View File

@ -68,19 +68,19 @@ public:
return "Tests items vs board edge clearance";
}
virtual std::set<DRC_CONSTRAINT_TYPE_T> GetConstraintTypes() const override;
virtual std::set<DRC_CONSTRAINT_T> GetConstraintTypes() const override;
int GetNumPhases() const override;
private:
bool testAgainstEdge( BOARD_ITEM* item, SHAPE* itemShape, BOARD_ITEM* other,
DRC_CONSTRAINT_TYPE_T aConstraintType, PCB_DRC_CODE aErrorCode );
DRC_CONSTRAINT_T aConstraintType, PCB_DRC_CODE aErrorCode );
};
bool DRC_TEST_PROVIDER_EDGE_CLEARANCE::testAgainstEdge( BOARD_ITEM* item, SHAPE* itemShape,
BOARD_ITEM* edge,
DRC_CONSTRAINT_TYPE_T aConstraintType,
DRC_CONSTRAINT_T aConstraintType,
PCB_DRC_CODE aErrorCode )
{
const std::shared_ptr<SHAPE>& edgeShape = edge->GetEffectiveShape( Edge_Cuts );
@ -259,7 +259,7 @@ int DRC_TEST_PROVIDER_EDGE_CLEARANCE::GetNumPhases() const
}
std::set<DRC_CONSTRAINT_TYPE_T> DRC_TEST_PROVIDER_EDGE_CLEARANCE::GetConstraintTypes() const
std::set<DRC_CONSTRAINT_T> DRC_TEST_PROVIDER_EDGE_CLEARANCE::GetConstraintTypes() const
{
return { EDGE_CLEARANCE_CONSTRAINT, SILK_CLEARANCE_CONSTRAINT };
}

4
pcbnew/drc/drc_test_provider_hole_clearance.cpp
View File

@ -64,7 +64,7 @@ public:
return "Tests hole to hole spacing";
}
virtual std::set<DRC_CONSTRAINT_TYPE_T> GetConstraintTypes() const override;
virtual std::set<DRC_CONSTRAINT_T> GetConstraintTypes() const override;
int GetNumPhases() const override;
@ -309,7 +309,7 @@ int DRC_TEST_PROVIDER_HOLE_CLEARANCE::GetNumPhases() const
}
std::set<DRC_CONSTRAINT_TYPE_T> DRC_TEST_PROVIDER_HOLE_CLEARANCE::GetConstraintTypes() const
std::set<DRC_CONSTRAINT_T> DRC_TEST_PROVIDER_HOLE_CLEARANCE::GetConstraintTypes() const
{
return { HOLE_TO_HOLE_CONSTRAINT };
}

4
pcbnew/drc/drc_test_provider_hole_size.cpp
View File

@ -62,7 +62,7 @@ public:
return "Tests sizes of drilled holes (via/pad drills)";
}
virtual std::set<DRC_CONSTRAINT_TYPE_T> GetConstraintTypes() const override;
virtual std::set<DRC_CONSTRAINT_T> GetConstraintTypes() const override;
int GetNumPhases() const override;
@ -202,7 +202,7 @@ int DRC_TEST_PROVIDER_HOLE_SIZE::GetNumPhases() const
}
std::set<DRC_CONSTRAINT_TYPE_T> DRC_TEST_PROVIDER_HOLE_SIZE::GetConstraintTypes() const
std::set<DRC_CONSTRAINT_T> DRC_TEST_PROVIDER_HOLE_SIZE::GetConstraintTypes() const
{
return { HOLE_SIZE_CONSTRAINT };
}

4
pcbnew/drc/drc_test_provider_lvs.cpp
View File

@ -67,7 +67,7 @@ public:
return "Performs layout-vs-schematics integity check";
}
virtual std::set<DRC_CONSTRAINT_TYPE_T> GetConstraintTypes() const override;
virtual std::set<DRC_CONSTRAINT_T> GetConstraintTypes() const override;
int GetNumPhases() const override;
@ -237,7 +237,7 @@ int DRC_TEST_PROVIDER_LVS::GetNumPhases() const
}
std::set<DRC_CONSTRAINT_TYPE_T> DRC_TEST_PROVIDER_LVS::GetConstraintTypes() const
std::set<DRC_CONSTRAINT_T> DRC_TEST_PROVIDER_LVS::GetConstraintTypes() const
{
return {};
}

6
pcbnew/drc/drc_test_provider_matched_length.cpp
View File

@ -70,7 +70,7 @@ public:
return 1;
}
virtual std::set<DRC_CONSTRAINT_TYPE_T> GetConstraintTypes() const override;
virtual std::set<DRC_CONSTRAINT_T> GetConstraintTypes() const override;
DRC_LENGTH_REPORT BuildLengthReport() const;
@ -235,7 +235,7 @@ bool DRC_TEST_PROVIDER_MATCHED_LENGTH::runInternal( bool aDelayReportMode )
auto evaluateLengthConstraints =
[&]( BOARD_ITEM *item ) -> bool
{
const DRC_CONSTRAINT_TYPE_T constraintsToCheck[] = {
const DRC_CONSTRAINT_T constraintsToCheck[] = {
LENGTH_CONSTRAINT,
SKEW_CONSTRAINT,
VIA_COUNT_CONSTRAINT,
@ -387,7 +387,7 @@ bool DRC_TEST_PROVIDER_MATCHED_LENGTH::runInternal( bool aDelayReportMode )
}
std::set<DRC_CONSTRAINT_TYPE_T> DRC_TEST_PROVIDER_MATCHED_LENGTH::GetConstraintTypes() const
std::set<DRC_CONSTRAINT_T> DRC_TEST_PROVIDER_MATCHED_LENGTH::GetConstraintTypes() const
{
return { LENGTH_CONSTRAINT, SKEW_CONSTRAINT, VIA_COUNT_CONSTRAINT };
}

4
pcbnew/drc/drc_test_provider_misc.cpp
View File

@ -65,7 +65,7 @@ public:
return "Misc checks (board outline, missing textvars)";
}
virtual std::set<DRC_CONSTRAINT_TYPE_T> GetConstraintTypes() const override;
virtual std::set<DRC_CONSTRAINT_T> GetConstraintTypes() const override;
int GetNumPhases() const override;
@ -238,7 +238,7 @@ int DRC_TEST_PROVIDER_MISC::GetNumPhases() const
}
std::set<DRC_CONSTRAINT_TYPE_T> DRC_TEST_PROVIDER_MISC::GetConstraintTypes() const
std::set<DRC_CONSTRAINT_T> DRC_TEST_PROVIDER_MISC::GetConstraintTypes() const
{
return {};
}

4
pcbnew/drc/drc_test_provider_silk_clearance.cpp
View File

@ -71,7 +71,7 @@ public:
return 1;
}
virtual std::set<DRC_CONSTRAINT_TYPE_T> GetConstraintTypes() const override;
virtual std::set<DRC_CONSTRAINT_T> GetConstraintTypes() const override;
private:
@ -247,7 +247,7 @@ bool DRC_TEST_PROVIDER_SILK_CLEARANCE::Run()
}
std::set<DRC_CONSTRAINT_TYPE_T> DRC_TEST_PROVIDER_SILK_CLEARANCE::GetConstraintTypes() const
std::set<DRC_CONSTRAINT_T> DRC_TEST_PROVIDER_SILK_CLEARANCE::GetConstraintTypes() const
{
return { SILK_CLEARANCE_CONSTRAINT };
}

4
pcbnew/drc/drc_test_provider_silk_to_mask.cpp
View File

@ -69,7 +69,7 @@ public:
return 1;
}
virtual std::set<DRC_CONSTRAINT_TYPE_T> GetConstraintTypes() const override;
virtual std::set<DRC_CONSTRAINT_T> GetConstraintTypes() const override;
private:
@ -188,7 +188,7 @@ bool DRC_TEST_PROVIDER_SILK_TO_MASK::Run()
}
std::set<DRC_CONSTRAINT_TYPE_T> DRC_TEST_PROVIDER_SILK_TO_MASK::GetConstraintTypes() const
std::set<DRC_CONSTRAINT_T> DRC_TEST_PROVIDER_SILK_TO_MASK::GetConstraintTypes() const
{
return { SILK_CLEARANCE_CONSTRAINT };
}

6
pcbnew/drc/drc_test_provider_track_width.cpp
View File

@ -57,7 +57,7 @@ public:
return "Tests track widths";
}
virtual std::set<DRC_CONSTRAINT_TYPE_T> GetConstraintTypes() const override;
virtual std::set<DRC_CONSTRAINT_T> GetConstraintTypes() const override;
int GetNumPhases() const override;
};
@ -67,7 +67,7 @@ bool DRC_TEST_PROVIDER_TRACK_WIDTH::Run()
{
const int delta = 100; // This is the number of tests between 2 calls to the progress bar
if( !m_drcEngine->HasRulesForConstraintType( DRC_CONSTRAINT_TYPE_T::TRACK_WIDTH_CONSTRAINT ) )
if( !m_drcEngine->HasRulesForConstraintType( TRACK_WIDTH_CONSTRAINT ) )
{
reportAux( "No track width constraints found. Skipping check." );
return false;
@ -169,7 +169,7 @@ int DRC_TEST_PROVIDER_TRACK_WIDTH::GetNumPhases() const
}
std::set<DRC_CONSTRAINT_TYPE_T> DRC_TEST_PROVIDER_TRACK_WIDTH::GetConstraintTypes() const
std::set<DRC_CONSTRAINT_T> DRC_TEST_PROVIDER_TRACK_WIDTH::GetConstraintTypes() const
{
return { TRACK_WIDTH_CONSTRAINT };
}

4
pcbnew/drc/drc_test_provider_via_diameter.cpp
View File

@ -56,7 +56,7 @@ public:
return "Tests via diameters";
}
virtual std::set<DRC_CONSTRAINT_TYPE_T> GetConstraintTypes() const override;
virtual std::set<DRC_CONSTRAINT_T> GetConstraintTypes() const override;
int GetNumPhases() const override;
};
@ -157,7 +157,7 @@ int DRC_TEST_PROVIDER_VIA_DIAMETER::GetNumPhases() const
}
std::set<DRC_CONSTRAINT_TYPE_T> DRC_TEST_PROVIDER_VIA_DIAMETER::GetConstraintTypes() const
std::set<DRC_CONSTRAINT_T> DRC_TEST_PROVIDER_VIA_DIAMETER::GetConstraintTypes() const
{
return { VIA_DIAMETER_CONSTRAINT };
}

2
pcbnew/router/pns_kicad_iface.cpp
View File

@ -170,7 +170,7 @@ bool PNS_PCBNEW_RULE_RESOLVER::QueryConstraint( PNS::CONSTRAINT_TYPE aType,
if( !drcEngine )
return false;
DRC_CONSTRAINT_TYPE_T hostType;
DRC_CONSTRAINT_T hostType;
switch ( aType )
{

5
pcbnew/tools/board_inspection_tool.cpp
View File

@ -212,9 +212,8 @@ void BOARD_INSPECTION_TOOL::reportZoneConnection( ZONE* aZone, PAD* aPad, REPORT
}
void BOARD_INSPECTION_TOOL::reportClearance( DRC_CONSTRAINT_TYPE_T aClearanceType,
PCB_LAYER_ID aLayer, BOARD_ITEM* aA, BOARD_ITEM* aB,
REPORTER* r )
void BOARD_INSPECTION_TOOL::reportClearance( DRC_CONSTRAINT_T aClearanceType, PCB_LAYER_ID aLayer,
BOARD_ITEM* aA, BOARD_ITEM* aB, REPORTER* r )
{
r->Report( "" );

4
pcbnew/tools/board_inspection_tool.h
View File

@ -132,8 +132,8 @@ private:
void reportZoneConnection( ZONE* aZone, PAD* aPad, REPORTER* r );
void reportClearance( DRC_CONSTRAINT_TYPE_T aClearanceType, PCB_LAYER_ID aLayer,
BOARD_ITEM* aA, BOARD_ITEM* aB, REPORTER* r );
void reportClearance( DRC_CONSTRAINT_T aClearanceType, PCB_LAYER_ID aLayer, BOARD_ITEM* aA,
BOARD_ITEM* aB, REPORTER* r );
wxString getItemDescription( BOARD_ITEM* aItem );

6
pcbnew/zone_filler.cpp
View File

@ -669,11 +669,11 @@ void ZONE_FILLER::buildCopperItemClearances( const ZONE* aZone, PCB_LAYER_ID aLa
zone_boundingbox.Inflate( m_worstClearance + extra_margin );
auto evalRulesForItems =
[&bds]( DRC_CONSTRAINT_TYPE_T aConstraint, const BOARD_ITEM* a, const BOARD_ITEM* b,
[&bds]( DRC_CONSTRAINT_T aConstraint, const BOARD_ITEM* a, const BOARD_ITEM* b,
PCB_LAYER_ID aEvalLayer ) -> int
{
DRC_CONSTRAINT c = bds.m_DRCEngine->EvalRulesForItems( aConstraint, a, b, aEvalLayer );
return c.Value().HasMin() ? c.Value().Min() : 0;
auto c = bds.m_DRCEngine->EvalRulesForItems( aConstraint, a, b, aEvalLayer );
return c.Value().Min();
};
// Add non-connected pad clearances