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Make track/via sizes UI more predictable and compatible with DRC. 

Two main changes: netclass values need to go through the DRC engine
so they can interact with other rules.  They're also now dependent
on the layer being routed as well as the start object.

Also make the controls adjust to each other better.  For instance,
copy-track-width needs to turn off when you select a particular
track width, and a particular track width needs to zero out when
you choose copy-track-width.

Fixes https://gitlab.com/kicad/code/kicad/issues/5951
This commit is contained in:
Jeff Young 2020-10-10 19:29:41 +01:00
parent cc563d254f
commit 04c4012ee6
11 changed files with 158 additions and 190 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
include/board_design_settings.h
View File

@ -439,16 +439,6 @@ public:
return ( m_diffPairIndex == 0 && !m_useCustomDiffPair );
}
/**
* Function SetCurrentNetClass
* Must be called after a netclass selection (or after a netclass parameter change
* Initialize vias and tracks values displayed in comb boxes of the auxiliary toolbar
* and some others parameters (netclass name ....)
* @param aNetClassName = the new netclass name
* @return true if lists of tracks and vias sizes are modified
*/
bool SetCurrentNetClass( const wxString& aNetClassName );
/**
* Function GetBiggestClearanceValue
* @return the biggest clearance value found in NetClasses list

82
pcbnew/board_design_settings.cpp
View File

@ -838,88 +838,6 @@ bool BOARD_DESIGN_SETTINGS::Ignore( int aDRCErrorCode )
}
bool BOARD_DESIGN_SETTINGS::SetCurrentNetClass( const wxString& aNetClassName )
{
NETCLASSPTR netClass = GetNetClasses().Find( aNetClassName );
bool lists_sizes_modified = false;
// if not found (should not happen) use the default
if( !netClass )
netClass = GetNetClasses().GetDefault();
m_currentNetClassName = netClass->GetName();
// Initialize others values:
if( m_TrackWidthList.size() == 0 )
{
lists_sizes_modified = true;
m_TrackWidthList.push_back( 0 );
}
if( m_ViasDimensionsList.size() == 0 )
{
lists_sizes_modified = true;
m_ViasDimensionsList.emplace_back( VIA_DIMENSION() );
}
if( m_DiffPairDimensionsList.size() == 0 )
{
lists_sizes_modified = true;
m_DiffPairDimensionsList.emplace_back( DIFF_PAIR_DIMENSION() );
}
/* note the m_ViasDimensionsList[0] and m_TrackWidthList[0] values
* are always the Netclass values
*/
if( m_TrackWidthList[0] != netClass->GetTrackWidth() )
{
lists_sizes_modified = true;
m_TrackWidthList[0] = netClass->GetTrackWidth();
}
if( m_ViasDimensionsList[0].m_Diameter != netClass->GetViaDiameter() )
{
lists_sizes_modified = true;
m_ViasDimensionsList[0].m_Diameter = netClass->GetViaDiameter();
}
if( m_ViasDimensionsList[0].m_Drill != netClass->GetViaDrill() )
{
lists_sizes_modified = true;
m_ViasDimensionsList[0].m_Drill = netClass->GetViaDrill();
}
if( m_DiffPairDimensionsList[0].m_Width != netClass->GetDiffPairWidth() )
{
lists_sizes_modified = true;
m_DiffPairDimensionsList[0].m_Width = netClass->GetDiffPairWidth();
}
if( m_DiffPairDimensionsList[0].m_Gap != netClass->GetDiffPairGap() )
{
lists_sizes_modified = true;
m_DiffPairDimensionsList[0].m_Gap = netClass->GetDiffPairGap();
}
if( m_DiffPairDimensionsList[0].m_ViaGap != netClass->GetDiffPairViaGap() )
{
lists_sizes_modified = true;
m_DiffPairDimensionsList[0].m_ViaGap = netClass->GetDiffPairViaGap();
}
if( GetViaSizeIndex() >= m_ViasDimensionsList.size() )
SetViaSizeIndex( m_ViasDimensionsList.size() );
if( GetTrackWidthIndex() >= m_TrackWidthList.size() )
SetTrackWidthIndex( m_TrackWidthList.size() );
if( GetDiffPairIndex() >= m_DiffPairDimensionsList.size() )
SetDiffPairIndex( m_DiffPairDimensionsList.size() );
return lists_sizes_modified;
}
int BOARD_DESIGN_SETTINGS::GetBiggestClearanceValue()
{
DRC_CONSTRAINT constraint;

5
pcbnew/class_board.cpp
View File

@ -82,13 +82,8 @@ BOARD::BOARD() :
// Initialize default netclass.
NETCLASS* defaultClass = bds.GetDefault();
defaultClass->SetDescription( _( "This is the default net class." ) );
bds.SetCurrentNetClass( defaultClass->GetName() );
// Set sensible initial values for custom track width & via size
bds.UseCustomTrackViaSize( false );
bds.SetCustomTrackWidth( bds.GetCurrentTrackWidth() );
bds.SetCustomViaSize( bds.GetCurrentViaSize() );
bds.SetCustomViaDrill( bds.GetCurrentViaDrill() );
// Initialize ratsnest
m_connectivity.reset( new CONNECTIVITY_DATA() );

69
pcbnew/drc/drc_engine.cpp
View File

@ -184,11 +184,9 @@ void DRC_ENGINE::loadImplicitRules()
auto makeNetclassRule =
[&]( const NETCLASSPTR& netclass, bool isDefault )
{
// Only add rules for netclass clearances which are larger than board minimums.
// Only add constraints for netclass values which are larger than board minimums.
// That way board minimums will still enforce a global minimum.
if( netclass->GetClearance() > bds.m_MinClearance )
{
DRC_RULE* rule = new DRC_RULE;
wxString name = netclass->GetName();
@ -201,10 +199,75 @@ void DRC_ENGINE::loadImplicitRules()
rule->m_Condition = condition;
netclassRules.push_back( rule );
if( netclass->GetClearance() > bds.m_MinClearance )
{
DRC_CONSTRAINT ncClearanceConstraint( DRC_CONSTRAINT_TYPE_CLEARANCE );
ncClearanceConstraint.Value().SetMin( netclass->GetClearance() );
rule->AddConstraint( ncClearanceConstraint );
}
if( netclass->GetTrackWidth() > bds.m_TrackMinWidth )
{
DRC_CONSTRAINT ncWidthConstraint( DRC_CONSTRAINT_TYPE_TRACK_WIDTH );
ncWidthConstraint.Value().SetMin( netclass->GetTrackWidth() );
rule->AddConstraint( ncWidthConstraint );
}
// We need separate rules for micro-vias and other vias because they use the
// same constraints.
//
// Note that since these are unary rules they don't need to be sorted, so we
// add them directly to the current rule set.
rule = new DRC_RULE;
rule->m_Name = wxString::Format( _( "netclass '%s'" ), name );
rule->m_Implicit = true;
expr = wxString::Format( "A.NetClass == '%s' && A.Via_Type != 'micro_via'", name );
condition = new DRC_RULE_CONDITION( expr );
rule->m_Condition = condition;
addRule( rule );
if( netclass->GetViaDiameter() > bds.m_ViasMinSize )
{
DRC_CONSTRAINT ncViaDiaConstraint( DRC_CONSTRAINT_TYPE_VIA_DIAMETER );
ncViaDiaConstraint.Value().SetMin( netclass->GetViaDiameter() );
rule->AddConstraint( ncViaDiaConstraint );
}
if( netclass->GetViaDrill() > bds.m_MinThroughDrill )
{
DRC_CONSTRAINT ncViaDrillConstraint( DRC_CONSTRAINT_TYPE_HOLE_SIZE );
ncViaDrillConstraint.Value().SetMin( netclass->GetViaDrill() );
rule->AddConstraint( ncViaDrillConstraint );
}
rule = new DRC_RULE;
rule->m_Name = wxString::Format( _( "netclass '%s'" ), name );
rule->m_Implicit = true;
expr = wxString::Format( "A.NetClass == '%s' && A.Via_Type == 'micro_via'", name );
condition = new DRC_RULE_CONDITION( expr );
rule->m_Condition = condition;
addRule( rule );
if( netclass->GetuViaDiameter() > bds.m_MicroViasMinSize )
{
DRC_CONSTRAINT ncuViaDiaConstraint( DRC_CONSTRAINT_TYPE_VIA_DIAMETER );
ncuViaDiaConstraint.Value().SetMin( netclass->GetuViaDiameter() );
rule->AddConstraint( ncuViaDiaConstraint );
}
if( netclass->GetuViaDrill() > bds.m_MicroViasMinDrill )
{
DRC_CONSTRAINT ncuViaDrillConstraint( DRC_CONSTRAINT_TYPE_HOLE_SIZE );
ncuViaDrillConstraint.Value().SetMin( netclass->GetuViaDrill() );
rule->AddConstraint( ncuViaDrillConstraint );
}
};
m_board->SynchronizeNetsAndNetClasses();

6
pcbnew/edit_track_width.cpp
View File

@ -192,7 +192,6 @@ void PCB_EDIT_FRAME::Tracks_and_Vias_Size_Event( wxCommandEvent& event )
if( ii == int( m_SelTrackWidthBox->GetCount() - 2 ) )
{
// this is the separator
m_SelTrackWidthBox->SetSelection( GetDesignSettings().GetTrackWidthIndex() );
}
else if( ii == int( m_SelTrackWidthBox->GetCount() - 1 ) )
{
@ -200,7 +199,10 @@ void PCB_EDIT_FRAME::Tracks_and_Vias_Size_Event( wxCommandEvent& event )
ShowBoardSetupDialog( _( "Tracks & Vias" ) );
}
else
{
GetDesignSettings().m_UseConnectedTrackWidth = false;
GetDesignSettings().SetTrackWidthIndex( ii );
}
break;
@ -218,7 +220,9 @@ void PCB_EDIT_FRAME::Tracks_and_Vias_Size_Event( wxCommandEvent& event )
ShowBoardSetupDialog( _( "Tracks & Vias" ) );
}
else
{
GetDesignSettings().SetViaSizeIndex( ii );
}
break;

10
pcbnew/files.cpp
View File

@ -719,9 +719,6 @@ bool PCB_EDIT_FRAME::OpenProjectFiles( const std::vector<wxString>& aFileSet, in
if( !converted )
UpdateFileHistory( GetBoard()->GetFileName() );
// Select netclass Default as current netclass (it always exists)
SetCurrentNetClass( NETCLASS::Default );
// Rebuild list of nets (full ratsnest rebuild)
GetBoard()->BuildConnectivity();
Compile_Ratsnest( true );
@ -817,9 +814,6 @@ bool PCB_EDIT_FRAME::SavePcbFile( const wxString& aFileName, bool addToHistory,
GetBoard()->SynchronizeNetsAndNetClasses();
// Select default Netclass before writing file. Useful to save default values in headers.
SetCurrentNetClass( NETCLASS::Default );
// Save various DRC parameters, such as violation severities (which may have been
// edited via the DRC dialog as well as the Board Setup dialog), DRC exclusions, etc.
SaveProjectSettings();
@ -925,10 +919,6 @@ bool PCB_EDIT_FRAME::SavePcbCopy( const wxString& aFileName, bool aCreateProject
GetBoard()->SynchronizeNetsAndNetClasses();
// Select default Netclass before writing file.
// Useful to save default values in headers
SetCurrentNetClass( NETCLASS::Default );
try
{
PLUGIN::RELEASER pi( IO_MGR::PluginFind( IO_MGR::KICAD_SEXP ) );

13
pcbnew/pcb_edit_frame.cpp
View File

@ -162,6 +162,7 @@ BEGIN_EVENT_TABLE( PCB_EDIT_FRAME, PCB_BASE_FRAME )
EVT_UPDATE_UI( ID_TOOLBARH_PCB_SELECT_LAYER, PCB_EDIT_FRAME::OnUpdateLayerSelectBox )
EVT_UPDATE_UI( ID_AUX_TOOLBAR_PCB_TRACK_WIDTH, PCB_EDIT_FRAME::OnUpdateSelectTrackWidth )
EVT_UPDATE_UI( ID_AUX_TOOLBAR_PCB_VIA_SIZE, PCB_EDIT_FRAME::OnUpdateSelectViaSize )
EVT_UPDATE_UI( ID_AUX_TOOLBAR_PCB_SELECT_AUTO_WIDTH, PCB_EDIT_FRAME::OnUpdateSelectAutoWidth )
EVT_UPDATE_UI_RANGE( ID_POPUP_PCB_SELECT_WIDTH1, ID_POPUP_PCB_SELECT_WIDTH8,
PCB_EDIT_FRAME::OnUpdateSelectTrackWidth )
EVT_UPDATE_UI_RANGE( ID_POPUP_PCB_SELECT_VIASIZE1, ID_POPUP_PCB_SELECT_VIASIZE8,
@ -889,7 +890,6 @@ void PCB_EDIT_FRAME::ShowBoardSetupDialog( const wxString& aInitialPage, const w
Prj().GetProjectFile().NetSettings().ResolveNetClassAssignments( true );
GetBoard()->SynchronizeNetsAndNetClasses();
GetBoard()->GetDesignSettings().SetCurrentNetClass( NETCLASS::Default );
SaveProjectSettings();
UpdateUserInterface();
@ -1267,17 +1267,6 @@ void PCB_EDIT_FRAME::ToPlotter( int aID )
}
bool PCB_EDIT_FRAME::SetCurrentNetClass( const wxString& aNetClassName )
{
bool change = GetDesignSettings().SetCurrentNetClass( aNetClassName );
if( change )
ReCreateAuxiliaryToolbar();
return change;
}
bool PCB_EDIT_FRAME::TestStandalone()
{
if( Kiface().IsSingle() )

13
pcbnew/pcb_edit_frame.h
View File

@ -319,6 +319,7 @@ public:
bool LayerManagerShown();
void OnUpdateSelectViaSize( wxUpdateUIEvent& aEvent );
void OnUpdateSelectTrackWidth( wxUpdateUIEvent& aEvent );
void OnUpdateSelectAutoWidth( wxUpdateUIEvent& aEvent );
void RunEeschema();
@ -423,18 +424,6 @@ public:
void ReCreateLayerBox( bool aForceResizeToolbar = true );
/**
* Function SetCurrentNetClass
* Must be called after a netclass selection (or after a netclass parameter change
* calls BOARD_DESIGN_SETTINGS::SetCurrentNetClass() and update trace width and via size
* combo boxes on main toolbar
* Initialize vias and tracks values displayed in comb boxes of the auxiliary toolbar
* and some others parameters (netclass name ....)
* @param aNetClassName = the new netclass name
* @return true if lists of tracks and vias sizes are modified
*/
bool SetCurrentNetClass( const wxString& aNetClassName );
/**
* Function OnModify
* must be called after a board change to set the modified flag.

61
pcbnew/router/pns_kicad_iface.cpp
View File

@ -191,14 +191,14 @@ bool PNS_PCBNEW_RULE_RESOLVER::IsDiffPair( const PNS::ITEM* aA, const PNS::ITEM*
bool PNS_PCBNEW_RULE_RESOLVER::QueryConstraint( PNS::CONSTRAINT_TYPE aType, const PNS::ITEM* aItemA, const PNS::ITEM* aItemB, int aLayer, PNS::CONSTRAINT* aConstraint )
bool PNS_PCBNEW_RULE_RESOLVER::QueryConstraint( PNS::CONSTRAINT_TYPE aType,
const PNS::ITEM* aItemA, const PNS::ITEM* aItemB,
int aLayer, PNS::CONSTRAINT* aConstraint )
{
std::shared_ptr<DRC_ENGINE> drcEngine = m_board->GetDesignSettings().m_DRCEngine;
if( !drcEngine )
{
return false;
}
DRC_CONSTRAINT_TYPE_T hostRuleType;
@ -216,6 +216,11 @@ bool PNS_PCBNEW_RULE_RESOLVER::QueryConstraint( PNS::CONSTRAINT_TYPE aType, cons
case PNS::CONSTRAINT_TYPE::CT_LENGTH:
hostRuleType = DRC_CONSTRAINT_TYPE_LENGTH;
break;
case PNS::CONSTRAINT_TYPE::CT_VIA_DIAMETER:
hostRuleType = DRC_CONSTRAINT_TYPE_VIA_DIAMETER;
break;
case PNS::CONSTRAINT_TYPE::CT_VIA_HOLE:
hostRuleType = DRC_CONSTRAINT_TYPE_HOLE_SIZE;
default:
return false; // should not happen
}
@ -223,9 +228,7 @@ bool PNS_PCBNEW_RULE_RESOLVER::QueryConstraint( PNS::CONSTRAINT_TYPE aType, cons
const BOARD_ITEM* parentA = aItemA ? aItemA->Parent() : nullptr;
const BOARD_ITEM* parentB = aItemB ? aItemB->Parent() : nullptr;
DRC_CONSTRAINT hostConstraint = drcEngine->EvalRulesForItems( hostRuleType,
parentA,
parentB,
DRC_CONSTRAINT hostConstraint = drcEngine->EvalRulesForItems( hostRuleType, parentA, parentB,
(PCB_LAYER_ID) aLayer );
if( hostConstraint.IsNull() )
@ -236,6 +239,8 @@ bool PNS_PCBNEW_RULE_RESOLVER::QueryConstraint( PNS::CONSTRAINT_TYPE aType, cons
case PNS::CONSTRAINT_TYPE::CT_CLEARANCE:
case PNS::CONSTRAINT_TYPE::CT_WIDTH:
case PNS::CONSTRAINT_TYPE::CT_DIFF_PAIR_GAP:
case PNS::CONSTRAINT_TYPE::CT_VIA_DIAMETER:
case PNS::CONSTRAINT_TYPE::CT_VIA_HOLE:
aConstraint->m_Value = hostConstraint.GetValue();
aConstraint->m_RuleName = hostConstraint.GetName();
aConstraint->m_Type = aType;
@ -321,11 +326,6 @@ bool PNS_KICAD_IFACE_BASE::ImportSizes( PNS::SIZES_SETTINGS& aSizes, PNS::ITEM*
{
BOARD_DESIGN_SETTINGS &bds = m_board->GetDesignSettings();
int net = aNet;
if( aStartItem )
net = aStartItem->Net();
int trackWidth = 0;
if( bds.m_UseConnectedTrackWidth && aStartItem != nullptr )
@ -336,12 +336,14 @@ bool PNS_KICAD_IFACE_BASE::ImportSizes( PNS::SIZES_SETTINGS& aSizes, PNS::ITEM*
if( !trackWidth && bds.UseNetClassTrack() && aStartItem ) // netclass value
{
PNS::CONSTRAINT constraint;
bool ok = m_ruleResolver->QueryConstraint( PNS::CONSTRAINT_TYPE::CT_WIDTH, aStartItem,
nullptr, aStartItem->Layer(), &constraint );
bool ok = m_ruleResolver->QueryConstraint( PNS::CONSTRAINT_TYPE::CT_WIDTH,
aStartItem, nullptr, aStartItem->Layer(),
&constraint );
if( ok )
{
trackWidth = constraint.m_Value.HasOpt() ? constraint.m_Value.Opt() : constraint.m_Value.Min();
trackWidth = constraint.m_Value.HasOpt() ? constraint.m_Value.Opt()
: constraint.m_Value.Min();
}
}
@ -357,8 +359,25 @@ bool PNS_KICAD_IFACE_BASE::ImportSizes( PNS::SIZES_SETTINGS& aSizes, PNS::ITEM*
if( bds.UseNetClassVia() ) // netclass value
{
viaDiameter = 0; //netClass->GetViaDiameter();
viaDrill = 0; //netClass->GetViaDrill(); // fixme
PNS::CONSTRAINT diaConstraint, drillConstraint;
bool okDia = m_ruleResolver->QueryConstraint( PNS::CONSTRAINT_TYPE::CT_VIA_DIAMETER,
aStartItem, nullptr, aStartItem->Layer(),
&diaConstraint );
bool okDrill = m_ruleResolver->QueryConstraint( PNS::CONSTRAINT_TYPE::CT_VIA_HOLE,
aStartItem, nullptr, aStartItem->Layer(),
&drillConstraint );
if( okDia )
{
viaDiameter = diaConstraint.m_Value.HasOpt() ? diaConstraint.m_Value.Opt()
: diaConstraint.m_Value.Min();
}
if( okDrill )
{
viaDrill = drillConstraint.m_Value.HasOpt() ? drillConstraint.m_Value.Opt()
: drillConstraint.m_Value.Min();
}
}
else
{
@ -376,10 +395,12 @@ bool PNS_KICAD_IFACE_BASE::ImportSizes( PNS::SIZES_SETTINGS& aSizes, PNS::ITEM*
if( bds.UseNetClassDiffPair() && aStartItem )
{
PNS::CONSTRAINT widthConstraint, gapConstraint;
bool okWidth = m_ruleResolver->QueryConstraint( PNS::CONSTRAINT_TYPE::CT_WIDTH, aStartItem,
nullptr, aStartItem->Layer(), &widthConstraint );
bool okGap = m_ruleResolver->QueryConstraint( PNS::CONSTRAINT_TYPE::CT_DIFF_PAIR_GAP, aStartItem,
nullptr, aStartItem->Layer(), &gapConstraint );
bool okWidth = m_ruleResolver->QueryConstraint( PNS::CONSTRAINT_TYPE::CT_WIDTH,
aStartItem, nullptr, aStartItem->Layer(),
&widthConstraint );
bool okGap = m_ruleResolver->QueryConstraint( PNS::CONSTRAINT_TYPE::CT_DIFF_PAIR_GAP,
aStartItem, nullptr, aStartItem->Layer(),
&gapConstraint );
if( okWidth )
diffPairWidth = widthConstraint.m_Value.OptThenMin();

11
pcbnew/router/router_tool.cpp
View File

@ -858,17 +858,6 @@ bool ROUTER_TOOL::prepareInteractive()
editFrame->SetActiveLayer( ToLAYER_ID( routingLayer ) );
// for some reason I don't understand, GetNetclass() may return null sometimes...
if( m_startItem && m_startItem->Net() >= 0 &&
m_startItem->Parent() && m_startItem->Parent()->GetNetClass() )
{
highlightNet( true, m_startItem->Net() );
// Update track width and via size shown in main toolbar comboboxes
editFrame->SetCurrentNetClass( m_startItem->Parent()->GetNetClass()->GetName() );
}
else
editFrame->SetCurrentNetClass( NETCLASS::Default );
controls()->ForceCursorPosition( false );
controls()->SetAutoPan( true );

46
pcbnew/toolbars_pcb_editor.cpp
View File

@ -594,17 +594,15 @@ void PCB_EDIT_FRAME::UpdateTrackWidthSelectBox( wxChoice* aTrackWidthSelectBox,
aTrackWidthSelectBox->Clear();
for( unsigned ii = 0; ii < GetDesignSettings().m_TrackWidthList.size(); ii++ )
aTrackWidthSelectBox->Append( _( "Track: use netclass width" ) );
for( unsigned ii = 1; ii < GetDesignSettings().m_TrackWidthList.size(); ii++ )
{
int size = GetDesignSettings().m_TrackWidthList[ii];
msg.Printf( _( "Track: %s (%s)" ), ComboBoxUnits( primaryUnit, size ),
ComboBoxUnits( secondaryUnit, size ) );
// Mark the netclass track width value (the first in list)
if( ii == 0 )
msg << wxT( " *" );
aTrackWidthSelectBox->Append( msg );
}
@ -648,6 +646,8 @@ void PCB_EDIT_FRAME::UpdateViaSizeSelectBox( wxChoice* aViaSizeSelectBox, bool a
secondaryUnit = EDA_UNITS::MILS;
}
aViaSizeSelectBox->Append( _( "Via: use netclass sizes" ) );
for( unsigned ii = 0; ii < GetDesignSettings().m_ViasDimensionsList.size(); ii++ )
{
VIA_DIMENSION viaDimension = GetDesignSettings().m_ViasDimensionsList[ii];
@ -671,10 +671,6 @@ void PCB_EDIT_FRAME::UpdateViaSizeSelectBox( wxChoice* aViaSizeSelectBox, bool a
msg.Printf( _( "Via: %s (%s)" ), priStr, secStr );
// Mark the netclass via size value (the first in list)
if( ii == 0 )
msg << wxT( " *" );
aViaSizeSelectBox->Append( msg );
}
@ -722,8 +718,16 @@ void PCB_EDIT_FRAME::OnUpdateSelectTrackWidth( wxUpdateUIEvent& aEvent )
{
if( aEvent.GetId() == ID_AUX_TOOLBAR_PCB_TRACK_WIDTH )
{
if( m_SelTrackWidthBox->GetSelection() != (int) GetDesignSettings().GetTrackWidthIndex() )
m_SelTrackWidthBox->SetSelection( GetDesignSettings().GetTrackWidthIndex() );
BOARD_DESIGN_SETTINGS& bds = GetDesignSettings();
int sel;
if( bds.m_UseConnectedTrackWidth || bds.UseCustomTrackViaSize() )
sel = wxNOT_FOUND;
else
sel = bds.GetTrackWidthIndex();
if( m_SelTrackWidthBox->GetSelection() != sel )
m_SelTrackWidthBox->SetSelection( sel );
}
}
@ -732,12 +736,28 @@ void PCB_EDIT_FRAME::OnUpdateSelectViaSize( wxUpdateUIEvent& aEvent )
{
if( aEvent.GetId() == ID_AUX_TOOLBAR_PCB_VIA_SIZE )
{
if( m_SelViaSizeBox->GetSelection() != (int) GetDesignSettings().GetViaSizeIndex() )
m_SelViaSizeBox->SetSelection( GetDesignSettings().GetViaSizeIndex() );
BOARD_DESIGN_SETTINGS& bds = GetDesignSettings();
int sel = 0;
if( bds.UseCustomTrackViaSize() )
sel = wxNOT_FOUND;
else
sel = bds.GetViaSizeIndex();
if( m_SelViaSizeBox->GetSelection() != sel )
m_SelViaSizeBox->SetSelection( sel );
}
}
void PCB_EDIT_FRAME::OnUpdateSelectAutoWidth( wxUpdateUIEvent& aEvent )
{
BOARD_DESIGN_SETTINGS& bds = GetDesignSettings();
aEvent.Check( bds.m_UseConnectedTrackWidth && !bds.UseCustomTrackViaSize() );
}
void PCB_EDIT_FRAME::OnUpdateLayerSelectBox( wxUpdateUIEvent& aEvent )
{
if( m_SelLayerBox->GetLayerSelection() != GetActiveLayer() )