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When routing don't give NPTH holes a copper clearance. 

Fixes https://gitlab.com/kicad/code/kicad/issues/6903
This commit is contained in:
Jeff Young 2021-01-02 16:32:03 +00:00
parent b5e7611696
commit 068af7d328
1 changed files with 21 additions and 3 deletions
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24
pcbnew/router/pns_kicad_iface.cpp
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@ -155,6 +155,20 @@ bool PNS_PCBNEW_RULE_RESOLVER::IsDiffPair( const PNS::ITEM* aA, const PNS::ITEM*
} }
bool isCopper( const PNS::ITEM* aItem )
{
BOARD_ITEM* parent = aItem->Parent();
if( parent && parent->Type() == PCB_PAD_T )
{
PAD* pad = static_cast<PAD*>( parent );
return pad->IsOnCopperLayer() && pad->GetAttribute() != PAD_ATTRIB_NPTH;
}
return true;
}
bool isEdge( const PNS::ITEM* aItem ) bool isEdge( const PNS::ITEM* aItem )
{ {
return aItem->Layer() == Edge_Cuts || aItem->Layer() == Margin; return aItem->Layer() == Edge_Cuts || aItem->Layer() == Margin;
@ -280,10 +294,14 @@ int PNS_PCBNEW_RULE_RESOLVER::Clearance( const PNS::ITEM* aA, const PNS::ITEM* a
} }
} }
if( QueryConstraint( PNS::CONSTRAINT_TYPE::CT_CLEARANCE, aA, aB, aA->Layer(), if( isCopper( aA ) && ( !aB || isCopper( aB ) ) )
&constraint ) )
{ {
rv = constraint.m_Value.Min(); if( QueryConstraint( PNS::CONSTRAINT_TYPE::CT_CLEARANCE, aA, aB, aA->Layer(),
&constraint ) )
{
if( constraint.m_Value.Min() > rv )
rv = constraint.m_Value.Min();
}
} }
if( isEdge( aA ) || ( aB && isEdge( aB ) ) ) if( isEdge( aA ) || ( aB && isEdge( aB ) ) )