3D model export: Improve 3D layer placement calculation algorithm.
Fixes https://gitlab.com/kicad/code/kicad/-/issues/18035
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@ -916,6 +916,46 @@ bool STEP_PCB_MODEL::AddTrackSegment( const PCB_TRACK* aTrack, const VECTOR2D& a
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void STEP_PCB_MODEL::getLayerZPlacement( const PCB_LAYER_ID aLayer, double& aZPos,
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double& aThickness )
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{
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// Offsets above copper in mm
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static const double c_silkscreenAboveCopper = 0.04;
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static const double c_soldermaskAboveCopper = 0.015;
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if( IsCopperLayer( aLayer ) )
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{
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getCopperLayerZPlacement( aLayer, aZPos, aThickness );
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}
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else if( IsFrontLayer( aLayer ) )
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{
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double f_pos, f_thickness;
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getCopperLayerZPlacement( F_Cu, f_pos, f_thickness );
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double top = std::max( f_pos, f_pos + f_thickness );
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if( aLayer == F_SilkS )
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aZPos = top + c_silkscreenAboveCopper;
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else
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aZPos = top + c_soldermaskAboveCopper;
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aThickness = 0.0; // Normal points up
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}
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else if( IsBackLayer( aLayer ) )
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{
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double b_pos, b_thickness;
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getCopperLayerZPlacement( B_Cu, b_pos, b_thickness );
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double bottom = std::min( b_pos, b_pos + b_thickness );
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if( aLayer == B_SilkS )
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aZPos = bottom - c_silkscreenAboveCopper;
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else
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aZPos = bottom - c_soldermaskAboveCopper;
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aThickness = -0.0; // Normal points down
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}
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}
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void STEP_PCB_MODEL::getCopperLayerZPlacement( const PCB_LAYER_ID aLayer, double& aZPos,
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double& aThickness )
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{
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int z = 0;
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int thickness = 0;
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@ -923,14 +963,22 @@ void STEP_PCB_MODEL::getLayerZPlacement( const PCB_LAYER_ID aLayer, double& aZPo
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const std::vector<BOARD_STACKUP_ITEM*>& materials = m_stackup.GetList();
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// Iterate from bottom to top
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for( auto it = materials.rbegin(); it != materials.rend(); ++it )
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{
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const BOARD_STACKUP_ITEM* item = *it;
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if( item->GetType() == BS_ITEM_TYPE_COPPER )
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{
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if( aLayer == B_Cu )
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{
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// This is the first encountered layer
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thickness = -item->GetThickness();
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break;
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}
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// Inner copper position is usually inside prepreg
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if( ( wasPrepreg || aLayer == B_Cu ) && aLayer != F_Cu )
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if( wasPrepreg && item->GetBrdLayerId() != F_Cu )
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thickness = -item->GetThickness();
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else
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thickness = item->GetThickness();
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@ -938,7 +986,8 @@ void STEP_PCB_MODEL::getLayerZPlacement( const PCB_LAYER_ID aLayer, double& aZPo
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if( item->GetBrdLayerId() == aLayer )
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break;
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z += thickness;
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if( item->GetBrdLayerId() != B_Cu )
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z += item->GetThickness();
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}
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else if( item->GetType() == BS_ITEM_TYPE_DIELECTRIC )
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{
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@ -946,8 +995,11 @@ void STEP_PCB_MODEL::getLayerZPlacement( const PCB_LAYER_ID aLayer, double& aZPo
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// Dielectric can have sub-layers. Layer 0 is the main layer
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// Not frequent, but possible
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thickness = 0;
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for( int idx = 0; idx < item->GetSublayersCount(); idx++ )
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z += item->GetThickness( idx );
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thickness += item->GetThickness( idx );
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z += thickness;
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}
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}
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@ -203,6 +203,8 @@ private:
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void getLayerZPlacement( const PCB_LAYER_ID aLayer, double& aZPos, double& aThickness );
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void getCopperLayerZPlacement( const PCB_LAYER_ID aLayer, double& aZPos, double& aThickness );
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void getBoardBodyZPlacement( double& aZPos, double& aThickness );
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/**
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