Consistency.
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@ -731,6 +731,29 @@ void ZONE_FILLER::buildCopperItemClearances( const ZONE_CONTAINER* aZone, PCB_LA
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// Add non-connected pad clearances
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//
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auto knockoutPad =
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[&]( D_PAD* aPad )
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{
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if( aPad->GetBoundingBox().Intersects( zone_boundingbox ) )
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{
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int gap;
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// for pads having the same netcode as the zone, the net clearance has no
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// meaning so use the greater of the zone clearance and the thermal relief
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if( aPad->GetNetCode() > 0 && aPad->GetNetCode() == aZone->GetNetCode() )
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{
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gap = std::max( zone_clearance, aZone->GetThermalReliefGap( aPad ) );
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}
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else
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{
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gap = evalRulesForItems( DRC_CONSTRAINT_TYPE_CLEARANCE, aZone, aPad,
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aLayer );
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}
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addKnockout( aPad, aLayer, gap, aHoles );
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}
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};
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for( MODULE* module : m_board->Modules() )
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{
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for( D_PAD* pad : module->Pads() )
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@ -747,30 +770,47 @@ void ZONE_FILLER::buildCopperItemClearances( const ZONE_CONTAINER* aZone, PCB_LA
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if( pad->GetNetCode() != aZone->GetNetCode() || pad->GetNetCode() <= 0
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|| aZone->GetPadConnection( pad ) == ZONE_CONNECTION::NONE )
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{
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if( pad->GetBoundingBox().Intersects( zone_boundingbox ) )
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{
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int gap;
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// for pads having the same netcode as the zone, the net clearance has no
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// meaning so use the greater of the zone clearance and the thermal relief
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if( pad->GetNetCode() > 0 && pad->GetNetCode() == aZone->GetNetCode() )
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{
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gap = std::max( zone_clearance, aZone->GetThermalReliefGap( pad ) );
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}
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else
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{
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gap = evalRulesForItems( DRC_CONSTRAINT_TYPE_CLEARANCE, aZone, pad,
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aLayer );
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}
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addKnockout( pad, aLayer, gap, aHoles );
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}
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knockoutPad( pad );
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}
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}
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}
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// Add non-connected track clearances
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//
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auto knockoutTrack =
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[&]( TRACK* aTrack )
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{
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if( aTrack->GetBoundingBox().Intersects( zone_boundingbox ) )
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{
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int gap = evalRulesForItems( DRC_CONSTRAINT_TYPE_CLEARANCE, aZone, aTrack,
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aLayer );
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gap += extra_margin;
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if( aTrack->Type() == PCB_VIA_T )
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{
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VIA* via = static_cast<VIA*>( aTrack );
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if( !via->FlashLayer( aLayer ) )
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{
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int radius = via->GetDrillValue() / 2 + bds.GetHolePlatingThickness();
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TransformCircleToPolygon( aHoles, via->GetPosition(), radius + gap,
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m_maxError, ERROR_OUTSIDE );
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}
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else
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{
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via->TransformShapeWithClearanceToPolygon( aHoles, aLayer, gap,
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m_maxError, ERROR_OUTSIDE );
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}
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}
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else
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{
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aTrack->TransformShapeWithClearanceToPolygon( aHoles, aLayer, gap,
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m_maxError, ERROR_OUTSIDE );
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}
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}
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};
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for( TRACK* track : m_board->Tracks() )
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{
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if( !track->IsOnLayer( aLayer ) )
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@ -779,40 +819,13 @@ void ZONE_FILLER::buildCopperItemClearances( const ZONE_CONTAINER* aZone, PCB_LA
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if( track->GetNetCode() == aZone->GetNetCode() && ( aZone->GetNetCode() != 0) )
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continue;
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if( track->GetBoundingBox().Intersects( zone_boundingbox ) )
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{
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int gap = evalRulesForItems( DRC_CONSTRAINT_TYPE_CLEARANCE, aZone, track, aLayer );
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gap += extra_margin;
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if( track->Type() == PCB_VIA_T )
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{
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VIA* via = static_cast<VIA*>( track );
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if( !via->FlashLayer( aLayer ) )
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{
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int radius = via->GetDrillValue() / 2 + bds.GetHolePlatingThickness() + gap;
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TransformCircleToPolygon( aHoles, via->GetPosition(), radius, m_maxError,
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ERROR_OUTSIDE );
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}
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else
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{
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via->TransformShapeWithClearanceToPolygon( aHoles, aLayer, gap, m_maxError,
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ERROR_OUTSIDE );
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}
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}
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else
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{
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track->TransformShapeWithClearanceToPolygon( aHoles, aLayer, gap, m_maxError,
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ERROR_OUTSIDE );
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}
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}
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knockoutTrack( track );
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}
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// Add graphic item clearances. They are by definition unconnected, and have no clearance
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// definitions of their own.
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//
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auto doGraphicItem =
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auto knockoutGraphic =
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[&]( BOARD_ITEM* aItem )
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{
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// A item on the Edge_Cuts is always seen as on any layer:
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@ -836,15 +849,15 @@ void ZONE_FILLER::buildCopperItemClearances( const ZONE_CONTAINER* aZone, PCB_LA
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for( MODULE* module : m_board->Modules() )
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{
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doGraphicItem( &module->Reference() );
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doGraphicItem( &module->Value() );
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knockoutGraphic( &module->Reference() );
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knockoutGraphic( &module->Value() );
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for( BOARD_ITEM* item : module->GraphicalItems() )
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doGraphicItem( item );
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knockoutGraphic( item );
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}
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for( BOARD_ITEM* item : m_board->Drawings() )
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doGraphicItem( item );
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knockoutGraphic( item );
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// Add non-connected zone clearances
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//
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