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Save hole-to-hole-min to file.

This commit is contained in:
Jeff Young 2020-05-18 23:55:10 +01:00
parent 4e2e280bf4
commit 0aaccfbb28
5 changed files with 11 additions and 4 deletions
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1
common/pcb.keywords
View File

@ -123,6 +123,7 @@ hatch_orientation
hatch_smoothing_level hatch_smoothing_level
hatch_smoothing_value hatch_smoothing_value
hide hide
hole_to_hole_min
italic italic
justify justify
keepout keepout

4
pcbnew/files.cpp
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@ -587,11 +587,9 @@ bool PCB_EDIT_FRAME::OpenProjectFiles( const std::vector<wxString>& aFileSet, in
bds.SetCopperEdgeClearance( inferLegacyEdgeClearance( loadedBoard ) ); bds.SetCopperEdgeClearance( inferLegacyEdgeClearance( loadedBoard ) );
} }
// 6.0 TODO: some of the 5.1 settings still haven't moved because they're waiting on // We store the severities in the config to keep board-file changes to a minimum
// the new DRC architecture
BOARD_DESIGN_SETTINGS& configBds = GetBoard()->GetDesignSettings(); BOARD_DESIGN_SETTINGS& configBds = GetBoard()->GetDesignSettings();
bds.m_DRCSeverities = configBds.m_DRCSeverities; bds.m_DRCSeverities = configBds.m_DRCSeverities;
bds.m_HoleToHoleMin = configBds.m_HoleToHoleMin;
SetBoard( loadedBoard ); SetBoard( loadedBoard );

2
pcbnew/kicad_plugin.cpp
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@ -515,6 +515,8 @@ void PCB_IO::formatSetup( BOARD* aBoard, int aNestLevel ) const
FormatInternalUnits( dsnSettings.m_ViasMinSize ).c_str() ); FormatInternalUnits( dsnSettings.m_ViasMinSize ).c_str() );
m_out->Print( aNestLevel+1, "(through_hole_min %s)\n", m_out->Print( aNestLevel+1, "(through_hole_min %s)\n",
FormatInternalUnits( dsnSettings.m_MinThroughDrill ).c_str() ); FormatInternalUnits( dsnSettings.m_MinThroughDrill ).c_str() );
m_out->Print( aNestLevel+1, "(hole_to_hole_min %s)\n",
FormatInternalUnits( dsnSettings.m_HoleToHoleMin ).c_str() );
// Save current default via size, for compatibility with older Pcbnew version; // Save current default via size, for compatibility with older Pcbnew version;
m_out->Print( aNestLevel+1, "(via_size %s)\n", m_out->Print( aNestLevel+1, "(via_size %s)\n",

3
pcbnew/kicad_plugin.h
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@ -67,7 +67,8 @@ class TEXTE_PCB;
//#define SEXPR_BOARD_FILE_VERSION 20191123 // pin function in pads //#define SEXPR_BOARD_FILE_VERSION 20191123 // pin function in pads
//#define SEXPR_BOARD_FILE_VERSION 20200104 // pad property for fabrication //#define SEXPR_BOARD_FILE_VERSION 20200104 // pad property for fabrication
//#define SEXPR_BOARD_FILE_VERSION 20200119 // arcs in tracks //#define SEXPR_BOARD_FILE_VERSION 20200119 // arcs in tracks
#define SEXPR_BOARD_FILE_VERSION 20200512 // page -> paper //#define SEXPR_BOARD_FILE_VERSION 20200512 // page -> paper
#define SEXPR_BOARD_FILE_VERSION 20200518 // save hole_to_hole_min
#define CTL_STD_LAYER_NAMES (1 << 0) ///< Use English Standard layer names #define CTL_STD_LAYER_NAMES (1 << 0) ///< Use English Standard layer names
#define CTL_OMIT_NETS (1 << 1) ///< Omit pads net names (useless in library) #define CTL_OMIT_NETS (1 << 1) ///< Omit pads net names (useless in library)

5
pcbnew/pcb_parser.cpp
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@ -1519,6 +1519,11 @@ void PCB_PARSER::parseSetup()
NeedRIGHT(); NeedRIGHT();
break; break;
case T_hole_to_hole_min:
designSettings.m_HoleToHoleMin = parseBoardUnits( T_hole_to_hole_min );
NeedRIGHT();
break;
case T_user_via: case T_user_via:
{ {
int viaSize = parseBoardUnits( "user via size" ); int viaSize = parseBoardUnits( "user via size" );