STEP export: reverse Wire when adding it to Face as a hole.
Better fix for https://gitlab.com/kicad/code/kicad/-/issues/17446
(cherry picked from commit 1264230973
)
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@ -1429,6 +1429,8 @@ bool STEP_PCB_MODEL::MakeShapes( std::vector<TopoDS_Shape>& aShapes, const SHAPE
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-pcbIUScale.IUTomm( aKiCoords.y - aOrigin.y ), aZposition );
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};
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gp_Pln basePlane( gp_Pnt( 0.0, 0.0, aZposition ), gp::DZ() );
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for( const SHAPE_POLY_SET::POLYGON& polygon : simplified.CPolygons() )
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{
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auto makeWireFromChain = [&]( BRepLib_MakeWire& aMkWire,
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@ -1654,27 +1656,33 @@ bool STEP_PCB_MODEL::MakeShapes( std::vector<TopoDS_Shape>& aShapes, const SHAPE
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if( contId == 0 ) // Outline
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{
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if( !wire.IsNull() )
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mkFace = BRepBuilderAPI_MakeFace( wire );
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{
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mkFace = BRepBuilderAPI_MakeFace( basePlane, wire );
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}
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else
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{
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ReportMessage( wxString::Format( _( "\n** Outline skipped **\n" ) ) );
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ReportMessage( wxString::Format( wxT( "\n** Outline skipped **\n" ) ) );
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ReportMessage( wxString::Format( _( "z: %g; bounding box: %s\n" ),
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ReportMessage( wxString::Format( wxT( "z: %g; bounding box: %s\n" ),
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aZposition,
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formatBBox( polygon[contId].BBox() ) ) );
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continue;
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break;
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}
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}
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else // Hole
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{
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if( !wire.IsNull() )
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{
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wire.Reverse();
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mkFace.Add( wire );
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}
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else
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{
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ReportMessage( wxString::Format( _( "\n** Hole skipped **\n" ) ) );
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ReportMessage( wxString::Format( wxT( "\n** Hole skipped **\n" ) ) );
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ReportMessage( wxString::Format( _( "z: %g; bounding box: %s\n" ),
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ReportMessage( wxString::Format( wxT( "z: %g; bounding box: %s\n" ),
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aZposition,
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formatBBox( polygon[contId].BBox() ) ) );
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}
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@ -1739,7 +1747,7 @@ bool STEP_PCB_MODEL::CreatePCB( SHAPE_POLY_SET& aOutline, VECTOR2D aOrigin, bool
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double boardZPos;
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getBoardBodyZPlacement( boardZPos, boardThickness );
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#if 0
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#if 1
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// This code should work, and it is working most of time
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// However there are issues if the main outline is a circle with holes:
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// holes from vias and pads are not working
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