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Move compound graphics tests back out to the shared path.

This commit is contained in:
Jeff Young 2020-10-12 10:27:12 +01:00
parent 380534807b
commit 1bcefe420a
1 changed files with 21 additions and 33 deletions
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54
pcbnew/drc/drc_test_provider_silk_clearance.cpp
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@ -23,6 +23,7 @@
#include <common.h> #include <common.h>
#include <class_board.h> #include <class_board.h>
#include <pcb_shape.h>
#include <geometry/polygon_test_point_inside.h> #include <geometry/polygon_test_point_inside.h>
#include <geometry/seg.h> #include <geometry/seg.h>
@ -120,6 +121,12 @@ bool DRC_TEST_PROVIDER_SILK_CLEARANCE::Run()
if( m_drcEngine->IsErrorLimitExceeded( DRCE_OVERLAPPING_SILK ) ) if( m_drcEngine->IsErrorLimitExceeded( DRCE_OVERLAPPING_SILK ) )
return false; return false;
if ( isInvisibleText( aRefItem->parent ) )
return true;
if ( isInvisibleText( aTestItem->parent ) )
return true;
auto constraint = m_drcEngine->EvalRulesForItems( DRC_CONSTRAINT_TYPE_SILK_CLEARANCE, auto constraint = m_drcEngine->EvalRulesForItems( DRC_CONSTRAINT_TYPE_SILK_CLEARANCE,
aRefItem->parent, aRefItem->parent,
aTestItem->parent, aTestItem->parent,
@ -132,47 +139,28 @@ bool DRC_TEST_PROVIDER_SILK_CLEARANCE::Run()
if( minClearance == 0 ) if( minClearance == 0 )
{ {
// MinClearance == 0 means the author didn't specify anything and we want to // MinClearance == 0 means the author didn't specify anything and we want
// use heuristics for a silk : silk collision. // to perform a basic silk : silk collision test.
// //
// MinClearance > 0 means we're in an author-specified condition that the // aLayers.first is always a silk layer, so we just need to check that
// rule matched, and we don't want any heuristics.
// We know that aLayers.first is a silk layer, so we just need to check that
// aLayers.second matches. // aLayers.second matches.
//
if( aLayers.second != aLayers.first ) if( aLayers.second != aLayers.first )
return true; return true;
}
KICAD_T refType = aRefItem->parent->Type(); // Graphics are often compound shapes so ignore collisions between shapes in a
KICAD_T testType = aTestItem->parent->Type(); // single footprint or on the board.
PCB_SHAPE* refGraphic = dynamic_cast<PCB_SHAPE*>( aRefItem->parent );
PCB_SHAPE* testGraphic = dynamic_cast<PCB_SHAPE*>( aTestItem->parent );
MODULE *parentModRef = nullptr; if( refGraphic && testGraphic )
MODULE *parentModTest = nullptr; {
MODULE *refParentFP = dynamic_cast<MODULE*>( refGraphic->GetParent() );
MODULE *testParentFP = dynamic_cast<MODULE*>( testGraphic->GetParent() );
if ( isInvisibleText( aRefItem->parent ) ) if( refParentFP == testParentFP ) // also true when both are nullptr
return true; return true;
if ( isInvisibleText( aTestItem->parent ) )
return true;
if( refType == PCB_FP_SHAPE_T || refType == PCB_FP_TEXT_T )
parentModRef = static_cast<MODULE*> ( aRefItem->parent->GetParent() );
if( testType == PCB_FP_SHAPE_T || testType == PCB_FP_TEXT_T )
parentModTest = static_cast<MODULE*> ( aTestItem->parent->GetParent() );
// Silkscreen drawings within the same module (or globally on the board)
// don't report clearance errors. Everything else does.
if( parentModRef && parentModRef == parentModTest )
{
if( refType == PCB_FP_SHAPE_T && testType == PCB_FP_SHAPE_T )
return true;
}
else if( !parentModRef && !parentModTest )
{
if( refType == PCB_SHAPE_T && testType == PCB_SHAPE_T )
return true;
}
} }
if( !aRefItem->shape->Collide( aTestItem->shape, minClearance, &actual, &pos ) ) if( !aRefItem->shape->Collide( aTestItem->shape, minClearance, &actual, &pos ) )