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Add SPICE regression test.

This commit is contained in:
Jeff Young 2023-01-21 19:32:00 +00:00
parent 259e382041
commit 241dc0d96b
8 changed files with 2686 additions and 7 deletions
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6
qa/data/eeschema/TL072-dual.lib Normal file
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@ -0,0 +1,6 @@
* A dual opamp ngspice model
.subckt TL072c 1out 1in- 1in+ vcc- 2in+ 2in- 2out vcc+
.include TL072.301
XU1A 1in+ 1in- vcc+ vcc- 1out TL072
XU1B 2in+ 2in- vcc+ vcc- 2out TL072
.ends

43
qa/data/eeschema/TL072.301 Normal file
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@ -0,0 +1,43 @@
* TL072 OPERATIONAL AMPLIFIER "MACROMODEL" SUBCIRCUIT
* CREATED USING PARTS RELEASE 4.01 ON 06/16/89 AT 13:08
* (REV N/A) SUPPLY VOLTAGE: +/-15V
* CONNECTIONS: NON-INVERTING INPUT
* | INVERTING INPUT
* | | POSITIVE POWER SUPPLY
* | | | NEGATIVE POWER SUPPLY
* | | | | OUTPUT
* | | | | |
.SUBCKT TL072 1 2 3 4 5
*
C1 11 12 3.498E-12
C2 6 7 15.00E-12
DC 5 53 DX
DE 54 5 DX
DLP 90 91 DX
DLN 92 90 DX
DP 4 3 DX
EGND 99 0 POLY(2) (3,0) (4,0) 0 .5 .5
FB 7 99 POLY(5) VB VC VE VLP VLN 0 4.715E6 -5E6 5E6 5E6 -5E6
GA 6 0 11 12 282.8E-6
GCM 0 6 10 99 8.942E-9
ISS 3 10 DC 195.0E-6
HLIM 90 0 VLIM 1K
J1 11 2 10 JX
J2 12 1 10 JX
R2 6 9 100.0E3
RD1 4 11 3.536E3
RD2 4 12 3.536E3
RO1 8 5 150
RO2 7 99 150
RP 3 4 2.143E3
RSS 10 99 1.026E6
VB 9 0 DC 0
VC 3 53 DC 2.200
VE 54 4 DC 2.200
VLIM 7 8 DC 0
VLP 91 0 DC 25
VLN 0 92 DC 25
.MODEL DX D(IS=800.0E-18)
.MODEL JX PJF(IS=15.00E-12 BETA=270.1E-6 VTO=-1)
.ENDS


20
qa/data/eeschema/VDMOS_models.lib Normal file
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@ -0,0 +1,20 @@
.model IRFP240 VDMOS nchan
+ Vto=4 Kp=5.9 Lambda=.001 Theta=0.015 ksubthres=.27
+ Rd=61m Rs=18m Rg=3 Rds=1e7
+ Cgdmax=2.45n Cgdmin=10p a=0.3 Cgs=1.2n
+ Is=60p N=1.1 Rb=14m XTI=3
+ Cjo=1.5n Vj=0.8 m=0.5
+ tcvth=0.0065 MU=-1.27 texp0=1.5
+ Rthjc=0.4 Cthj=0.1
+ mtriode=0.8
.model IRFP9240 VDMOS pchan
+ Vto=-4 Kp=8.8 Lambda=.003 Theta=0.08 ksubthres=.35
+ Rd=180m Rs=50m Rg=3 Rds=1e7
+ Cgdmax=1.25n Cgdmin=50p a=0.23 Cgs=1.15n
+ Is=150p N=1.3 Rb=16m XTI=2
+ Cjo=1.3n Vj=0.8 m=0.5
+ tcvth=0.004 MU=-1.27 texp0=1.5
+ Rthjc=0.4 Cthj=0.1
+ mtriode=0.6
+ tnom=29

28
qa/data/eeschema/issue13112.kicad_pro
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@ -1,6 +1,8 @@
{
"board": {
"layer_presets": []
"3dviewports": [],
"layer_presets": [],
"viewports": []
},
"boards": [],
"cvpcb": {
@ -184,18 +186,23 @@
"rule_severities": {
"bus_definition_conflict": "error",
"bus_entry_needed": "error",
"bus_label_syntax": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"conflicting_netclasses": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"endpoint_off_grid": "warning",
"extra_units": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"missing_bidi_pin": "warning",
"missing_input_pin": "warning",
"missing_power_pin": "error",
"missing_unit": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
@ -205,6 +212,7 @@
"pin_to_pin": "warning",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"simulation_model_issue": "error",
"unannotated": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
@ -216,13 +224,13 @@
"pinned_symbol_libs": []
},
"meta": {
"filename": "bip-osc.kicad_pro",
"filename": "issue13112.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12.0,
"bus_width": 12,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
@ -236,13 +244,15 @@
"track_width": 0.25,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6.0
"wire_width": 6
}
],
"meta": {
"version": 2
"version": 3
},
"net_colors": null
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": []
},
"pcbnew": {
"last_paths": {
@ -258,6 +268,8 @@
"schematic": {
"annotate_start_num": 0,
"drawing": {
"dashed_lines_dash_length_ratio": 12.0,
"dashed_lines_gap_length_ratio": 3.0,
"default_line_thickness": 6.0,
"default_text_size": 50.0,
"field_names": [],
@ -290,6 +302,8 @@
"plot_directory": "",
"spice_adjust_passive_values": false,
"spice_external_command": "C:\\Spice64\\bin\\ngspice \"%I\"",
"spice_save_all_currents": false,
"spice_save_all_voltages": false,
"subpart_first_id": 65,
"subpart_id_separator": 0
},

342
qa/data/eeschema/issue13162.kicad_pro Normal file
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@ -0,0 +1,342 @@
{
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {
"board_outline_line_width": 0.1,
"copper_line_width": 0.2,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"other_line_width": 0.15,
"silk_line_width": 0.15,
"silk_text_size_h": 1.0,
"silk_text_size_v": 1.0,
"silk_text_thickness": 0.15
},
"diff_pair_dimensions": [],
"drc_exclusions": [],
"rules": {
"solder_mask_clearance": 0.0,
"solder_mask_min_width": 0.0
},
"track_widths": [],
"via_dimensions": []
},
"layer_presets": [],
"viewports": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"erc": {
"erc_exclusions": [],
"meta": {
"version": 0
},
"pin_map": [
[
0,
0,
0,
0,
0,
0,
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0,
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0,
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],
[
0,
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],
[
0,
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],
[
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],
[
0,
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],
[
0,
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],
[
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],
[
0,
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],
[
0,
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],
[
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],
[
0,
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],
[
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2
]
],
"rule_severities": {
"bus_definition_conflict": "error",
"bus_entry_needed": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"conflicting_netclasses": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"endpoint_off_grid": "warning",
"extra_units": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"missing_bidi_pin": "warning",
"missing_input_pin": "warning",
"missing_power_pin": "error",
"missing_unit": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "warning",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"simulation_model_issue": "error",
"unannotated": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
"wire_dangling": "error"
}
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "issue13162.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.25,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6
}
],
"meta": {
"version": 3
},
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": []
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "",
"specctra_dsn": "",
"step": "",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"annotate_start_num": 0,
"drawing": {
"dashed_lines_dash_length_ratio": 12.0,
"dashed_lines_gap_length_ratio": 3.0,
"default_bus_thickness": 12.0,
"default_junction_size": 40.0,
"default_line_thickness": 6.0,
"default_text_size": 50.0,
"default_wire_thickness": 6.0,
"field_names": [],
"intersheets_ref_own_page": false,
"intersheets_ref_prefix": "",
"intersheets_ref_short": false,
"intersheets_ref_show": false,
"intersheets_ref_suffix": "",
"junction_size_choice": 3,
"label_size_ratio": 0.3,
"pin_symbol_size": 25.0,
"text_offset_ratio": 0.3
},
"legacy_lib_dir": "",
"legacy_lib_list": [],
"meta": {
"version": 1
},
"net_format_name": "Spice",
"ngspice": {
"fix_include_paths": true,
"fix_passive_vals": false,
"meta": {
"version": 0
},
"model_mode": 4,
"workbook_filename": "Dual-NMOS-amp.wbk"
},
"page_layout_descr_file": "",
"plot_directory": "",
"spice_adjust_passive_values": false,
"spice_external_command": "C:\\Spice64\\bin\\ngspice \"%I\"",
"spice_save_all_currents": false,
"spice_save_all_voltages": false,
"subpart_first_id": 65,
"subpart_id_separator": 0
},
"sheets": [
[
"26ed1b96-1145-41e6-9da8-50c504d01964",
""
]
],
"text_variables": {}
}

2190
qa/data/eeschema/issue13162.kicad_sch Normal file
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File diff suppressed because it is too large Load Diff

54
qa/data/eeschema/issue13162.spice Normal file
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@ -0,0 +1,54 @@
KiCad schematic
.include "/Users/jeff/kicad_arm/kicad/qa/data/eeschema/TL072-dual.lib"
.include "/Users/jeff/kicad_arm/kicad/qa/data/eeschema/VDMOS_models.lib"
.save all
.probe alli
.ic v(Tj1)={envtemp} v(Tj2)={envtemp}
.temp {envtemp}
.param envtemp=25
.tran 200u 10
.option RELTOL=.01 ABSTOL=1N VNTOL=10u
.control
set controlswait
if $?sharedmode
rusage
else
run
rusage
settype temperature tj1 tj2 tcase1 tcase2
plot tj1 tj2 tcase1 tcase2
plot in out xlimit 5.2 5.3
end
.endc
Rload1 out GND 8
C7 Net-_C7-Pad1_ GND 300m
Vamb1 Net-_R11-Pad1_ GND {envtemp}
R14 Net-_R11-Pad1_ Net-_C7-Pad1_ 3
C6 Net-_C6-Pad1_ GND 300m
R13 Net-_C7-Pad1_ Tcase2 200m
R12 GND Tj2 1G
R9 GND Tj1 1G
R10 Net-_C6-Pad1_ Tcase1 200m
R11 Net-_R11-Pad1_ Net-_C6-Pad1_ 3
R4 Net-_U1A--_ GND 1k
C3 Net-_U1B-+_ GND 1u
R2 Net-_U1B-+_ GND 10k
XU1 Net-_R16-Pad2_ Net-_U1A--_ Net-_U1A-+_ GND Net-_U1B-+_ Net-_U1B--_ Net-_R17-Pad2_ VCC TL072c
R5 Net-_M2-D_ Net-_U1A--_ 19.5k
R17 Net-_M2-G_ Net-_R17-Pad2_ 100
R6 Net-_M2-S_ Net-_U1B--_ 100k
Vin1 in GND dc 0 ac 1 sin(0 0.5 100 20m)
C1 VCC GND 1u
R16 Net-_M1-G_ Net-_R16-Pad2_ 100
C2 Net-_U1A-+_ in 330n
R3 Net-_U1A-+_ Net-_U1B--_ 100k
R1 VCC Net-_U1B-+_ 390k
R7 Net-_M1-S_ Net-_M2-D_ 100m
C4 Net-_M2-D_ out 10m
R15 out GND 1k
C5 out Net-_M2-D_ 1u
M2 Net-_M2-D_ Net-_M2-G_ Net-_M2-S_ Tj2 Tcase2 IRFP240 thermal
M1 VCC Net-_M1-G_ Net-_M1-S_ Tj1 Tcase1 IRFP240 thermal
V1 VCC GND 36
R8 Net-_M2-S_ GND 800m
.end

10
qa/unittests/eeschema/sim/test_sim_regressions.cpp
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@ -116,4 +116,14 @@ BOOST_FIXTURE_TEST_CASE( LegacyFixups, TEST_SIM_REGRESSIONS_FIXTURE )
}
BOOST_FIXTURE_TEST_CASE( DualNMOSAmp, TEST_SIM_REGRESSIONS_FIXTURE )
{
LOCALE_IO dummy;
TestNetlist( "issue13162" );
TestTranPoint( 0.030, { { "V(out)", 0.535 } }, 0.001 );
TestTranPoint( 0.035, { { "V(out)", -1.437 } }, 0.001 );
}
#endif // KICAD_SPICE