Update Translations
This commit is contained in:
Seth Hillbrand
parent
15a44d75fb
commit
266ee381d5
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@ -2,7 +2,7 @@ msgid ""
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msgstr ""
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"Project-Id-Version: KiCad\n"
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"Report-Msgid-Bugs-To: \n"
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"POT-Creation-Date: 2022-02-14 09:20-0800\n"
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"POT-Creation-Date: 2022-02-16 17:22-0800\n"
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"PO-Revision-Date: 2011-11-29 21:48+0200\n"
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"Last-Translator: Evgeniy Ivanov <evgeniy_p_ivanov@yahoo.ca>\n"
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"Language-Team: KiCad Team <evgeniy_p_ivanov@yahoo.ca>\n"
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@ -4872,12 +4872,12 @@ msgstr "Псевдоним"
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#: common/filename_resolver.cpp:468
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#, fuzzy
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msgid "This path:wxT( "
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msgid "This path:"
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msgstr "Път към списък на връзките"
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#: common/filename_resolver.cpp:471
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#, fuzzy
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msgid "Existing path:wxT( "
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msgid "Existing path:"
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msgstr "Липсва:"
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#: common/filename_resolver.cpp:473
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@ -14069,9 +14069,9 @@ msgstr "(използвай клас на връзката)"
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msgid "Connection Name"
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msgstr "Тип на връзката:"
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#: eeschema/sch_connection.cpp:415
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#, fuzzy
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msgid "Net CodewxT( "
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#: eeschema/sch_connection.cpp:415 pcbnew/dialogs/dialog_net_inspector.cpp:76
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#: pcbnew/netinfo_item.cpp:76
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msgid "Net Code"
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msgstr "Код на верига"
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#: eeschema/sch_connection.cpp:420 eeschema/sch_connection.cpp:433
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@ -20043,8 +20043,8 @@ msgstr ""
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"Грешка: %s"
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#: kicad/tools/kicad_manager_control.cpp:670
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#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1558
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#: pcbnew/pcb_edit_frame.cpp:1588
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#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1551
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#: pcbnew/pcb_edit_frame.cpp:1581
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#, fuzzy
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msgid "KiCad Error"
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msgstr "Зареди грешката"
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@ -23228,7 +23228,7 @@ msgstr "Размер на перото"
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#: pcbnew/dialogs/dialog_board_setup.cpp:108
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#: pcbnew/dialogs/dialog_constraints_reporter.cpp:54
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#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1744
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#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1737
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#, fuzzy
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msgid "Custom Rules"
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msgstr "Особени ширини на пътечка:"
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@ -26562,10 +26562,6 @@ msgstr "Показване на полярни координати"
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msgid "Move Item"
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msgstr "Премести изображение"
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#: pcbnew/dialogs/dialog_net_inspector.cpp:76 pcbnew/netinfo_item.cpp:76
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msgid "Net Code"
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msgstr "Код на верига"
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#: pcbnew/dialogs/dialog_net_inspector.cpp:77 pcbnew/netinfo_item.cpp:74
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msgid "Net Name"
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msgstr "Име на верига"
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@ -30334,8 +30330,8 @@ msgid ""
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" A.inDiffPair('<net_name>')\n"
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"True if `A` has net that is part of the specified differential pair.\n"
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"`<net_name>` is the base name of the differential pair. For example, "
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"`inDiffPair('CLK')`\n"
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"matches items in the `CLK_P` and `CLK_N` nets.\n"
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"`inDiffPair('/CLK')`\n"
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"matches items in the `/CLK_P` and `/CLK_N` nets.\n"
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"<br><br>\n"
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"\n"
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" AB.isCoupledDiffPair()\n"
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@ -30375,20 +30371,20 @@ msgid ""
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" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n"
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"\n"
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"\n"
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" (rule \"Distance between Vias of Different Nets\" \n"
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" (rule \"Distance between Vias of Different Nets\"\n"
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" (constraint hole_to_hole (min 0.254mm))\n"
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" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n"
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"\n"
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" (rule \"Clearance between Pads of Different Nets\" \n"
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" (rule \"Clearance between Pads of Different Nets\"\n"
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" (constraint clearance (min 3.0mm))\n"
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" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n"
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"\n"
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"\n"
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" (rule \"Via Hole to Track Clearance\" \n"
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" (rule \"Via Hole to Track Clearance\"\n"
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" (constraint hole_clearance (min 0.254mm))\n"
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" (condition \"A.Type =='Via' && B.Type =='Track'\"))\n"
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" \n"
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" (rule \"Pad to Track Clearance\" \n"
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" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n"
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"\n"
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" (rule \"Pad to Track Clearance\"\n"
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" (constraint clearance (min 0.2mm))\n"
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" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n"
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"\n"
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@ -30398,11 +30394,11 @@ msgid ""
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" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n"
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"\n"
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"\n"
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" (rule \"Max Drill Hole Size Mechanical\" \n"
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" (rule \"Max Drill Hole Size Mechanical\"\n"
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" (constraint hole_size (max 6.3mm))\n"
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" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n"
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" \n"
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" (rule \"Max Drill Hole Size PTH\" \n"
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"\n"
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" (rule \"Max Drill Hole Size PTH\"\n"
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" (constraint hole_size (max 6.35mm))\n"
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" (condition \"A.Pad_Type == 'Through-hole'\"))\n"
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"\n"
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@ -30410,7 +30406,7 @@ msgid ""
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" # Specify an optimal gap for a particular diff-pair\n"
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" (rule \"dp clock gap\"\n"
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" (constraint diff_pair_gap (opt \"0.8mm\"))\n"
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" (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n"
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" (condition \"A.inDiffPair('/CLK')\"))\n"
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"\n"
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" # Specify a larger clearance around any diff-pair\n"
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" (rule \"dp clearance\"\n"
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@ -33082,59 +33078,59 @@ msgstr "Библиотека %s не е намерена"
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msgid "PCB file changes are unsaved"
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msgstr ""
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#: pcbnew/pcb_edit_frame.cpp:1473
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#: pcbnew/pcb_edit_frame.cpp:1466
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#, fuzzy
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msgid "The schematic for this board cannot be found."
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msgstr "Промяната на име на файл на лист неможе да бъде отменено."
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#: pcbnew/pcb_edit_frame.cpp:1497
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#: pcbnew/pcb_edit_frame.cpp:1490
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msgid ""
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"Cannot update the PCB because PCB editor is opened in stand-alone mode. In "
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"order to create or update PCBs from schematics, you must launch the KiCad "
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"project manager and create a project."
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msgstr ""
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#: pcbnew/pcb_edit_frame.cpp:1519
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#: pcbnew/pcb_edit_frame.cpp:1512
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#, fuzzy
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msgid "Eeschema netlist"
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msgstr "Прочети листа с веригите"
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#: pcbnew/pcb_edit_frame.cpp:1530
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#: pcbnew/pcb_edit_frame.cpp:1523
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msgid ""
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"Received an error while reading netlist. Please report this issue to the "
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"KiCad team using the menu Help->Report Bug."
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msgstr ""
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#: pcbnew/pcb_edit_frame.cpp:1557
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#: pcbnew/pcb_edit_frame.cpp:1550
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#, fuzzy, c-format
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msgid "Schematic file '%s' not found."
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msgstr "Помощен файл %s не е намерен."
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#: pcbnew/pcb_edit_frame.cpp:1587
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#: pcbnew/pcb_edit_frame.cpp:1580
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#, fuzzy
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msgid "Eeschema failed to load."
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msgstr ""
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"Неуспешно зареждане на компонентна библиотека <%s> .\n"
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"Грешка: %s"
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#: pcbnew/pcb_edit_frame.cpp:1738
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#: pcbnew/pcb_edit_frame.cpp:1731
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#, fuzzy
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msgid "Edit design rules"
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msgstr "Правила на проектиране"
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#: pcbnew/pcb_edit_frame.cpp:1750
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#: pcbnew/pcb_edit_frame.cpp:1743
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#, fuzzy
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msgid "Could not compile custom design rules."
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msgstr "Зареди съществуващ файл с конфиг. горещи клавиши"
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#: pcbnew/pcb_edit_frame.cpp:1785
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#: pcbnew/pcb_edit_frame.cpp:1778
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msgid "Export Hyperlynx Layout"
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msgstr ""
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#: pcbnew/pcb_expr_evaluator.cpp:95 pcbnew/pcb_expr_evaluator.cpp:264
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#: pcbnew/pcb_expr_evaluator.cpp:330 pcbnew/pcb_expr_evaluator.cpp:396
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#: pcbnew/pcb_expr_evaluator.cpp:614 pcbnew/pcb_expr_evaluator.cpp:716
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#: pcbnew/pcb_expr_evaluator.cpp:829
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#: pcbnew/pcb_expr_evaluator.cpp:824
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#, c-format
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msgid "Missing argument to '%s'"
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msgstr ""
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@ -33159,7 +33155,7 @@ msgstr "Филтър комп.отп. <%s> е вече определен."
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msgid "Footprint has no back courtyard."
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msgstr "Филтър комп.отп. <%s> е вече определен."
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#: pcbnew/pcb_expr_evaluator.cpp:1152
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#: pcbnew/pcb_expr_evaluator.cpp:1153
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msgid "must be mm, in, or mil"
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msgstr ""
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@ -38698,6 +38694,10 @@ msgstr "Печат на схемата"
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msgid "KiCad Printed Circuit Board"
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msgstr "Създаване на печатна платка"
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#, fuzzy
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#~ msgid "Net CodewxT( "
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#~ msgstr "Код на верига"
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#, fuzzy
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#~ msgid "Save changes to schematic before closing?"
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#~ msgstr "Съхрани файлове списък на вериги и комп.отп."
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@ -3,7 +3,7 @@ msgid ""
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msgstr ""
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"Project-Id-Version: kicad\n"
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"Report-Msgid-Bugs-To: \n"
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"POT-Creation-Date: 2022-02-14 09:20-0800\n"
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"POT-Creation-Date: 2022-02-16 17:22-0800\n"
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"PO-Revision-Date: 2022-02-16 13:03+0000\n"
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"Last-Translator: Arnau Llovet Vidal <arnaullv@gmail.com>\n"
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"Language-Team: Catalan <https://hosted.weblate.org/projects/kicad/v6/ca/>\n"
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@ -4606,12 +4606,12 @@ msgstr "Àlies: "
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#: common/filename_resolver.cpp:468
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#, fuzzy
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msgid "This path:wxT( "
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msgid "This path:"
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msgstr "Aquest camí:"
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#: common/filename_resolver.cpp:471
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#, fuzzy
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msgid "Existing path:wxT( "
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msgid "Existing path:"
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msgstr "Camí existent:"
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#: common/filename_resolver.cpp:473
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@ -13425,9 +13425,9 @@ msgstr "Classe de xarxa assignada"
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msgid "Connection Name"
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msgstr "Nom de connexió"
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#: eeschema/sch_connection.cpp:415
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#, fuzzy
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msgid "Net CodewxT( "
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#: eeschema/sch_connection.cpp:415 pcbnew/dialogs/dialog_net_inspector.cpp:76
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#: pcbnew/netinfo_item.cpp:76
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msgid "Net Code"
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msgstr "Codi de la xarxa"
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#: eeschema/sch_connection.cpp:420 eeschema/sch_connection.cpp:433
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@ -19274,8 +19274,8 @@ msgid "Application failed to load:\n"
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msgstr "Pcbnew no ha pogut carregar:\n"
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#: kicad/tools/kicad_manager_control.cpp:670
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#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1558
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#: pcbnew/pcb_edit_frame.cpp:1588
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#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1551
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#: pcbnew/pcb_edit_frame.cpp:1581
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msgid "KiCad Error"
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msgstr "Error de KiCad"
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@ -22344,7 +22344,7 @@ msgstr "Mida del traç"
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#: pcbnew/dialogs/dialog_board_setup.cpp:108
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#: pcbnew/dialogs/dialog_constraints_reporter.cpp:54
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#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1744
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#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1737
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msgid "Custom Rules"
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msgstr "Normes personalitzades"
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@ -25484,10 +25484,6 @@ msgstr "Utilitza coordenades polars"
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msgid "Move Item"
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msgstr "Mou l'element"
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#: pcbnew/dialogs/dialog_net_inspector.cpp:76 pcbnew/netinfo_item.cpp:76
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msgid "Net Code"
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msgstr "Codi de la xarxa"
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#: pcbnew/dialogs/dialog_net_inspector.cpp:77 pcbnew/netinfo_item.cpp:74
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msgid "Net Name"
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msgstr "Nom de la xarxa"
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@ -29063,8 +29059,8 @@ msgid ""
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" A.inDiffPair('<net_name>')\n"
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"True if `A` has net that is part of the specified differential pair.\n"
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"`<net_name>` is the base name of the differential pair. For example, "
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"`inDiffPair('CLK')`\n"
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"matches items in the `CLK_P` and `CLK_N` nets.\n"
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"`inDiffPair('/CLK')`\n"
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"matches items in the `/CLK_P` and `/CLK_N` nets.\n"
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"<br><br>\n"
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"\n"
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" AB.isCoupledDiffPair()\n"
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@ -29104,20 +29100,20 @@ msgid ""
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" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n"
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"\n"
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"\n"
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" (rule \"Distance between Vias of Different Nets\" \n"
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" (rule \"Distance between Vias of Different Nets\"\n"
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" (constraint hole_to_hole (min 0.254mm))\n"
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" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n"
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"\n"
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" (rule \"Clearance between Pads of Different Nets\" \n"
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" (rule \"Clearance between Pads of Different Nets\"\n"
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" (constraint clearance (min 3.0mm))\n"
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" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n"
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"\n"
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"\n"
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" (rule \"Via Hole to Track Clearance\" \n"
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" (rule \"Via Hole to Track Clearance\"\n"
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" (constraint hole_clearance (min 0.254mm))\n"
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" (condition \"A.Type =='Via' && B.Type =='Track'\"))\n"
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" \n"
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" (rule \"Pad to Track Clearance\" \n"
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" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n"
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"\n"
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" (rule \"Pad to Track Clearance\"\n"
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" (constraint clearance (min 0.2mm))\n"
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" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n"
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"\n"
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@ -29127,11 +29123,11 @@ msgid ""
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" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n"
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"\n"
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"\n"
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" (rule \"Max Drill Hole Size Mechanical\" \n"
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" (rule \"Max Drill Hole Size Mechanical\"\n"
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" (constraint hole_size (max 6.3mm))\n"
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" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n"
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" \n"
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" (rule \"Max Drill Hole Size PTH\" \n"
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"\n"
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" (rule \"Max Drill Hole Size PTH\"\n"
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" (constraint hole_size (max 6.35mm))\n"
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" (condition \"A.Pad_Type == 'Through-hole'\"))\n"
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"\n"
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@ -29139,7 +29135,7 @@ msgid ""
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" # Specify an optimal gap for a particular diff-pair\n"
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" (rule \"dp clock gap\"\n"
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" (constraint diff_pair_gap (opt \"0.8mm\"))\n"
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" (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n"
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" (condition \"A.inDiffPair('/CLK')\"))\n"
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"\n"
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" # Specify a larger clearance around any diff-pair\n"
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" (rule \"dp clearance\"\n"
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@ -31770,55 +31766,55 @@ msgstr "Únicament l'àrea de la placa"
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msgid "PCB file changes are unsaved"
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msgstr ""
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#: pcbnew/pcb_edit_frame.cpp:1473
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#: pcbnew/pcb_edit_frame.cpp:1466
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#, fuzzy
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msgid "The schematic for this board cannot be found."
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msgstr "El camp %s no pot estar buit."
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#: pcbnew/pcb_edit_frame.cpp:1497
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#: pcbnew/pcb_edit_frame.cpp:1490
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msgid ""
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"Cannot update the PCB because PCB editor is opened in stand-alone mode. In "
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"order to create or update PCBs from schematics, you must launch the KiCad "
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"project manager and create a project."
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msgstr ""
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#: pcbnew/pcb_edit_frame.cpp:1519
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#: pcbnew/pcb_edit_frame.cpp:1512
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#, fuzzy
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msgid "Eeschema netlist"
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msgstr "Netlist d'EEschema"
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|
||||
#: pcbnew/pcb_edit_frame.cpp:1530
|
||||
#: pcbnew/pcb_edit_frame.cpp:1523
|
||||
msgid ""
|
||||
"Received an error while reading netlist. Please report this issue to the "
|
||||
"KiCad team using the menu Help->Report Bug."
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1557
|
||||
#: pcbnew/pcb_edit_frame.cpp:1550
|
||||
#, fuzzy, c-format
|
||||
msgid "Schematic file '%s' not found."
|
||||
msgstr "No s'ha trobat el fitxer de recuperació «%s»."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1587
|
||||
#: pcbnew/pcb_edit_frame.cpp:1580
|
||||
msgid "Eeschema failed to load."
|
||||
msgstr "No s'ha pogut carregar l'Eeschema."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1738
|
||||
#: pcbnew/pcb_edit_frame.cpp:1731
|
||||
msgid "Edit design rules"
|
||||
msgstr "Edita normes de disseny"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1750
|
||||
#: pcbnew/pcb_edit_frame.cpp:1743
|
||||
#, fuzzy
|
||||
msgid "Could not compile custom design rules."
|
||||
msgstr "No s'ha pogut obrir el fitxer de configuració"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1785
|
||||
#: pcbnew/pcb_edit_frame.cpp:1778
|
||||
msgid "Export Hyperlynx Layout"
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:95 pcbnew/pcb_expr_evaluator.cpp:264
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:330 pcbnew/pcb_expr_evaluator.cpp:396
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:614 pcbnew/pcb_expr_evaluator.cpp:716
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:829
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:824
|
||||
#, c-format
|
||||
msgid "Missing argument to '%s'"
|
||||
msgstr ""
|
||||
|
|
@ -31843,7 +31839,7 @@ msgstr "No s'ha trobat l'empremta «%s»"
|
|||
msgid "Footprint has no back courtyard."
|
||||
msgstr "No s'ha trobat l'empremta «%s»"
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1152
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1153
|
||||
msgid "must be mm, in, or mil"
|
||||
msgstr ""
|
||||
|
||||
|
|
@ -37244,6 +37240,10 @@ msgstr "Edita l'esquemàtic"
|
|||
msgid "KiCad Printed Circuit Board"
|
||||
msgstr "Fitxers de plaques de circuits impresos de KiCad (*.brd)|*.brd"
|
||||
|
||||
#, fuzzy
|
||||
#~ msgid "Net CodewxT( "
|
||||
#~ msgstr "Codi de la xarxa"
|
||||
|
||||
#~ msgid "Save changes to schematic before closing?"
|
||||
#~ msgstr "Vols desar els canvis de l'esquemàtic abans de tancar?"
|
||||
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@ msgid ""
|
|||
msgstr ""
|
||||
"Project-Id-Version: kicad\n"
|
||||
"Report-Msgid-Bugs-To: \n"
|
||||
"POT-Creation-Date: 2022-02-14 09:20-0800\n"
|
||||
"POT-Creation-Date: 2022-02-16 17:22-0800\n"
|
||||
"PO-Revision-Date: 2022-02-16 13:03+0000\n"
|
||||
"Last-Translator: Jan Straka <bach@email.cz>\n"
|
||||
"Language-Team: Czech <https://hosted.weblate.org/projects/kicad/v6/cs/>\n"
|
||||
|
|
@ -4569,11 +4569,13 @@ msgid "Alias: "
|
|||
msgstr "Alias: "
|
||||
|
||||
#: common/filename_resolver.cpp:468
|
||||
msgid "This path:wxT( "
|
||||
#, fuzzy
|
||||
msgid "This path:"
|
||||
msgstr "Tato cesta:wxT( "
|
||||
|
||||
#: common/filename_resolver.cpp:471
|
||||
msgid "Existing path:wxT( "
|
||||
#, fuzzy
|
||||
msgid "Existing path:"
|
||||
msgstr "Existující cesta:wxT( "
|
||||
|
||||
#: common/filename_resolver.cpp:473
|
||||
|
|
@ -13291,9 +13293,10 @@ msgstr "Přiřazená třída spojů"
|
|||
msgid "Connection Name"
|
||||
msgstr "Název připojení"
|
||||
|
||||
#: eeschema/sch_connection.cpp:415
|
||||
msgid "Net CodewxT( "
|
||||
msgstr "Kód sítěwxT( "
|
||||
#: eeschema/sch_connection.cpp:415 pcbnew/dialogs/dialog_net_inspector.cpp:76
|
||||
#: pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr "Kód sítě"
|
||||
|
||||
#: eeschema/sch_connection.cpp:420 eeschema/sch_connection.cpp:433
|
||||
#, c-format
|
||||
|
|
@ -18990,8 +18993,8 @@ msgid "Application failed to load:\n"
|
|||
msgstr "Načtení aplikace se nezdařilo:\n"
|
||||
|
||||
#: kicad/tools/kicad_manager_control.cpp:670
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1558
|
||||
#: pcbnew/pcb_edit_frame.cpp:1588
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1551
|
||||
#: pcbnew/pcb_edit_frame.cpp:1581
|
||||
msgid "KiCad Error"
|
||||
msgstr "KiCad chyba"
|
||||
|
||||
|
|
@ -21968,7 +21971,7 @@ msgstr "Předdefinované velikosti"
|
|||
|
||||
#: pcbnew/dialogs/dialog_board_setup.cpp:108
|
||||
#: pcbnew/dialogs/dialog_constraints_reporter.cpp:54
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1744
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1737
|
||||
msgid "Custom Rules"
|
||||
msgstr "Vlastní pravidla"
|
||||
|
||||
|
|
@ -25019,10 +25022,6 @@ msgstr "Použít polární souřadnice"
|
|||
msgid "Move Item"
|
||||
msgstr "Přesunout položku"
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:76 pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr "Kód sítě"
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:77 pcbnew/netinfo_item.cpp:74
|
||||
msgid "Net Name"
|
||||
msgstr "Název sítě"
|
||||
|
|
@ -28555,8 +28554,8 @@ msgid ""
|
|||
" A.inDiffPair('<net_name>')\n"
|
||||
"True if `A` has net that is part of the specified differential pair.\n"
|
||||
"`<net_name>` is the base name of the differential pair. For example, "
|
||||
"`inDiffPair('CLK')`\n"
|
||||
"matches items in the `CLK_P` and `CLK_N` nets.\n"
|
||||
"`inDiffPair('/CLK')`\n"
|
||||
"matches items in the `/CLK_P` and `/CLK_N` nets.\n"
|
||||
"<br><br>\n"
|
||||
"\n"
|
||||
" AB.isCoupledDiffPair()\n"
|
||||
|
|
@ -28596,20 +28595,20 @@ msgid ""
|
|||
" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Distance between Vias of Different Nets\" \n"
|
||||
" (rule \"Distance between Vias of Different Nets\"\n"
|
||||
" (constraint hole_to_hole (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
" (rule \"Clearance between Pads of Different Nets\" \n"
|
||||
" (rule \"Clearance between Pads of Different Nets\"\n"
|
||||
" (constraint clearance (min 3.0mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Via Hole to Track Clearance\" \n"
|
||||
" (rule \"Via Hole to Track Clearance\"\n"
|
||||
" (constraint hole_clearance (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Track'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Pad to Track Clearance\" \n"
|
||||
" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n"
|
||||
"\n"
|
||||
" (rule \"Pad to Track Clearance\"\n"
|
||||
" (constraint clearance (min 0.2mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -28619,11 +28618,11 @@ msgid ""
|
|||
" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\" \n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\"\n"
|
||||
" (constraint hole_size (max 6.3mm))\n"
|
||||
" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Max Drill Hole Size PTH\" \n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size PTH\"\n"
|
||||
" (constraint hole_size (max 6.35mm))\n"
|
||||
" (condition \"A.Pad_Type == 'Through-hole'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -28631,7 +28630,7 @@ msgid ""
|
|||
" # Specify an optimal gap for a particular diff-pair\n"
|
||||
" (rule \"dp clock gap\"\n"
|
||||
" (constraint diff_pair_gap (opt \"0.8mm\"))\n"
|
||||
" (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n"
|
||||
" (condition \"A.inDiffPair('/CLK')\"))\n"
|
||||
"\n"
|
||||
" # Specify a larger clearance around any diff-pair\n"
|
||||
" (rule \"dp clearance\"\n"
|
||||
|
|
@ -31155,11 +31154,11 @@ msgstr "Soubor desky je pouze pro čtení."
|
|||
msgid "PCB file changes are unsaved"
|
||||
msgstr "Změny souboru DPS neuloženy"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1473
|
||||
#: pcbnew/pcb_edit_frame.cpp:1466
|
||||
msgid "The schematic for this board cannot be found."
|
||||
msgstr "Schéma této desky nelze nalézt."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1497
|
||||
#: pcbnew/pcb_edit_frame.cpp:1490
|
||||
#, fuzzy
|
||||
msgid ""
|
||||
"Cannot update the PCB because PCB editor is opened in stand-alone mode. In "
|
||||
|
|
@ -31170,41 +31169,41 @@ msgstr ""
|
|||
"bylo možno vytvořit/aktualizovat DPS ze schématu, musíte spustit základní "
|
||||
"program Kicad a vytvořit DPS."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1519
|
||||
#: pcbnew/pcb_edit_frame.cpp:1512
|
||||
msgid "Eeschema netlist"
|
||||
msgstr "Eeschema netlist"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1530
|
||||
#: pcbnew/pcb_edit_frame.cpp:1523
|
||||
msgid ""
|
||||
"Received an error while reading netlist. Please report this issue to the "
|
||||
"KiCad team using the menu Help->Report Bug."
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1557
|
||||
#: pcbnew/pcb_edit_frame.cpp:1550
|
||||
#, c-format
|
||||
msgid "Schematic file '%s' not found."
|
||||
msgstr "Soubor schématu '%s' nenalezen."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1587
|
||||
#: pcbnew/pcb_edit_frame.cpp:1580
|
||||
msgid "Eeschema failed to load."
|
||||
msgstr "Eeschema se nepodařilo načíst."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1738
|
||||
#: pcbnew/pcb_edit_frame.cpp:1731
|
||||
msgid "Edit design rules"
|
||||
msgstr "Upravit pravidla návrhu"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1750
|
||||
#: pcbnew/pcb_edit_frame.cpp:1743
|
||||
msgid "Could not compile custom design rules."
|
||||
msgstr "Nelze sestavit vlastní pravidla návrhu."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1785
|
||||
#: pcbnew/pcb_edit_frame.cpp:1778
|
||||
msgid "Export Hyperlynx Layout"
|
||||
msgstr "Export do formátu hyperlynxu"
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:95 pcbnew/pcb_expr_evaluator.cpp:264
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:330 pcbnew/pcb_expr_evaluator.cpp:396
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:614 pcbnew/pcb_expr_evaluator.cpp:716
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:829
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:824
|
||||
#, c-format
|
||||
msgid "Missing argument to '%s'"
|
||||
msgstr "Chybí argument pro '%s'"
|
||||
|
|
@ -31226,7 +31225,7 @@ msgstr "Pouzdro nemá nahoře žádnou zónu obsazení."
|
|||
msgid "Footprint has no back courtyard."
|
||||
msgstr "Pouzdro nemá dole žádnou zónu obsazení."
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1152
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1153
|
||||
msgid "must be mm, in, or mil"
|
||||
msgstr "musí být mm, in nebo mily"
|
||||
|
||||
|
|
@ -36451,6 +36450,9 @@ msgstr "KiCad schéma"
|
|||
msgid "KiCad Printed Circuit Board"
|
||||
msgstr "KiCad deska plošných spojů"
|
||||
|
||||
#~ msgid "Net CodewxT( "
|
||||
#~ msgstr "Kód sítěwxT( "
|
||||
|
||||
#~ msgid "Save changes to schematic before closing?"
|
||||
#~ msgstr "Uložit změny do schématu před zavřením?"
|
||||
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@ msgid ""
|
|||
msgstr ""
|
||||
"Project-Id-Version: KiCad\n"
|
||||
"Report-Msgid-Bugs-To: \n"
|
||||
"POT-Creation-Date: 2022-02-14 09:20-0800\n"
|
||||
"POT-Creation-Date: 2022-02-16 17:22-0800\n"
|
||||
"PO-Revision-Date: 2021-08-20 19:52+0000\n"
|
||||
"Last-Translator: Seth Hillbrand <seth@kipro-pcb.com>\n"
|
||||
"Language-Team: Danish <https://hosted.weblate.org/projects/kicad/master-"
|
||||
|
|
@ -4692,12 +4692,12 @@ msgstr "Alias: "
|
|||
|
||||
#: common/filename_resolver.cpp:468
|
||||
#, fuzzy
|
||||
msgid "This path:wxT( "
|
||||
msgid "This path:"
|
||||
msgstr "Denne vej:"
|
||||
|
||||
#: common/filename_resolver.cpp:471
|
||||
#, fuzzy
|
||||
msgid "Existing path:wxT( "
|
||||
msgid "Existing path:"
|
||||
msgstr "Eksisterende sti:"
|
||||
|
||||
#: common/filename_resolver.cpp:473
|
||||
|
|
@ -13548,9 +13548,9 @@ msgstr "Tildelt netklasse"
|
|||
msgid "Connection Name"
|
||||
msgstr "Forbindelsesnavn"
|
||||
|
||||
#: eeschema/sch_connection.cpp:415
|
||||
#, fuzzy
|
||||
msgid "Net CodewxT( "
|
||||
#: eeschema/sch_connection.cpp:415 pcbnew/dialogs/dialog_net_inspector.cpp:76
|
||||
#: pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr "Net kode"
|
||||
|
||||
#: eeschema/sch_connection.cpp:420 eeschema/sch_connection.cpp:433
|
||||
|
|
@ -19445,8 +19445,8 @@ msgid "Application failed to load:\n"
|
|||
msgstr "Programmet kunne ikke indlæses:\n"
|
||||
|
||||
#: kicad/tools/kicad_manager_control.cpp:670
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1558
|
||||
#: pcbnew/pcb_edit_frame.cpp:1588
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1551
|
||||
#: pcbnew/pcb_edit_frame.cpp:1581
|
||||
msgid "KiCad Error"
|
||||
msgstr "KiCad-fejl"
|
||||
|
||||
|
|
@ -22604,7 +22604,7 @@ msgstr "Foruddefinerede størrelser:"
|
|||
|
||||
#: pcbnew/dialogs/dialog_board_setup.cpp:108
|
||||
#: pcbnew/dialogs/dialog_constraints_reporter.cpp:54
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1744
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1737
|
||||
#, fuzzy
|
||||
msgid "Custom Rules"
|
||||
msgstr "Brugerdefineret lag sæt"
|
||||
|
|
@ -25691,10 +25691,6 @@ msgstr "Brug polære koordinater"
|
|||
msgid "Move Item"
|
||||
msgstr "Flyt element"
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:76 pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr "Net kode"
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:77 pcbnew/netinfo_item.cpp:74
|
||||
msgid "Net Name"
|
||||
msgstr "Netnavn"
|
||||
|
|
@ -29287,8 +29283,8 @@ msgid ""
|
|||
" A.inDiffPair('<net_name>')\n"
|
||||
"True if `A` has net that is part of the specified differential pair.\n"
|
||||
"`<net_name>` is the base name of the differential pair. For example, "
|
||||
"`inDiffPair('CLK')`\n"
|
||||
"matches items in the `CLK_P` and `CLK_N` nets.\n"
|
||||
"`inDiffPair('/CLK')`\n"
|
||||
"matches items in the `/CLK_P` and `/CLK_N` nets.\n"
|
||||
"<br><br>\n"
|
||||
"\n"
|
||||
" AB.isCoupledDiffPair()\n"
|
||||
|
|
@ -29328,20 +29324,20 @@ msgid ""
|
|||
" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Distance between Vias of Different Nets\" \n"
|
||||
" (rule \"Distance between Vias of Different Nets\"\n"
|
||||
" (constraint hole_to_hole (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
" (rule \"Clearance between Pads of Different Nets\" \n"
|
||||
" (rule \"Clearance between Pads of Different Nets\"\n"
|
||||
" (constraint clearance (min 3.0mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Via Hole to Track Clearance\" \n"
|
||||
" (rule \"Via Hole to Track Clearance\"\n"
|
||||
" (constraint hole_clearance (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Track'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Pad to Track Clearance\" \n"
|
||||
" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n"
|
||||
"\n"
|
||||
" (rule \"Pad to Track Clearance\"\n"
|
||||
" (constraint clearance (min 0.2mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -29351,11 +29347,11 @@ msgid ""
|
|||
" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\" \n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\"\n"
|
||||
" (constraint hole_size (max 6.3mm))\n"
|
||||
" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Max Drill Hole Size PTH\" \n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size PTH\"\n"
|
||||
" (constraint hole_size (max 6.35mm))\n"
|
||||
" (condition \"A.Pad_Type == 'Through-hole'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -29363,7 +29359,7 @@ msgid ""
|
|||
" # Specify an optimal gap for a particular diff-pair\n"
|
||||
" (rule \"dp clock gap\"\n"
|
||||
" (constraint diff_pair_gap (opt \"0.8mm\"))\n"
|
||||
" (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n"
|
||||
" (condition \"A.inDiffPair('/CLK')\"))\n"
|
||||
"\n"
|
||||
" # Specify a larger clearance around any diff-pair\n"
|
||||
" (rule \"dp clearance\"\n"
|
||||
|
|
@ -31939,11 +31935,11 @@ msgstr "Kun bestyrelsesområde"
|
|||
msgid "PCB file changes are unsaved"
|
||||
msgstr "PCB-filændringer er ikke gemt"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1473
|
||||
#: pcbnew/pcb_edit_frame.cpp:1466
|
||||
msgid "The schematic for this board cannot be found."
|
||||
msgstr "Skemaet for dette tavle kan ikke findes."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1497
|
||||
#: pcbnew/pcb_edit_frame.cpp:1490
|
||||
#, fuzzy
|
||||
msgid ""
|
||||
"Cannot update the PCB because PCB editor is opened in stand-alone mode. In "
|
||||
|
|
@ -31954,44 +31950,44 @@ msgstr ""
|
|||
"For at oprette eller opdatere PCB'er fra skemaer skal du starte KiCad-"
|
||||
"projektlederen og oprette et projekt."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1519
|
||||
#: pcbnew/pcb_edit_frame.cpp:1512
|
||||
msgid "Eeschema netlist"
|
||||
msgstr "Eeschema netliste"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1530
|
||||
#: pcbnew/pcb_edit_frame.cpp:1523
|
||||
msgid ""
|
||||
"Received an error while reading netlist. Please report this issue to the "
|
||||
"KiCad team using the menu Help->Report Bug."
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1557
|
||||
#: pcbnew/pcb_edit_frame.cpp:1550
|
||||
#, fuzzy, c-format
|
||||
msgid "Schematic file '%s' not found."
|
||||
msgstr "Skematisk fil \"%s\" blev ikke fundet."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1587
|
||||
#: pcbnew/pcb_edit_frame.cpp:1580
|
||||
#, fuzzy
|
||||
msgid "Eeschema failed to load."
|
||||
msgstr "Eeschema kunne ikke indlæse:\n"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1738
|
||||
#: pcbnew/pcb_edit_frame.cpp:1731
|
||||
#, fuzzy
|
||||
msgid "Edit design rules"
|
||||
msgstr "Designregler"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1750
|
||||
#: pcbnew/pcb_edit_frame.cpp:1743
|
||||
#, fuzzy
|
||||
msgid "Could not compile custom design rules."
|
||||
msgstr "DRC ufuldstændig: kunne ikke kompilere designregler. "
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1785
|
||||
#: pcbnew/pcb_edit_frame.cpp:1778
|
||||
msgid "Export Hyperlynx Layout"
|
||||
msgstr "Eksportér Hyperlynx Layout"
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:95 pcbnew/pcb_expr_evaluator.cpp:264
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:330 pcbnew/pcb_expr_evaluator.cpp:396
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:614 pcbnew/pcb_expr_evaluator.cpp:716
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:829
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:824
|
||||
#, c-format
|
||||
msgid "Missing argument to '%s'"
|
||||
msgstr "Manglende argument til '%s'"
|
||||
|
|
@ -32013,7 +32009,7 @@ msgstr "Footprint har ingen gårdhave."
|
|||
msgid "Footprint has no back courtyard."
|
||||
msgstr "Footprint har ingen baggård."
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1152
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1153
|
||||
msgid "must be mm, in, or mil"
|
||||
msgstr "skal være mm, in eller mil"
|
||||
|
||||
|
|
@ -37346,6 +37342,10 @@ msgstr "Rediger skematisk"
|
|||
msgid "KiCad Printed Circuit Board"
|
||||
msgstr "KiCad-printkortfiler"
|
||||
|
||||
#, fuzzy
|
||||
#~ msgid "Net CodewxT( "
|
||||
#~ msgstr "Net kode"
|
||||
|
||||
#~ msgid "Save changes to schematic before closing?"
|
||||
#~ msgstr "Gem ændringer i skemaet inden lukning?"
|
||||
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@ msgid ""
|
|||
msgstr ""
|
||||
"Project-Id-Version: KiCad i18n Deutsch\n"
|
||||
"Report-Msgid-Bugs-To: \n"
|
||||
"POT-Creation-Date: 2022-02-14 09:20-0800\n"
|
||||
"POT-Creation-Date: 2022-02-16 17:22-0800\n"
|
||||
"PO-Revision-Date: 2022-02-16 22:56+0000\n"
|
||||
"Last-Translator: Mark Hämmerling <dev@markh.de>\n"
|
||||
"Language-Team: German <https://hosted.weblate.org/projects/kicad/v6/de/>\n"
|
||||
|
|
@ -4640,12 +4640,12 @@ msgstr "Alias: "
|
|||
|
||||
#: common/filename_resolver.cpp:468
|
||||
#, fuzzy
|
||||
msgid "This path:wxT( "
|
||||
msgid "This path:"
|
||||
msgstr "Dieser Pfad:"
|
||||
|
||||
#: common/filename_resolver.cpp:471
|
||||
#, fuzzy
|
||||
msgid "Existing path:wxT( "
|
||||
msgid "Existing path:"
|
||||
msgstr "Existierender Pfad:"
|
||||
|
||||
#: common/filename_resolver.cpp:473
|
||||
|
|
@ -13490,9 +13490,9 @@ msgstr "Zugewiesene Netzklasse"
|
|||
msgid "Connection Name"
|
||||
msgstr "Verbindungsname"
|
||||
|
||||
#: eeschema/sch_connection.cpp:415
|
||||
#, fuzzy
|
||||
msgid "Net CodewxT( "
|
||||
#: eeschema/sch_connection.cpp:415 pcbnew/dialogs/dialog_net_inspector.cpp:76
|
||||
#: pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr "Netz-Code"
|
||||
|
||||
#: eeschema/sch_connection.cpp:420 eeschema/sch_connection.cpp:433
|
||||
|
|
@ -19300,8 +19300,8 @@ msgid "Application failed to load:\n"
|
|||
msgstr "Anwendung konnte nicht geladen werden:\n"
|
||||
|
||||
#: kicad/tools/kicad_manager_control.cpp:670
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1558
|
||||
#: pcbnew/pcb_edit_frame.cpp:1588
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1551
|
||||
#: pcbnew/pcb_edit_frame.cpp:1581
|
||||
msgid "KiCad Error"
|
||||
msgstr "KiCad-Fehler"
|
||||
|
||||
|
|
@ -20889,16 +20889,17 @@ msgstr ""
|
|||
"\n"
|
||||
"Der bestimmende Wert ist fett dargestellt.\n"
|
||||
"\n"
|
||||
"Die Berechnungen gelten für Ströme bis zu 35 A (extern) bzw. 17,5 A (intern)"
|
||||
", Temperaturanstiege bis zu 100 °C und Breiten von bis zu 400 mil (10 mm).\n"
|
||||
"Die Berechnungen gelten für Ströme bis zu 35 A (extern) bzw. 17,5 A "
|
||||
"(intern), Temperaturanstiege bis zu 100 °C und Breiten von bis zu 400 mil "
|
||||
"(10 mm).\n"
|
||||
"\n"
|
||||
"Die zugehörige Formel aus IPC 2221 lautet\n"
|
||||
"<center>___I = K · ΔT<sup>0,44</sup> · (W · "
|
||||
"H)<sup>0,725</sup>___</center>\n"
|
||||
"wobei:<br>\n"
|
||||
"___I___ = Maximaler Strom in A<br>\n"
|
||||
"___ΔT___ = Temperaturanstieg über die Umgebungstemperatur in °C<br>"
|
||||
"\n"
|
||||
"___ΔT___ = Temperaturanstieg über die Umgebungstemperatur in °"
|
||||
"C<br>\n"
|
||||
"___W___ = Breite in mil<br>\n"
|
||||
"___H___ = Dicke (Höhe) in mil<br>\n"
|
||||
"___K___ = 0,024 für interne Leiterbahnen oder 0,048 für externe "
|
||||
|
|
@ -22361,7 +22362,7 @@ msgstr "Vordefinierte Größen"
|
|||
|
||||
#: pcbnew/dialogs/dialog_board_setup.cpp:108
|
||||
#: pcbnew/dialogs/dialog_constraints_reporter.cpp:54
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1744
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1737
|
||||
msgid "Custom Rules"
|
||||
msgstr "Benutzerdefinierte Regeln"
|
||||
|
||||
|
|
@ -25444,10 +25445,6 @@ msgstr "Polarkoordinaten benutzen"
|
|||
msgid "Move Item"
|
||||
msgstr "Element verschieben"
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:76 pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr "Netz-Code"
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:77 pcbnew/netinfo_item.cpp:74
|
||||
msgid "Net Name"
|
||||
msgstr "Netzname"
|
||||
|
|
@ -28948,6 +28945,7 @@ msgid "Check rule syntax"
|
|||
msgstr "Überprüfen Sie die Regelsyntax"
|
||||
|
||||
#: pcbnew/dialogs/panel_setup_rules_help_md.h:2
|
||||
#, fuzzy
|
||||
msgid ""
|
||||
"### Top-level Clauses\n"
|
||||
"\n"
|
||||
|
|
@ -29073,8 +29071,8 @@ msgid ""
|
|||
" A.inDiffPair('<net_name>')\n"
|
||||
"True if `A` has net that is part of the specified differential pair.\n"
|
||||
"`<net_name>` is the base name of the differential pair. For example, "
|
||||
"`inDiffPair('CLK')`\n"
|
||||
"matches items in the `CLK_P` and `CLK_N` nets.\n"
|
||||
"`inDiffPair('/CLK')`\n"
|
||||
"matches items in the `/CLK_P` and `/CLK_N` nets.\n"
|
||||
"<br><br>\n"
|
||||
"\n"
|
||||
" AB.isCoupledDiffPair()\n"
|
||||
|
|
@ -29114,20 +29112,20 @@ msgid ""
|
|||
" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Distance between Vias of Different Nets\" \n"
|
||||
" (rule \"Distance between Vias of Different Nets\"\n"
|
||||
" (constraint hole_to_hole (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
" (rule \"Clearance between Pads of Different Nets\" \n"
|
||||
" (rule \"Clearance between Pads of Different Nets\"\n"
|
||||
" (constraint clearance (min 3.0mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Via Hole to Track Clearance\" \n"
|
||||
" (rule \"Via Hole to Track Clearance\"\n"
|
||||
" (constraint hole_clearance (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Track'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Pad to Track Clearance\" \n"
|
||||
" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n"
|
||||
"\n"
|
||||
" (rule \"Pad to Track Clearance\"\n"
|
||||
" (constraint clearance (min 0.2mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -29137,11 +29135,11 @@ msgid ""
|
|||
" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\" \n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\"\n"
|
||||
" (constraint hole_size (max 6.3mm))\n"
|
||||
" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Max Drill Hole Size PTH\" \n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size PTH\"\n"
|
||||
" (constraint hole_size (max 6.35mm))\n"
|
||||
" (condition \"A.Pad_Type == 'Through-hole'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -29149,7 +29147,7 @@ msgid ""
|
|||
" # Specify an optimal gap for a particular diff-pair\n"
|
||||
" (rule \"dp clock gap\"\n"
|
||||
" (constraint diff_pair_gap (opt \"0.8mm\"))\n"
|
||||
" (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n"
|
||||
" (condition \"A.inDiffPair('/CLK')\"))\n"
|
||||
"\n"
|
||||
" # Specify a larger clearance around any diff-pair\n"
|
||||
" (rule \"dp clearance\"\n"
|
||||
|
|
@ -31907,11 +31905,11 @@ msgstr "Platinendatei ist schreibgeschützt."
|
|||
msgid "PCB file changes are unsaved"
|
||||
msgstr "Änderungen an Platine nicht gespeichert"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1473
|
||||
#: pcbnew/pcb_edit_frame.cpp:1466
|
||||
msgid "The schematic for this board cannot be found."
|
||||
msgstr "Der Schaltplan für diese Platine kann nicht gefunden werden."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1497
|
||||
#: pcbnew/pcb_edit_frame.cpp:1490
|
||||
msgid ""
|
||||
"Cannot update the PCB because PCB editor is opened in stand-alone mode. In "
|
||||
"order to create or update PCBs from schematics, you must launch the KiCad "
|
||||
|
|
@ -31922,11 +31920,11 @@ msgstr ""
|
|||
"erstellen oder zu aktualisieren, starten Sie die KiCad-Projektverwaltung und "
|
||||
"erstellen Sie ein Projekt."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1519
|
||||
#: pcbnew/pcb_edit_frame.cpp:1512
|
||||
msgid "Eeschema netlist"
|
||||
msgstr "Eeschema Netzliste"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1530
|
||||
#: pcbnew/pcb_edit_frame.cpp:1523
|
||||
msgid ""
|
||||
"Received an error while reading netlist. Please report this issue to the "
|
||||
"KiCad team using the menu Help->Report Bug."
|
||||
|
|
@ -31934,31 +31932,31 @@ msgstr ""
|
|||
"Beim Lesen der Netzliste ist ein Fehler aufgetreten. Bitte melden Sie "
|
||||
"dieses Problem an das KiCad-Team über das Menü Hilfe->Fehler melden."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1557
|
||||
#: pcbnew/pcb_edit_frame.cpp:1550
|
||||
#, c-format
|
||||
msgid "Schematic file '%s' not found."
|
||||
msgstr "Schaltplandatei \"%s\" nicht gefunden."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1587
|
||||
#: pcbnew/pcb_edit_frame.cpp:1580
|
||||
msgid "Eeschema failed to load."
|
||||
msgstr "Eeschema konnte nicht geladen werden."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1738
|
||||
#: pcbnew/pcb_edit_frame.cpp:1731
|
||||
msgid "Edit design rules"
|
||||
msgstr "Designregeln bearbeiten"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1750
|
||||
#: pcbnew/pcb_edit_frame.cpp:1743
|
||||
msgid "Could not compile custom design rules."
|
||||
msgstr "Benutzerdefinierte Designregeln konnten nicht kompiliert werden."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1785
|
||||
#: pcbnew/pcb_edit_frame.cpp:1778
|
||||
msgid "Export Hyperlynx Layout"
|
||||
msgstr "Hyperlynx-Layout exportieren"
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:95 pcbnew/pcb_expr_evaluator.cpp:264
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:330 pcbnew/pcb_expr_evaluator.cpp:396
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:614 pcbnew/pcb_expr_evaluator.cpp:716
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:829
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:824
|
||||
#, c-format
|
||||
msgid "Missing argument to '%s'"
|
||||
msgstr "Fehlendes Argument zu '%s'"
|
||||
|
|
@ -31981,7 +31979,7 @@ msgstr "Footprint hat keine Abstandsfläche auf der Oberseite definiert."
|
|||
msgid "Footprint has no back courtyard."
|
||||
msgstr "Footprint hat keine Abstandsfläche auf der Rückseite definiert."
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1152
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1153
|
||||
msgid "must be mm, in, or mil"
|
||||
msgstr "muss mm, in oder mil sein"
|
||||
|
||||
|
|
@ -37255,6 +37253,10 @@ msgstr "KiCad-Schaltplan"
|
|||
msgid "KiCad Printed Circuit Board"
|
||||
msgstr "KiCad-Leiterplatte"
|
||||
|
||||
#, fuzzy
|
||||
#~ msgid "Net CodewxT( "
|
||||
#~ msgstr "Netz-Code"
|
||||
|
||||
#~ msgid "Save changes to schematic before closing?"
|
||||
#~ msgstr "Änderungen am Schaltplan vor dem Schließen speichern?"
|
||||
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ msgid ""
|
|||
msgstr ""
|
||||
"Project-Id-Version: KiCad\n"
|
||||
"Report-Msgid-Bugs-To: \n"
|
||||
"POT-Creation-Date: 2022-02-14 09:20-0800\n"
|
||||
"POT-Creation-Date: 2022-02-16 17:22-0800\n"
|
||||
"PO-Revision-Date: 2021-11-21 21:17+0000\n"
|
||||
"Last-Translator: aris-kimi <aris_kimi@hotmail.com>\n"
|
||||
"Language-Team: Greek <https://hosted.weblate.org/projects/kicad/master-"
|
||||
|
|
@ -4622,12 +4622,12 @@ msgstr "Συνώνυμο: "
|
|||
|
||||
#: common/filename_resolver.cpp:468
|
||||
#, fuzzy
|
||||
msgid "This path:wxT( "
|
||||
msgid "This path:"
|
||||
msgstr "Αυτή η διαδρομή:"
|
||||
|
||||
#: common/filename_resolver.cpp:471
|
||||
#, fuzzy
|
||||
msgid "Existing path:wxT( "
|
||||
msgid "Existing path:"
|
||||
msgstr "Υπάρχουσα διαδρομή:"
|
||||
|
||||
#: common/filename_resolver.cpp:473
|
||||
|
|
@ -13455,9 +13455,9 @@ msgstr "Netclass που έχουν Ανατεθεί"
|
|||
msgid "Connection Name"
|
||||
msgstr "Όνομα Σύνδεσης"
|
||||
|
||||
#: eeschema/sch_connection.cpp:415
|
||||
#, fuzzy
|
||||
msgid "Net CodewxT( "
|
||||
#: eeschema/sch_connection.cpp:415 pcbnew/dialogs/dialog_net_inspector.cpp:76
|
||||
#: pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr "Κωδικός Δικτύου"
|
||||
|
||||
#: eeschema/sch_connection.cpp:420 eeschema/sch_connection.cpp:433
|
||||
|
|
@ -19251,8 +19251,8 @@ msgid "Application failed to load:\n"
|
|||
msgstr "Αποτυχία φόρτωσης της εφαρμογής:\n"
|
||||
|
||||
#: kicad/tools/kicad_manager_control.cpp:670
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1558
|
||||
#: pcbnew/pcb_edit_frame.cpp:1588
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1551
|
||||
#: pcbnew/pcb_edit_frame.cpp:1581
|
||||
msgid "KiCad Error"
|
||||
msgstr "Σφάλμα KiCad"
|
||||
|
||||
|
|
@ -22302,7 +22302,7 @@ msgstr "Προκαθορισμένα μεγέθη"
|
|||
|
||||
#: pcbnew/dialogs/dialog_board_setup.cpp:108
|
||||
#: pcbnew/dialogs/dialog_constraints_reporter.cpp:54
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1744
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1737
|
||||
msgid "Custom Rules"
|
||||
msgstr "Προσαρμοσμένοι Κανόνες"
|
||||
|
||||
|
|
@ -25402,10 +25402,6 @@ msgstr "Χρήση πολικών συντεταγμένων"
|
|||
msgid "Move Item"
|
||||
msgstr "Μετακίνηση Αντικειμένου"
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:76 pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr "Κωδικός Δικτύου"
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:77 pcbnew/netinfo_item.cpp:74
|
||||
msgid "Net Name"
|
||||
msgstr "Όνομα Δικτύου"
|
||||
|
|
@ -28916,6 +28912,7 @@ msgid "Check rule syntax"
|
|||
msgstr "Ελέγξτε τη σύνταξη κανόνων"
|
||||
|
||||
#: pcbnew/dialogs/panel_setup_rules_help_md.h:2
|
||||
#, fuzzy
|
||||
msgid ""
|
||||
"### Top-level Clauses\n"
|
||||
"\n"
|
||||
|
|
@ -29041,8 +29038,8 @@ msgid ""
|
|||
" A.inDiffPair('<net_name>')\n"
|
||||
"True if `A` has net that is part of the specified differential pair.\n"
|
||||
"`<net_name>` is the base name of the differential pair. For example, "
|
||||
"`inDiffPair('CLK')`\n"
|
||||
"matches items in the `CLK_P` and `CLK_N` nets.\n"
|
||||
"`inDiffPair('/CLK')`\n"
|
||||
"matches items in the `/CLK_P` and `/CLK_N` nets.\n"
|
||||
"<br><br>\n"
|
||||
"\n"
|
||||
" AB.isCoupledDiffPair()\n"
|
||||
|
|
@ -29082,20 +29079,20 @@ msgid ""
|
|||
" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Distance between Vias of Different Nets\" \n"
|
||||
" (rule \"Distance between Vias of Different Nets\"\n"
|
||||
" (constraint hole_to_hole (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
" (rule \"Clearance between Pads of Different Nets\" \n"
|
||||
" (rule \"Clearance between Pads of Different Nets\"\n"
|
||||
" (constraint clearance (min 3.0mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Via Hole to Track Clearance\" \n"
|
||||
" (rule \"Via Hole to Track Clearance\"\n"
|
||||
" (constraint hole_clearance (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Track'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Pad to Track Clearance\" \n"
|
||||
" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n"
|
||||
"\n"
|
||||
" (rule \"Pad to Track Clearance\"\n"
|
||||
" (constraint clearance (min 0.2mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -29105,11 +29102,11 @@ msgid ""
|
|||
" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\" \n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\"\n"
|
||||
" (constraint hole_size (max 6.3mm))\n"
|
||||
" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Max Drill Hole Size PTH\" \n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size PTH\"\n"
|
||||
" (constraint hole_size (max 6.35mm))\n"
|
||||
" (condition \"A.Pad_Type == 'Through-hole'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -29117,7 +29114,7 @@ msgid ""
|
|||
" # Specify an optimal gap for a particular diff-pair\n"
|
||||
" (rule \"dp clock gap\"\n"
|
||||
" (constraint diff_pair_gap (opt \"0.8mm\"))\n"
|
||||
" (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n"
|
||||
" (condition \"A.inDiffPair('/CLK')\"))\n"
|
||||
"\n"
|
||||
" # Specify a larger clearance around any diff-pair\n"
|
||||
" (rule \"dp clearance\"\n"
|
||||
|
|
@ -31854,11 +31851,11 @@ msgstr "Το αρχείο πλακέτας είναι μόνο για ανάγν
|
|||
msgid "PCB file changes are unsaved"
|
||||
msgstr "Οι αλλαγές αρχείων PCB δεν είναι αποθηκευμένες"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1473
|
||||
#: pcbnew/pcb_edit_frame.cpp:1466
|
||||
msgid "The schematic for this board cannot be found."
|
||||
msgstr "Το σχηματικό για αυτήν την πλακέτα δεν μπορεί να βρεθεί."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1497
|
||||
#: pcbnew/pcb_edit_frame.cpp:1490
|
||||
msgid ""
|
||||
"Cannot update the PCB because PCB editor is opened in stand-alone mode. In "
|
||||
"order to create or update PCBs from schematics, you must launch the KiCad "
|
||||
|
|
@ -31869,11 +31866,11 @@ msgstr ""
|
|||
"σχηματικά διαγράμματα, πρέπει να εκτελέσετε τον διαχειριστή έργων Kicad και "
|
||||
"να δημιουργήσετε ένα έργο PCB."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1519
|
||||
#: pcbnew/pcb_edit_frame.cpp:1512
|
||||
msgid "Eeschema netlist"
|
||||
msgstr "Λίστα δικτύων EEschema"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1530
|
||||
#: pcbnew/pcb_edit_frame.cpp:1523
|
||||
msgid ""
|
||||
"Received an error while reading netlist. Please report this issue to the "
|
||||
"KiCad team using the menu Help->Report Bug."
|
||||
|
|
@ -31882,31 +31879,31 @@ msgstr ""
|
|||
"ζήτημα στην ομάδα του KiCad χρησιμοποιώντας το μενού Βοήθεια->Αναφορά "
|
||||
"σφάλματος."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1557
|
||||
#: pcbnew/pcb_edit_frame.cpp:1550
|
||||
#, c-format
|
||||
msgid "Schematic file '%s' not found."
|
||||
msgstr "Δεν βρέθηκε το σχηματικό αρχείο \"%s\"."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1587
|
||||
#: pcbnew/pcb_edit_frame.cpp:1580
|
||||
msgid "Eeschema failed to load."
|
||||
msgstr "Αποτυχία φόρτωσης του Eeschema."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1738
|
||||
#: pcbnew/pcb_edit_frame.cpp:1731
|
||||
msgid "Edit design rules"
|
||||
msgstr "Επεξεργασία κανόνων σχεδίασης"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1750
|
||||
#: pcbnew/pcb_edit_frame.cpp:1743
|
||||
msgid "Could not compile custom design rules."
|
||||
msgstr "Αδυναμία επεξεργασίας ειδικών κανόνων σχεδίασης."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1785
|
||||
#: pcbnew/pcb_edit_frame.cpp:1778
|
||||
msgid "Export Hyperlynx Layout"
|
||||
msgstr "Εξαγωγή Σχεδίασης Hyperlynx"
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:95 pcbnew/pcb_expr_evaluator.cpp:264
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:330 pcbnew/pcb_expr_evaluator.cpp:396
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:614 pcbnew/pcb_expr_evaluator.cpp:716
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:829
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:824
|
||||
#, c-format
|
||||
msgid "Missing argument to '%s'"
|
||||
msgstr "Λείπει παράμετρος από '%s'"
|
||||
|
|
@ -31928,7 +31925,7 @@ msgstr "Το αποτύπωμα δεν έχει μπροστινό χώρο απ
|
|||
msgid "Footprint has no back courtyard."
|
||||
msgstr "Το αποτύπωμα δεν έχει πίσω χώρο αποτυπώματος."
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1152
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1153
|
||||
msgid "must be mm, in, or mil"
|
||||
msgstr "πρέπει να είναι mm, in ή mil"
|
||||
|
||||
|
|
@ -37200,6 +37197,10 @@ msgstr "Σχηματικό KiCad"
|
|||
msgid "KiCad Printed Circuit Board"
|
||||
msgstr "Πλακέτα Τυπωμένου Κυκλώματος KiCad"
|
||||
|
||||
#, fuzzy
|
||||
#~ msgid "Net CodewxT( "
|
||||
#~ msgstr "Κωδικός Δικτύου"
|
||||
|
||||
#~ msgid "Save changes to schematic before closing?"
|
||||
#~ msgstr "Αποθήκευση αλλαγών στο σχηματικό πριν το κλείσιμο;"
|
||||
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@ msgid ""
|
|||
msgstr ""
|
||||
"Project-Id-Version: KiCad\n"
|
||||
"Report-Msgid-Bugs-To: \n"
|
||||
"POT-Creation-Date: 2022-02-14 09:20-0800\n"
|
||||
"POT-Creation-Date: 2022-02-16 17:22-0800\n"
|
||||
"PO-Revision-Date: 2018-07-15 17:07+0200\n"
|
||||
"Last-Translator: Simon Richter <Simon.Richter@hogyros.de>\n"
|
||||
"Language-Team: Simon Richter <Simon.Richter@hogyros.de>\n"
|
||||
|
|
@ -2787,11 +2787,11 @@ msgstr "3D model search path"
|
|||
msgid "Alias: "
|
||||
msgstr "Alias: "
|
||||
|
||||
msgid "This path:wxT( "
|
||||
msgstr "This path:wxT( "
|
||||
msgid "This path:"
|
||||
msgstr "This path:"
|
||||
|
||||
msgid "Existing path:wxT( "
|
||||
msgstr "Existing path:wxT( "
|
||||
msgid "Existing path:"
|
||||
msgstr "Existing path:"
|
||||
|
||||
msgid "Bad alias (duplicate name)"
|
||||
msgstr "Bad alias (duplicate name)"
|
||||
|
|
@ -9006,8 +9006,8 @@ msgstr "Assigned Netclass"
|
|||
msgid "Connection Name"
|
||||
msgstr "Connection Name"
|
||||
|
||||
msgid "Net CodewxT( "
|
||||
msgstr "Net CodewxT( "
|
||||
msgid "Net Code"
|
||||
msgstr "Net Code"
|
||||
|
||||
#, c-format
|
||||
msgid "Bus Alias %s Members"
|
||||
|
|
@ -17733,9 +17733,6 @@ msgstr "Use polar coordinates"
|
|||
msgid "Move Item"
|
||||
msgstr "Move Item"
|
||||
|
||||
msgid "Net Code"
|
||||
msgstr "Net Code"
|
||||
|
||||
msgid "Net Name"
|
||||
msgstr "Net Name"
|
||||
|
||||
|
|
@ -20358,8 +20355,8 @@ msgid ""
|
|||
" A.inDiffPair('<net_name>')\n"
|
||||
"True if `A` has net that is part of the specified differential pair.\n"
|
||||
"`<net_name>` is the base name of the differential pair. For example, "
|
||||
"`inDiffPair('CLK')`\n"
|
||||
"matches items in the `CLK_P` and `CLK_N` nets.\n"
|
||||
"`inDiffPair('/CLK')`\n"
|
||||
"matches items in the `/CLK_P` and `/CLK_N` nets.\n"
|
||||
"<br><br>\n"
|
||||
"\n"
|
||||
" AB.isCoupledDiffPair()\n"
|
||||
|
|
@ -20399,20 +20396,20 @@ msgid ""
|
|||
" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Distance between Vias of Different Nets\" \n"
|
||||
" (rule \"Distance between Vias of Different Nets\"\n"
|
||||
" (constraint hole_to_hole (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
" (rule \"Clearance between Pads of Different Nets\" \n"
|
||||
" (rule \"Clearance between Pads of Different Nets\"\n"
|
||||
" (constraint clearance (min 3.0mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Via Hole to Track Clearance\" \n"
|
||||
" (rule \"Via Hole to Track Clearance\"\n"
|
||||
" (constraint hole_clearance (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Track'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Pad to Track Clearance\" \n"
|
||||
" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n"
|
||||
"\n"
|
||||
" (rule \"Pad to Track Clearance\"\n"
|
||||
" (constraint clearance (min 0.2mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -20422,11 +20419,11 @@ msgid ""
|
|||
" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\" \n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\"\n"
|
||||
" (constraint hole_size (max 6.3mm))\n"
|
||||
" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Max Drill Hole Size PTH\" \n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size PTH\"\n"
|
||||
" (constraint hole_size (max 6.35mm))\n"
|
||||
" (condition \"A.Pad_Type == 'Through-hole'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -20434,7 +20431,7 @@ msgid ""
|
|||
" # Specify an optimal gap for a particular diff-pair\n"
|
||||
" (rule \"dp clock gap\"\n"
|
||||
" (constraint diff_pair_gap (opt \"0.8mm\"))\n"
|
||||
" (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n"
|
||||
" (condition \"A.inDiffPair('/CLK')\"))\n"
|
||||
"\n"
|
||||
" # Specify a larger clearance around any diff-pair\n"
|
||||
" (rule \"dp clearance\"\n"
|
||||
|
|
@ -20565,8 +20562,8 @@ msgstr ""
|
|||
" A.inDiffPair('<net_name>')\n"
|
||||
"True if `A` has net that is part of the specified differential pair.\n"
|
||||
"`<net_name>` is the base name of the differential pair. For example, "
|
||||
"`inDiffPair('CLK')`\n"
|
||||
"matches items in the `CLK_P` and `CLK_N` nets.\n"
|
||||
"`inDiffPair('/CLK')`\n"
|
||||
"matches items in the `/CLK_P` and `/CLK_N` nets.\n"
|
||||
"<br><br>\n"
|
||||
"\n"
|
||||
" AB.isCoupledDiffPair()\n"
|
||||
|
|
@ -20606,20 +20603,20 @@ msgstr ""
|
|||
" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Distance between Vias of Different Nets\" \n"
|
||||
" (rule \"Distance between Vias of Different Nets\"\n"
|
||||
" (constraint hole_to_hole (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
" (rule \"Clearance between Pads of Different Nets\" \n"
|
||||
" (rule \"Clearance between Pads of Different Nets\"\n"
|
||||
" (constraint clearance (min 3.0mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Via Hole to Track Clearance\" \n"
|
||||
" (rule \"Via Hole to Track Clearance\"\n"
|
||||
" (constraint hole_clearance (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Track'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Pad to Track Clearance\" \n"
|
||||
" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n"
|
||||
"\n"
|
||||
" (rule \"Pad to Track Clearance\"\n"
|
||||
" (constraint clearance (min 0.2mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -20629,11 +20626,11 @@ msgstr ""
|
|||
" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\" \n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\"\n"
|
||||
" (constraint hole_size (max 6.3mm))\n"
|
||||
" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Max Drill Hole Size PTH\" \n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size PTH\"\n"
|
||||
" (constraint hole_size (max 6.35mm))\n"
|
||||
" (condition \"A.Pad_Type == 'Through-hole'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -20641,7 +20638,7 @@ msgstr ""
|
|||
" # Specify an optimal gap for a particular diff-pair\n"
|
||||
" (rule \"dp clock gap\"\n"
|
||||
" (constraint diff_pair_gap (opt \"0.8mm\"))\n"
|
||||
" (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n"
|
||||
" (condition \"A.inDiffPair('/CLK')\"))\n"
|
||||
"\n"
|
||||
" # Specify a larger clearance around any diff-pair\n"
|
||||
" (rule \"dp clearance\"\n"
|
||||
|
|
@ -26562,11 +26559,437 @@ msgstr "KiCad Schematic"
|
|||
msgid "KiCad Printed Circuit Board"
|
||||
msgstr "KiCad Printed Circuit Board"
|
||||
|
||||
#~ msgid "This path:"
|
||||
#~ msgstr "This path:"
|
||||
#~ msgid "This path:wxT( "
|
||||
#~ msgstr "This path:wxT( "
|
||||
|
||||
#~ msgid "Existing path:"
|
||||
#~ msgstr "Existing path:"
|
||||
#~ msgid "Existing path:wxT( "
|
||||
#~ msgstr "Existing path:wxT( "
|
||||
|
||||
#~ msgid "Net CodewxT( "
|
||||
#~ msgstr "Net CodewxT( "
|
||||
|
||||
#~ msgid ""
|
||||
#~ "### Top-level Clauses\n"
|
||||
#~ "\n"
|
||||
#~ " (version <number>)\n"
|
||||
#~ "\n"
|
||||
#~ " (rule <rule_name> <rule_clause> ...)\n"
|
||||
#~ "\n"
|
||||
#~ "\n"
|
||||
#~ "<br><br>\n"
|
||||
#~ "\n"
|
||||
#~ "### Rule Clauses\n"
|
||||
#~ "\n"
|
||||
#~ " (constraint <constraint_type> ...)\n"
|
||||
#~ "\n"
|
||||
#~ " (condition \"<expression>\")\n"
|
||||
#~ "\n"
|
||||
#~ " (layer \"<layer_name>\")\n"
|
||||
#~ "\n"
|
||||
#~ "\n"
|
||||
#~ "<br><br>\n"
|
||||
#~ "\n"
|
||||
#~ "### Constraint Types\n"
|
||||
#~ "\n"
|
||||
#~ " * annular\\_width\n"
|
||||
#~ " * clearance\n"
|
||||
#~ " * courtyard_clearance\n"
|
||||
#~ " * diff\\_pair\\_gap\n"
|
||||
#~ " * diff\\_pair\\_uncoupled\n"
|
||||
#~ " * disallow\n"
|
||||
#~ " * edge\\_clearance\n"
|
||||
#~ " * length\n"
|
||||
#~ " * hole\\_clearance\n"
|
||||
#~ " * hole\\_size\n"
|
||||
#~ " * silk\\_clearance\n"
|
||||
#~ " * skew\n"
|
||||
#~ " * track\\_width\n"
|
||||
#~ " * via\\_count\n"
|
||||
#~ " * via\\_diameter\n"
|
||||
#~ "\n"
|
||||
#~ "\n"
|
||||
#~ "<br><br>\n"
|
||||
#~ "\n"
|
||||
#~ "### Item Types\n"
|
||||
#~ "\n"
|
||||
#~ " * buried_via\n"
|
||||
#~ " * graphic\n"
|
||||
#~ " * hole\n"
|
||||
#~ " * micro_via\n"
|
||||
#~ " * pad\n"
|
||||
#~ " * text\n"
|
||||
#~ " * track\n"
|
||||
#~ " * via\n"
|
||||
#~ " * zone\n"
|
||||
#~ "\n"
|
||||
#~ "<br>\n"
|
||||
#~ "\n"
|
||||
#~ "### Examples\n"
|
||||
#~ "\n"
|
||||
#~ " (version 1)\n"
|
||||
#~ "\n"
|
||||
#~ " (rule HV\n"
|
||||
#~ " (constraint clearance (min 1.5mm))\n"
|
||||
#~ " (condition \"A.NetClass == 'HV'\"))\n"
|
||||
#~ "\n"
|
||||
#~ "\n"
|
||||
#~ " (rule HV\n"
|
||||
#~ " (layer outer)\n"
|
||||
#~ " (constraint clearance (min 1.5mm))\n"
|
||||
#~ " (condition \"A.NetClass == 'HV'\"))\n"
|
||||
#~ "\n"
|
||||
#~ "\n"
|
||||
#~ " (rule HV_HV\n"
|
||||
#~ " # wider clearance between HV tracks\n"
|
||||
#~ " (constraint clearance (min \"1.5mm + 2.0mm\"))\n"
|
||||
#~ " (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n"
|
||||
#~ "\n"
|
||||
#~ "\n"
|
||||
#~ " (rule HV_unshielded\n"
|
||||
#~ " (constraint clearance (min 2mm))\n"
|
||||
#~ " (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n"
|
||||
#~ "<br><br>\n"
|
||||
#~ "\n"
|
||||
#~ "### Notes\n"
|
||||
#~ "\n"
|
||||
#~ "Version clause must be the first clause. It indicates the syntax version "
|
||||
#~ "of the file so that \n"
|
||||
#~ "future rules parsers can perform automatic updates. It should be\n"
|
||||
#~ "set to \"1\".\n"
|
||||
#~ "\n"
|
||||
#~ "Rules should be ordered by specificity. Later rules take\n"
|
||||
#~ "precedence over earlier rules; once a matching rule is found\n"
|
||||
#~ "no further rules will be checked.\n"
|
||||
#~ "\n"
|
||||
#~ "Use Ctrl+/ to comment or uncomment line(s).\n"
|
||||
#~ "<br><br><br>\n"
|
||||
#~ "\n"
|
||||
#~ "### Expression functions\n"
|
||||
#~ "\n"
|
||||
#~ "All function parameters support simple wildcards (`*` and `?`).\n"
|
||||
#~ "<br><br>\n"
|
||||
#~ "\n"
|
||||
#~ " A.insideCourtyard('<footprint_refdes>')\n"
|
||||
#~ "True if any part of `A` lies within the given footprint's principal "
|
||||
#~ "courtyard.\n"
|
||||
#~ "<br><br>\n"
|
||||
#~ "\n"
|
||||
#~ " A.insideFrontCourtyard('<footprint_refdes>')\n"
|
||||
#~ "True if any part of `A` lies within the given footprint's front "
|
||||
#~ "courtyard.\n"
|
||||
#~ "<br><br>\n"
|
||||
#~ "\n"
|
||||
#~ " A.insideBackCourtyard('<footprint_refdes>')\n"
|
||||
#~ "True if any part of `A` lies within the given footprint's back "
|
||||
#~ "courtyard.\n"
|
||||
#~ "<br><br>\n"
|
||||
#~ "\n"
|
||||
#~ " A.insideArea('<zone_name>')\n"
|
||||
#~ "True if any part of `A` lies within the given zone's outline.\n"
|
||||
#~ "<br><br>\n"
|
||||
#~ "\n"
|
||||
#~ " A.isPlated()\n"
|
||||
#~ "True if `A` has a hole which is plated.\n"
|
||||
#~ "<br><br>\n"
|
||||
#~ "\n"
|
||||
#~ " A.inDiffPair('<net_name>')\n"
|
||||
#~ "True if `A` has net that is part of the specified differential pair.\n"
|
||||
#~ "`<net_name>` is the base name of the differential pair. For example, "
|
||||
#~ "`inDiffPair('CLK')`\n"
|
||||
#~ "matches items in the `CLK_P` and `CLK_N` nets.\n"
|
||||
#~ "<br><br>\n"
|
||||
#~ "\n"
|
||||
#~ " AB.isCoupledDiffPair()\n"
|
||||
#~ "True if `A` and `B` are members of the same diff pair.\n"
|
||||
#~ "<br><br>\n"
|
||||
#~ "\n"
|
||||
#~ " A.memberOf('<group_name>')\n"
|
||||
#~ "True if `A` is a member of the given group. Includes nested membership.\n"
|
||||
#~ "<br><br>\n"
|
||||
#~ "\n"
|
||||
#~ " A.existsOnLayer('<layer_name>')\n"
|
||||
#~ "True if `A` exists on the given layer. The layer name can be\n"
|
||||
#~ "either the name assigned in Board Setup > Board Editor Layers or\n"
|
||||
#~ "the canonical name (ie: `F.Cu`).\n"
|
||||
#~ "\n"
|
||||
#~ "NB: this returns true if `A` is on the given layer, independently\n"
|
||||
#~ "of whether or not the rule is being evaluated for that layer.\n"
|
||||
#~ "For the latter use a `(layer \"layer_name\")` clause in the rule.\n"
|
||||
#~ "<br><br><br>\n"
|
||||
#~ "\n"
|
||||
#~ "### More Examples\n"
|
||||
#~ "\n"
|
||||
#~ " (rule \"copper keepout\"\n"
|
||||
#~ " (constraint disallow track via zone)\n"
|
||||
#~ " (condition \"A.insideArea('zone3')\"))\n"
|
||||
#~ "\n"
|
||||
#~ "\n"
|
||||
#~ " (rule \"BGA neckdown\"\n"
|
||||
#~ " (constraint track_width (min 0.2mm) (opt 0.25mm))\n"
|
||||
#~ " (constraint clearance (min 0.05mm) (opt 0.08mm))\n"
|
||||
#~ " (condition \"A.insideCourtyard('U3')\"))\n"
|
||||
#~ "\n"
|
||||
#~ "\n"
|
||||
#~ " # prevent silk over tented vias\n"
|
||||
#~ " (rule silk_over_via\n"
|
||||
#~ " (constraint silk_clearance (min 0.2mm))\n"
|
||||
#~ " (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n"
|
||||
#~ "\n"
|
||||
#~ "\n"
|
||||
#~ " (rule \"Distance between Vias of Different Nets\" \n"
|
||||
#~ " (constraint hole_to_hole (min 0.254mm))\n"
|
||||
#~ " (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net"
|
||||
#~ "\"))\n"
|
||||
#~ "\n"
|
||||
#~ " (rule \"Clearance between Pads of Different Nets\" \n"
|
||||
#~ " (constraint clearance (min 3.0mm))\n"
|
||||
#~ " (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net"
|
||||
#~ "\"))\n"
|
||||
#~ "\n"
|
||||
#~ "\n"
|
||||
#~ " (rule \"Via Hole to Track Clearance\" \n"
|
||||
#~ " (constraint hole_clearance (min 0.254mm))\n"
|
||||
#~ " (condition \"A.Type =='Via' && B.Type =='Track'\"))\n"
|
||||
#~ " \n"
|
||||
#~ " (rule \"Pad to Track Clearance\" \n"
|
||||
#~ " (constraint clearance (min 0.2mm))\n"
|
||||
#~ " (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n"
|
||||
#~ "\n"
|
||||
#~ "\n"
|
||||
#~ " (rule \"clearance-to-1mm-cutout\"\n"
|
||||
#~ " (constraint clearance (min 0.8mm))\n"
|
||||
#~ " (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n"
|
||||
#~ "\n"
|
||||
#~ "\n"
|
||||
#~ " (rule \"Max Drill Hole Size Mechanical\" \n"
|
||||
#~ " (constraint hole_size (max 6.3mm))\n"
|
||||
#~ " (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n"
|
||||
#~ " \n"
|
||||
#~ " (rule \"Max Drill Hole Size PTH\" \n"
|
||||
#~ " (constraint hole_size (max 6.35mm))\n"
|
||||
#~ " (condition \"A.Pad_Type == 'Through-hole'\"))\n"
|
||||
#~ "\n"
|
||||
#~ "\n"
|
||||
#~ " # Specify an optimal gap for a particular diff-pair\n"
|
||||
#~ " (rule \"dp clock gap\"\n"
|
||||
#~ " (constraint diff_pair_gap (opt \"0.8mm\"))\n"
|
||||
#~ " (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n"
|
||||
#~ "\n"
|
||||
#~ " # Specify a larger clearance around any diff-pair\n"
|
||||
#~ " (rule \"dp clearance\"\n"
|
||||
#~ " (constraint clearance (min \"1.5mm\"))\n"
|
||||
#~ " (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n"
|
||||
#~ msgstr ""
|
||||
#~ "### Top-level Clauses\n"
|
||||
#~ "\n"
|
||||
#~ " (version <number>)\n"
|
||||
#~ "\n"
|
||||
#~ " (rule <rule_name> <rule_clause> ...)\n"
|
||||
#~ "\n"
|
||||
#~ "\n"
|
||||
#~ "<br><br>\n"
|
||||
#~ "\n"
|
||||
#~ "### Rule Clauses\n"
|
||||
#~ "\n"
|
||||
#~ " (constraint <constraint_type> ...)\n"
|
||||
#~ "\n"
|
||||
#~ " (condition \"<expression>\")\n"
|
||||
#~ "\n"
|
||||
#~ " (layer \"<layer_name>\")\n"
|
||||
#~ "\n"
|
||||
#~ "\n"
|
||||
#~ "<br><br>\n"
|
||||
#~ "\n"
|
||||
#~ "### Constraint Types\n"
|
||||
#~ "\n"
|
||||
#~ " * annular\\_width\n"
|
||||
#~ " * clearance\n"
|
||||
#~ " * courtyard_clearance\n"
|
||||
#~ " * diff\\_pair\\_gap\n"
|
||||
#~ " * diff\\_pair\\_uncoupled\n"
|
||||
#~ " * disallow\n"
|
||||
#~ " * edge\\_clearance\n"
|
||||
#~ " * length\n"
|
||||
#~ " * hole\\_clearance\n"
|
||||
#~ " * hole\\_size\n"
|
||||
#~ " * silk\\_clearance\n"
|
||||
#~ " * skew\n"
|
||||
#~ " * track\\_width\n"
|
||||
#~ " * via\\_count\n"
|
||||
#~ " * via\\_diameter\n"
|
||||
#~ "\n"
|
||||
#~ "\n"
|
||||
#~ "<br><br>\n"
|
||||
#~ "\n"
|
||||
#~ "### Item Types\n"
|
||||
#~ "\n"
|
||||
#~ " * buried_via\n"
|
||||
#~ " * graphic\n"
|
||||
#~ " * hole\n"
|
||||
#~ " * micro_via\n"
|
||||
#~ " * pad\n"
|
||||
#~ " * text\n"
|
||||
#~ " * track\n"
|
||||
#~ " * via\n"
|
||||
#~ " * zone\n"
|
||||
#~ "\n"
|
||||
#~ "<br>\n"
|
||||
#~ "\n"
|
||||
#~ "### Examples\n"
|
||||
#~ "\n"
|
||||
#~ " (version 1)\n"
|
||||
#~ "\n"
|
||||
#~ " (rule HV\n"
|
||||
#~ " (constraint clearance (min 1.5mm))\n"
|
||||
#~ " (condition \"A.NetClass == 'HV'\"))\n"
|
||||
#~ "\n"
|
||||
#~ "\n"
|
||||
#~ " (rule HV\n"
|
||||
#~ " (layer outer)\n"
|
||||
#~ " (constraint clearance (min 1.5mm))\n"
|
||||
#~ " (condition \"A.NetClass == 'HV'\"))\n"
|
||||
#~ "\n"
|
||||
#~ "\n"
|
||||
#~ " (rule HV_HV\n"
|
||||
#~ " # wider clearance between HV tracks\n"
|
||||
#~ " (constraint clearance (min \"1.5mm + 2.0mm\"))\n"
|
||||
#~ " (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n"
|
||||
#~ "\n"
|
||||
#~ "\n"
|
||||
#~ " (rule HV_unshielded\n"
|
||||
#~ " (constraint clearance (min 2mm))\n"
|
||||
#~ " (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n"
|
||||
#~ "<br><br>\n"
|
||||
#~ "\n"
|
||||
#~ "### Notes\n"
|
||||
#~ "\n"
|
||||
#~ "Version clause must be the first clause. It indicates the syntax version "
|
||||
#~ "of the file so that \n"
|
||||
#~ "future rules parsers can perform automatic updates. It should be\n"
|
||||
#~ "set to \"1\".\n"
|
||||
#~ "\n"
|
||||
#~ "Rules should be ordered by specificity. Later rules take\n"
|
||||
#~ "precedence over earlier rules; once a matching rule is found\n"
|
||||
#~ "no further rules will be checked.\n"
|
||||
#~ "\n"
|
||||
#~ "Use Ctrl+/ to comment or uncomment line(s).\n"
|
||||
#~ "<br><br><br>\n"
|
||||
#~ "\n"
|
||||
#~ "### Expression functions\n"
|
||||
#~ "\n"
|
||||
#~ "All function parameters support simple wildcards (`*` and `?`).\n"
|
||||
#~ "<br><br>\n"
|
||||
#~ "\n"
|
||||
#~ " A.insideCourtyard('<footprint_refdes>')\n"
|
||||
#~ "True if any part of `A` lies within the given footprint's principal "
|
||||
#~ "courtyard.\n"
|
||||
#~ "<br><br>\n"
|
||||
#~ "\n"
|
||||
#~ " A.insideFrontCourtyard('<footprint_refdes>')\n"
|
||||
#~ "True if any part of `A` lies within the given footprint's front "
|
||||
#~ "courtyard.\n"
|
||||
#~ "<br><br>\n"
|
||||
#~ "\n"
|
||||
#~ " A.insideBackCourtyard('<footprint_refdes>')\n"
|
||||
#~ "True if any part of `A` lies within the given footprint's back "
|
||||
#~ "courtyard.\n"
|
||||
#~ "<br><br>\n"
|
||||
#~ "\n"
|
||||
#~ " A.insideArea('<zone_name>')\n"
|
||||
#~ "True if any part of `A` lies within the given zone's outline.\n"
|
||||
#~ "<br><br>\n"
|
||||
#~ "\n"
|
||||
#~ " A.isPlated()\n"
|
||||
#~ "True if `A` has a hole which is plated.\n"
|
||||
#~ "<br><br>\n"
|
||||
#~ "\n"
|
||||
#~ " A.inDiffPair('<net_name>')\n"
|
||||
#~ "True if `A` has net that is part of the specified differential pair.\n"
|
||||
#~ "`<net_name>` is the base name of the differential pair. For example, "
|
||||
#~ "`inDiffPair('CLK')`\n"
|
||||
#~ "matches items in the `CLK_P` and `CLK_N` nets.\n"
|
||||
#~ "<br><br>\n"
|
||||
#~ "\n"
|
||||
#~ " AB.isCoupledDiffPair()\n"
|
||||
#~ "True if `A` and `B` are members of the same diff pair.\n"
|
||||
#~ "<br><br>\n"
|
||||
#~ "\n"
|
||||
#~ " A.memberOf('<group_name>')\n"
|
||||
#~ "True if `A` is a member of the given group. Includes nested membership.\n"
|
||||
#~ "<br><br>\n"
|
||||
#~ "\n"
|
||||
#~ " A.existsOnLayer('<layer_name>')\n"
|
||||
#~ "True if `A` exists on the given layer. The layer name can be\n"
|
||||
#~ "either the name assigned in Board Setup > Board Editor Layers or\n"
|
||||
#~ "the canonical name (ie: `F.Cu`).\n"
|
||||
#~ "\n"
|
||||
#~ "NB: this returns true if `A` is on the given layer, independently\n"
|
||||
#~ "of whether or not the rule is being evaluated for that layer.\n"
|
||||
#~ "For the latter use a `(layer \"layer_name\")` clause in the rule.\n"
|
||||
#~ "<br><br><br>\n"
|
||||
#~ "\n"
|
||||
#~ "### More Examples\n"
|
||||
#~ "\n"
|
||||
#~ " (rule \"copper keepout\"\n"
|
||||
#~ " (constraint disallow track via zone)\n"
|
||||
#~ " (condition \"A.insideArea('zone3')\"))\n"
|
||||
#~ "\n"
|
||||
#~ "\n"
|
||||
#~ " (rule \"BGA neckdown\"\n"
|
||||
#~ " (constraint track_width (min 0.2mm) (opt 0.25mm))\n"
|
||||
#~ " (constraint clearance (min 0.05mm) (opt 0.08mm))\n"
|
||||
#~ " (condition \"A.insideCourtyard('U3')\"))\n"
|
||||
#~ "\n"
|
||||
#~ "\n"
|
||||
#~ " # prevent silk over tented vias\n"
|
||||
#~ " (rule silk_over_via\n"
|
||||
#~ " (constraint silk_clearance (min 0.2mm))\n"
|
||||
#~ " (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n"
|
||||
#~ "\n"
|
||||
#~ "\n"
|
||||
#~ " (rule \"Distance between Vias of Different Nets\" \n"
|
||||
#~ " (constraint hole_to_hole (min 0.254mm))\n"
|
||||
#~ " (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net"
|
||||
#~ "\"))\n"
|
||||
#~ "\n"
|
||||
#~ " (rule \"Clearance between Pads of Different Nets\" \n"
|
||||
#~ " (constraint clearance (min 3.0mm))\n"
|
||||
#~ " (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net"
|
||||
#~ "\"))\n"
|
||||
#~ "\n"
|
||||
#~ "\n"
|
||||
#~ " (rule \"Via Hole to Track Clearance\" \n"
|
||||
#~ " (constraint hole_clearance (min 0.254mm))\n"
|
||||
#~ " (condition \"A.Type =='Via' && B.Type =='Track'\"))\n"
|
||||
#~ " \n"
|
||||
#~ " (rule \"Pad to Track Clearance\" \n"
|
||||
#~ " (constraint clearance (min 0.2mm))\n"
|
||||
#~ " (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n"
|
||||
#~ "\n"
|
||||
#~ "\n"
|
||||
#~ " (rule \"clearance-to-1mm-cutout\"\n"
|
||||
#~ " (constraint clearance (min 0.8mm))\n"
|
||||
#~ " (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n"
|
||||
#~ "\n"
|
||||
#~ "\n"
|
||||
#~ " (rule \"Max Drill Hole Size Mechanical\" \n"
|
||||
#~ " (constraint hole_size (max 6.3mm))\n"
|
||||
#~ " (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n"
|
||||
#~ " \n"
|
||||
#~ " (rule \"Max Drill Hole Size PTH\" \n"
|
||||
#~ " (constraint hole_size (max 6.35mm))\n"
|
||||
#~ " (condition \"A.Pad_Type == 'Through-hole'\"))\n"
|
||||
#~ "\n"
|
||||
#~ "\n"
|
||||
#~ " # Specify an optimal gap for a particular diff-pair\n"
|
||||
#~ " (rule \"dp clock gap\"\n"
|
||||
#~ " (constraint diff_pair_gap (opt \"0.8mm\"))\n"
|
||||
#~ " (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n"
|
||||
#~ "\n"
|
||||
#~ " # Specify a larger clearance around any diff-pair\n"
|
||||
#~ " (rule \"dp clearance\"\n"
|
||||
#~ " (constraint clearance (min \"1.5mm\"))\n"
|
||||
#~ " (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n"
|
||||
|
||||
#, c-format
|
||||
#~ msgid "Storage file not fully parsed (%d bytes remaining)."
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@ msgid ""
|
|||
msgstr ""
|
||||
"Project-Id-Version: KiCad Spanish Translation\n"
|
||||
"Report-Msgid-Bugs-To: \n"
|
||||
"POT-Creation-Date: 2022-02-14 09:20-0800\n"
|
||||
"POT-Creation-Date: 2022-02-16 17:22-0800\n"
|
||||
"PO-Revision-Date: 2022-01-03 10:45+0000\n"
|
||||
"Last-Translator: Jose Perez <mirror.k2@gmail.com>\n"
|
||||
"Language-Team: Spanish <https://hosted.weblate.org/projects/kicad/v6/es/>\n"
|
||||
|
|
@ -4606,12 +4606,12 @@ msgstr "Alias: "
|
|||
|
||||
#: common/filename_resolver.cpp:468
|
||||
#, fuzzy
|
||||
msgid "This path:wxT( "
|
||||
msgid "This path:"
|
||||
msgstr "Esta ruta:"
|
||||
|
||||
#: common/filename_resolver.cpp:471
|
||||
#, fuzzy
|
||||
msgid "Existing path:wxT( "
|
||||
msgid "Existing path:"
|
||||
msgstr "Ruta existente:"
|
||||
|
||||
#: common/filename_resolver.cpp:473
|
||||
|
|
@ -13432,9 +13432,9 @@ msgstr "Clase de red asignada"
|
|||
msgid "Connection Name"
|
||||
msgstr "Nombre de conexión"
|
||||
|
||||
#: eeschema/sch_connection.cpp:415
|
||||
#, fuzzy
|
||||
msgid "Net CodewxT( "
|
||||
#: eeschema/sch_connection.cpp:415 pcbnew/dialogs/dialog_net_inspector.cpp:76
|
||||
#: pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr "Código red"
|
||||
|
||||
#: eeschema/sch_connection.cpp:420 eeschema/sch_connection.cpp:433
|
||||
|
|
@ -19225,8 +19225,8 @@ msgid "Application failed to load:\n"
|
|||
msgstr "Fallo al cargar la aplicación:\n"
|
||||
|
||||
#: kicad/tools/kicad_manager_control.cpp:670
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1558
|
||||
#: pcbnew/pcb_edit_frame.cpp:1588
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1551
|
||||
#: pcbnew/pcb_edit_frame.cpp:1581
|
||||
msgid "KiCad Error"
|
||||
msgstr "Error de KiCad"
|
||||
|
||||
|
|
@ -22289,7 +22289,7 @@ msgstr "Tamaños predefinidos"
|
|||
|
||||
#: pcbnew/dialogs/dialog_board_setup.cpp:108
|
||||
#: pcbnew/dialogs/dialog_constraints_reporter.cpp:54
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1744
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1737
|
||||
msgid "Custom Rules"
|
||||
msgstr "Reglas personalizadas"
|
||||
|
||||
|
|
@ -25364,10 +25364,6 @@ msgstr "Utilizar coordenadas polares"
|
|||
msgid "Move Item"
|
||||
msgstr "Mover elemento"
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:76 pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr "Código red"
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:77 pcbnew/netinfo_item.cpp:74
|
||||
msgid "Net Name"
|
||||
msgstr "Nombre red"
|
||||
|
|
@ -28854,6 +28850,7 @@ msgid "Check rule syntax"
|
|||
msgstr "Verificar reglas de sintaxis"
|
||||
|
||||
#: pcbnew/dialogs/panel_setup_rules_help_md.h:2
|
||||
#, fuzzy
|
||||
msgid ""
|
||||
"### Top-level Clauses\n"
|
||||
"\n"
|
||||
|
|
@ -28979,8 +28976,8 @@ msgid ""
|
|||
" A.inDiffPair('<net_name>')\n"
|
||||
"True if `A` has net that is part of the specified differential pair.\n"
|
||||
"`<net_name>` is the base name of the differential pair. For example, "
|
||||
"`inDiffPair('CLK')`\n"
|
||||
"matches items in the `CLK_P` and `CLK_N` nets.\n"
|
||||
"`inDiffPair('/CLK')`\n"
|
||||
"matches items in the `/CLK_P` and `/CLK_N` nets.\n"
|
||||
"<br><br>\n"
|
||||
"\n"
|
||||
" AB.isCoupledDiffPair()\n"
|
||||
|
|
@ -29020,20 +29017,20 @@ msgid ""
|
|||
" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Distance between Vias of Different Nets\" \n"
|
||||
" (rule \"Distance between Vias of Different Nets\"\n"
|
||||
" (constraint hole_to_hole (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
" (rule \"Clearance between Pads of Different Nets\" \n"
|
||||
" (rule \"Clearance between Pads of Different Nets\"\n"
|
||||
" (constraint clearance (min 3.0mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Via Hole to Track Clearance\" \n"
|
||||
" (rule \"Via Hole to Track Clearance\"\n"
|
||||
" (constraint hole_clearance (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Track'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Pad to Track Clearance\" \n"
|
||||
" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n"
|
||||
"\n"
|
||||
" (rule \"Pad to Track Clearance\"\n"
|
||||
" (constraint clearance (min 0.2mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -29043,11 +29040,11 @@ msgid ""
|
|||
" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\" \n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\"\n"
|
||||
" (constraint hole_size (max 6.3mm))\n"
|
||||
" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Max Drill Hole Size PTH\" \n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size PTH\"\n"
|
||||
" (constraint hole_size (max 6.35mm))\n"
|
||||
" (condition \"A.Pad_Type == 'Through-hole'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -29055,7 +29052,7 @@ msgid ""
|
|||
" # Specify an optimal gap for a particular diff-pair\n"
|
||||
" (rule \"dp clock gap\"\n"
|
||||
" (constraint diff_pair_gap (opt \"0.8mm\"))\n"
|
||||
" (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n"
|
||||
" (condition \"A.inDiffPair('/CLK')\"))\n"
|
||||
"\n"
|
||||
" # Specify a larger clearance around any diff-pair\n"
|
||||
" (rule \"dp clearance\"\n"
|
||||
|
|
@ -31803,11 +31800,11 @@ msgstr "El archivo de placa es de solo lectura."
|
|||
msgid "PCB file changes are unsaved"
|
||||
msgstr "Los cambios a la placa no están guardados"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1473
|
||||
#: pcbnew/pcb_edit_frame.cpp:1466
|
||||
msgid "The schematic for this board cannot be found."
|
||||
msgstr "No puede encontrar el esquema para esta placa."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1497
|
||||
#: pcbnew/pcb_edit_frame.cpp:1490
|
||||
msgid ""
|
||||
"Cannot update the PCB because PCB editor is opened in stand-alone mode. In "
|
||||
"order to create or update PCBs from schematics, you must launch the KiCad "
|
||||
|
|
@ -31817,11 +31814,11 @@ msgstr ""
|
|||
"modo independiente. Para crear o actualizar placas desde el esquema es "
|
||||
"necesario abrir al administrador de proyectos de KiCad y crear un proyecto."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1519
|
||||
#: pcbnew/pcb_edit_frame.cpp:1512
|
||||
msgid "Eeschema netlist"
|
||||
msgstr "Lista de redes de Eeschema"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1530
|
||||
#: pcbnew/pcb_edit_frame.cpp:1523
|
||||
msgid ""
|
||||
"Received an error while reading netlist. Please report this issue to the "
|
||||
"KiCad team using the menu Help->Report Bug."
|
||||
|
|
@ -31829,31 +31826,31 @@ msgstr ""
|
|||
"Se recibió un error al leer la lista de redes. Por favor, informe de este "
|
||||
"problema al equipo de KiCad utilizando el menú Ayuda->Informar de un error."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1557
|
||||
#: pcbnew/pcb_edit_frame.cpp:1550
|
||||
#, c-format
|
||||
msgid "Schematic file '%s' not found."
|
||||
msgstr "No se ha encontrado el archivo de esquema '%s'."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1587
|
||||
#: pcbnew/pcb_edit_frame.cpp:1580
|
||||
msgid "Eeschema failed to load."
|
||||
msgstr "Fallo al cargar Eeschema."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1738
|
||||
#: pcbnew/pcb_edit_frame.cpp:1731
|
||||
msgid "Edit design rules"
|
||||
msgstr "Editar reglas de diseño"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1750
|
||||
#: pcbnew/pcb_edit_frame.cpp:1743
|
||||
msgid "Could not compile custom design rules."
|
||||
msgstr "No se pueden compilar las reglas de diseño personalizadas."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1785
|
||||
#: pcbnew/pcb_edit_frame.cpp:1778
|
||||
msgid "Export Hyperlynx Layout"
|
||||
msgstr "Exportar diseño Hyperlynx"
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:95 pcbnew/pcb_expr_evaluator.cpp:264
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:330 pcbnew/pcb_expr_evaluator.cpp:396
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:614 pcbnew/pcb_expr_evaluator.cpp:716
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:829
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:824
|
||||
#, c-format
|
||||
msgid "Missing argument to '%s'"
|
||||
msgstr "Argumento faltante a '%s'"
|
||||
|
|
@ -31875,7 +31872,7 @@ msgstr "La huella no tiene un patio frontal."
|
|||
msgid "Footprint has no back courtyard."
|
||||
msgstr "La huella no tiene un patio trasero."
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1152
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1153
|
||||
msgid "must be mm, in, or mil"
|
||||
msgstr "deber ser mm, in, o mil"
|
||||
|
||||
|
|
@ -37145,6 +37142,10 @@ msgstr "Esquema de KiCad"
|
|||
msgid "KiCad Printed Circuit Board"
|
||||
msgstr "Placa de circuito impreso de KiCad"
|
||||
|
||||
#, fuzzy
|
||||
#~ msgid "Net CodewxT( "
|
||||
#~ msgstr "Código red"
|
||||
|
||||
#~ msgid "Save changes to schematic before closing?"
|
||||
#~ msgstr "¿Guardar los cambios del esquema antes de cerrar?"
|
||||
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@ msgid ""
|
|||
msgstr ""
|
||||
"Project-Id-Version: KiCad Spanish Translation\n"
|
||||
"Report-Msgid-Bugs-To: \n"
|
||||
"POT-Creation-Date: 2022-02-14 09:20-0800\n"
|
||||
"POT-Creation-Date: 2022-02-16 17:22-0800\n"
|
||||
"PO-Revision-Date: 2022-02-16 13:03+0000\n"
|
||||
"Last-Translator: Ulices <ulicesah@gmail.com>\n"
|
||||
"Language-Team: Spanish (Mexico) <https://hosted.weblate.org/projects/kicad/"
|
||||
|
|
@ -4608,12 +4608,12 @@ msgstr "Alias: "
|
|||
|
||||
#: common/filename_resolver.cpp:468
|
||||
#, fuzzy
|
||||
msgid "This path:wxT( "
|
||||
msgid "This path:"
|
||||
msgstr "Esta ruta:"
|
||||
|
||||
#: common/filename_resolver.cpp:471
|
||||
#, fuzzy
|
||||
msgid "Existing path:wxT( "
|
||||
msgid "Existing path:"
|
||||
msgstr "Ruta existente:"
|
||||
|
||||
#: common/filename_resolver.cpp:473
|
||||
|
|
@ -13431,9 +13431,9 @@ msgstr "Clase de red asignada"
|
|||
msgid "Connection Name"
|
||||
msgstr "Nombre de conexión"
|
||||
|
||||
#: eeschema/sch_connection.cpp:415
|
||||
#, fuzzy
|
||||
msgid "Net CodewxT( "
|
||||
#: eeschema/sch_connection.cpp:415 pcbnew/dialogs/dialog_net_inspector.cpp:76
|
||||
#: pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr "Código red"
|
||||
|
||||
#: eeschema/sch_connection.cpp:420 eeschema/sch_connection.cpp:433
|
||||
|
|
@ -19222,8 +19222,8 @@ msgid "Application failed to load:\n"
|
|||
msgstr "Fallo al cargar la aplicación:\n"
|
||||
|
||||
#: kicad/tools/kicad_manager_control.cpp:670
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1558
|
||||
#: pcbnew/pcb_edit_frame.cpp:1588
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1551
|
||||
#: pcbnew/pcb_edit_frame.cpp:1581
|
||||
msgid "KiCad Error"
|
||||
msgstr "Error de KiCad"
|
||||
|
||||
|
|
@ -22282,7 +22282,7 @@ msgstr "Tamaños predefinidos"
|
|||
|
||||
#: pcbnew/dialogs/dialog_board_setup.cpp:108
|
||||
#: pcbnew/dialogs/dialog_constraints_reporter.cpp:54
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1744
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1737
|
||||
msgid "Custom Rules"
|
||||
msgstr "Reglas personalizadas"
|
||||
|
||||
|
|
@ -25357,10 +25357,6 @@ msgstr "Utilizar coordenadas polares"
|
|||
msgid "Move Item"
|
||||
msgstr "Mover elemento"
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:76 pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr "Código red"
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:77 pcbnew/netinfo_item.cpp:74
|
||||
msgid "Net Name"
|
||||
msgstr "Nombre red"
|
||||
|
|
@ -28848,6 +28844,7 @@ msgid "Check rule syntax"
|
|||
msgstr "Verificar reglas de sintaxis"
|
||||
|
||||
#: pcbnew/dialogs/panel_setup_rules_help_md.h:2
|
||||
#, fuzzy
|
||||
msgid ""
|
||||
"### Top-level Clauses\n"
|
||||
"\n"
|
||||
|
|
@ -28973,8 +28970,8 @@ msgid ""
|
|||
" A.inDiffPair('<net_name>')\n"
|
||||
"True if `A` has net that is part of the specified differential pair.\n"
|
||||
"`<net_name>` is the base name of the differential pair. For example, "
|
||||
"`inDiffPair('CLK')`\n"
|
||||
"matches items in the `CLK_P` and `CLK_N` nets.\n"
|
||||
"`inDiffPair('/CLK')`\n"
|
||||
"matches items in the `/CLK_P` and `/CLK_N` nets.\n"
|
||||
"<br><br>\n"
|
||||
"\n"
|
||||
" AB.isCoupledDiffPair()\n"
|
||||
|
|
@ -29014,20 +29011,20 @@ msgid ""
|
|||
" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Distance between Vias of Different Nets\" \n"
|
||||
" (rule \"Distance between Vias of Different Nets\"\n"
|
||||
" (constraint hole_to_hole (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
" (rule \"Clearance between Pads of Different Nets\" \n"
|
||||
" (rule \"Clearance between Pads of Different Nets\"\n"
|
||||
" (constraint clearance (min 3.0mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Via Hole to Track Clearance\" \n"
|
||||
" (rule \"Via Hole to Track Clearance\"\n"
|
||||
" (constraint hole_clearance (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Track'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Pad to Track Clearance\" \n"
|
||||
" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n"
|
||||
"\n"
|
||||
" (rule \"Pad to Track Clearance\"\n"
|
||||
" (constraint clearance (min 0.2mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -29037,11 +29034,11 @@ msgid ""
|
|||
" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\" \n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\"\n"
|
||||
" (constraint hole_size (max 6.3mm))\n"
|
||||
" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Max Drill Hole Size PTH\" \n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size PTH\"\n"
|
||||
" (constraint hole_size (max 6.35mm))\n"
|
||||
" (condition \"A.Pad_Type == 'Through-hole'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -29049,7 +29046,7 @@ msgid ""
|
|||
" # Specify an optimal gap for a particular diff-pair\n"
|
||||
" (rule \"dp clock gap\"\n"
|
||||
" (constraint diff_pair_gap (opt \"0.8mm\"))\n"
|
||||
" (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n"
|
||||
" (condition \"A.inDiffPair('/CLK')\"))\n"
|
||||
"\n"
|
||||
" # Specify a larger clearance around any diff-pair\n"
|
||||
" (rule \"dp clearance\"\n"
|
||||
|
|
@ -31800,11 +31797,11 @@ msgstr "El archivo de placa es de solo lectura."
|
|||
msgid "PCB file changes are unsaved"
|
||||
msgstr "Los cambios a la placa no están guardados"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1473
|
||||
#: pcbnew/pcb_edit_frame.cpp:1466
|
||||
msgid "The schematic for this board cannot be found."
|
||||
msgstr "No puede encontrar el esquema para esta placa."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1497
|
||||
#: pcbnew/pcb_edit_frame.cpp:1490
|
||||
msgid ""
|
||||
"Cannot update the PCB because PCB editor is opened in stand-alone mode. In "
|
||||
"order to create or update PCBs from schematics, you must launch the KiCad "
|
||||
|
|
@ -31814,11 +31811,11 @@ msgstr ""
|
|||
"modo independiente. Para crear o actualizar placas desde el esquema es "
|
||||
"necesario abrir al administrador de proyectos de KiCad y crear un proyecto."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1519
|
||||
#: pcbnew/pcb_edit_frame.cpp:1512
|
||||
msgid "Eeschema netlist"
|
||||
msgstr "Lista de redes de Eeschema"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1530
|
||||
#: pcbnew/pcb_edit_frame.cpp:1523
|
||||
msgid ""
|
||||
"Received an error while reading netlist. Please report this issue to the "
|
||||
"KiCad team using the menu Help->Report Bug."
|
||||
|
|
@ -31827,31 +31824,31 @@ msgstr ""
|
|||
"este problema al equipo de KiCad utilizando el menú Ayuda->Informar de un "
|
||||
"error."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1557
|
||||
#: pcbnew/pcb_edit_frame.cpp:1550
|
||||
#, c-format
|
||||
msgid "Schematic file '%s' not found."
|
||||
msgstr "No se ha encontrado el archivo de esquema '%s'."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1587
|
||||
#: pcbnew/pcb_edit_frame.cpp:1580
|
||||
msgid "Eeschema failed to load."
|
||||
msgstr "Fallo al cargar Eeschema."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1738
|
||||
#: pcbnew/pcb_edit_frame.cpp:1731
|
||||
msgid "Edit design rules"
|
||||
msgstr "Editar reglas de diseño"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1750
|
||||
#: pcbnew/pcb_edit_frame.cpp:1743
|
||||
msgid "Could not compile custom design rules."
|
||||
msgstr "No se pueden compilar las reglas de diseño personalizadas."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1785
|
||||
#: pcbnew/pcb_edit_frame.cpp:1778
|
||||
msgid "Export Hyperlynx Layout"
|
||||
msgstr "Exportar diseño Hyperlynx"
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:95 pcbnew/pcb_expr_evaluator.cpp:264
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:330 pcbnew/pcb_expr_evaluator.cpp:396
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:614 pcbnew/pcb_expr_evaluator.cpp:716
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:829
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:824
|
||||
#, c-format
|
||||
msgid "Missing argument to '%s'"
|
||||
msgstr "Argumento faltante a '%s'"
|
||||
|
|
@ -31873,7 +31870,7 @@ msgstr "La huella no tiene un patio frontal."
|
|||
msgid "Footprint has no back courtyard."
|
||||
msgstr "La huella no tiene un patio trasero."
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1152
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1153
|
||||
msgid "must be mm, in, or mil"
|
||||
msgstr "deber ser mm, in, o mil"
|
||||
|
||||
|
|
@ -37145,6 +37142,10 @@ msgstr "Esquema de KiCad"
|
|||
msgid "KiCad Printed Circuit Board"
|
||||
msgstr "Placa de circuito impreso de KiCad"
|
||||
|
||||
#, fuzzy
|
||||
#~ msgid "Net CodewxT( "
|
||||
#~ msgstr "Código red"
|
||||
|
||||
#~ msgid "Save changes to schematic before closing?"
|
||||
#~ msgstr "¿Guardar los cambios del esquema antes de cerrar?"
|
||||
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@ msgid ""
|
|||
msgstr ""
|
||||
"Project-Id-Version: KiCad\n"
|
||||
"Report-Msgid-Bugs-To: \n"
|
||||
"POT-Creation-Date: 2022-02-14 09:20-0800\n"
|
||||
"POT-Creation-Date: 2022-02-16 17:22-0800\n"
|
||||
"PO-Revision-Date: 2022-02-16 13:03+0000\n"
|
||||
"Last-Translator: Henrik Kauhanen <henrik@kauhanen.se>\n"
|
||||
"Language-Team: Finnish <https://hosted.weblate.org/projects/kicad/v6/fi/>\n"
|
||||
|
|
@ -4625,12 +4625,12 @@ msgstr "Alias: "
|
|||
|
||||
#: common/filename_resolver.cpp:468
|
||||
#, fuzzy
|
||||
msgid "This path:wxT( "
|
||||
msgid "This path:"
|
||||
msgstr "Tämä polku:"
|
||||
|
||||
#: common/filename_resolver.cpp:471
|
||||
#, fuzzy
|
||||
msgid "Existing path:wxT( "
|
||||
msgid "Existing path:"
|
||||
msgstr "Nykyinen polku:"
|
||||
|
||||
#: common/filename_resolver.cpp:473
|
||||
|
|
@ -8535,8 +8535,8 @@ msgstr "Vaihda vakavuudeksi Virhe kaikkien ”%s” rikkomusten osalta"
|
|||
#, fuzzy
|
||||
msgid "Violation severities can also be edited in the Board Setup... dialog"
|
||||
msgstr ""
|
||||
"Rikkomusten vakavuutta voidaan muokata myös Piirilevyasetukset ... "
|
||||
"-valintaikkunassa"
|
||||
"Rikkomusten vakavuutta voidaan muokata myös Piirilevyasetukset ... -"
|
||||
"valintaikkunassa"
|
||||
|
||||
#: eeschema/dialogs/dialog_erc.cpp:533 pcbnew/dialogs/dialog_drc.cpp:476
|
||||
#, c-format
|
||||
|
|
@ -13509,9 +13509,9 @@ msgstr "Määritetty verkkoluokka"
|
|||
msgid "Connection Name"
|
||||
msgstr "Yhteyden nimi"
|
||||
|
||||
#: eeschema/sch_connection.cpp:415
|
||||
#, fuzzy
|
||||
msgid "Net CodewxT( "
|
||||
#: eeschema/sch_connection.cpp:415 pcbnew/dialogs/dialog_net_inspector.cpp:76
|
||||
#: pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr "kytkentäverkon koodi"
|
||||
|
||||
#: eeschema/sch_connection.cpp:420 eeschema/sch_connection.cpp:433
|
||||
|
|
@ -19356,8 +19356,8 @@ msgid "Application failed to load:\n"
|
|||
msgstr "Sovelluksen lataaminen epäonnistui:\n"
|
||||
|
||||
#: kicad/tools/kicad_manager_control.cpp:670
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1558
|
||||
#: pcbnew/pcb_edit_frame.cpp:1588
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1551
|
||||
#: pcbnew/pcb_edit_frame.cpp:1581
|
||||
msgid "KiCad Error"
|
||||
msgstr "KiCad-virhe"
|
||||
|
||||
|
|
@ -22485,7 +22485,7 @@ msgstr "Ennalta valitut koot"
|
|||
|
||||
#: pcbnew/dialogs/dialog_board_setup.cpp:108
|
||||
#: pcbnew/dialogs/dialog_constraints_reporter.cpp:54
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1744
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1737
|
||||
#, fuzzy
|
||||
msgid "Custom Rules"
|
||||
msgstr "Mukautettu tasosarja"
|
||||
|
|
@ -25565,10 +25565,6 @@ msgstr "Käytä napakoordinaatteja"
|
|||
msgid "Move Item"
|
||||
msgstr "Siirrä kohde"
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:76 pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr "kytkentäverkon koodi"
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:77 pcbnew/netinfo_item.cpp:74
|
||||
msgid "Net Name"
|
||||
msgstr "Kytkentäverkon nimi"
|
||||
|
|
@ -29070,6 +29066,7 @@ msgid "Check rule syntax"
|
|||
msgstr "Tarkista säännön syntaksit"
|
||||
|
||||
#: pcbnew/dialogs/panel_setup_rules_help_md.h:2
|
||||
#, fuzzy
|
||||
msgid ""
|
||||
"### Top-level Clauses\n"
|
||||
"\n"
|
||||
|
|
@ -29195,8 +29192,8 @@ msgid ""
|
|||
" A.inDiffPair('<net_name>')\n"
|
||||
"True if `A` has net that is part of the specified differential pair.\n"
|
||||
"`<net_name>` is the base name of the differential pair. For example, "
|
||||
"`inDiffPair('CLK')`\n"
|
||||
"matches items in the `CLK_P` and `CLK_N` nets.\n"
|
||||
"`inDiffPair('/CLK')`\n"
|
||||
"matches items in the `/CLK_P` and `/CLK_N` nets.\n"
|
||||
"<br><br>\n"
|
||||
"\n"
|
||||
" AB.isCoupledDiffPair()\n"
|
||||
|
|
@ -29236,20 +29233,20 @@ msgid ""
|
|||
" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Distance between Vias of Different Nets\" \n"
|
||||
" (rule \"Distance between Vias of Different Nets\"\n"
|
||||
" (constraint hole_to_hole (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
" (rule \"Clearance between Pads of Different Nets\" \n"
|
||||
" (rule \"Clearance between Pads of Different Nets\"\n"
|
||||
" (constraint clearance (min 3.0mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Via Hole to Track Clearance\" \n"
|
||||
" (rule \"Via Hole to Track Clearance\"\n"
|
||||
" (constraint hole_clearance (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Track'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Pad to Track Clearance\" \n"
|
||||
" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n"
|
||||
"\n"
|
||||
" (rule \"Pad to Track Clearance\"\n"
|
||||
" (constraint clearance (min 0.2mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -29259,11 +29256,11 @@ msgid ""
|
|||
" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\" \n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\"\n"
|
||||
" (constraint hole_size (max 6.3mm))\n"
|
||||
" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Max Drill Hole Size PTH\" \n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size PTH\"\n"
|
||||
" (constraint hole_size (max 6.35mm))\n"
|
||||
" (condition \"A.Pad_Type == 'Through-hole'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -29271,7 +29268,7 @@ msgid ""
|
|||
" # Specify an optimal gap for a particular diff-pair\n"
|
||||
" (rule \"dp clock gap\"\n"
|
||||
" (constraint diff_pair_gap (opt \"0.8mm\"))\n"
|
||||
" (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n"
|
||||
" (condition \"A.inDiffPair('/CLK')\"))\n"
|
||||
"\n"
|
||||
" # Specify a larger clearance around any diff-pair\n"
|
||||
" (rule \"dp clearance\"\n"
|
||||
|
|
@ -32020,11 +32017,11 @@ msgstr "Piirilevytiedostoon ei ole kirjoitusoikeuksia."
|
|||
msgid "PCB file changes are unsaved"
|
||||
msgstr "PCB-tiedostomuutoksia ei ole tallennettu"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1473
|
||||
#: pcbnew/pcb_edit_frame.cpp:1466
|
||||
msgid "The schematic for this board cannot be found."
|
||||
msgstr "Tämän kortin kaaviota ei löydy."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1497
|
||||
#: pcbnew/pcb_edit_frame.cpp:1490
|
||||
msgid ""
|
||||
"Cannot update the PCB because PCB editor is opened in stand-alone mode. In "
|
||||
"order to create or update PCBs from schematics, you must launch the KiCad "
|
||||
|
|
@ -32034,11 +32031,11 @@ msgstr ""
|
|||
"voit luoda tai päivittää piirilevyjä kytkentäkaavioista, sinun on "
|
||||
"käynnistettävä KiCad-ohjelma ja luotava projekti."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1519
|
||||
#: pcbnew/pcb_edit_frame.cpp:1512
|
||||
msgid "Eeschema netlist"
|
||||
msgstr "Eeschema-verkkolista"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1530
|
||||
#: pcbnew/pcb_edit_frame.cpp:1523
|
||||
msgid ""
|
||||
"Received an error while reading netlist. Please report this issue to the "
|
||||
"KiCad team using the menu Help->Report Bug."
|
||||
|
|
@ -32046,31 +32043,31 @@ msgstr ""
|
|||
"Virhe luettaessa netlist:iä. Raportoisitko tästä ongelmasta KiCad-tiimille "
|
||||
"käyttäen Apua->Raportoi virhe -valikkoa."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1557
|
||||
#: pcbnew/pcb_edit_frame.cpp:1550
|
||||
#, fuzzy, c-format
|
||||
msgid "Schematic file '%s' not found."
|
||||
msgstr "Kaaviotiedostoa \"%s\" ei löydy."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1587
|
||||
#: pcbnew/pcb_edit_frame.cpp:1580
|
||||
msgid "Eeschema failed to load."
|
||||
msgstr "Eescheman lataaminen epäonnistui."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1738
|
||||
#: pcbnew/pcb_edit_frame.cpp:1731
|
||||
msgid "Edit design rules"
|
||||
msgstr "Muokkaa suunnittelusääntöjä"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1750
|
||||
#: pcbnew/pcb_edit_frame.cpp:1743
|
||||
msgid "Could not compile custom design rules."
|
||||
msgstr "Ei voitu kääntää mukautettuja suunnittelusääntöjä."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1785
|
||||
#: pcbnew/pcb_edit_frame.cpp:1778
|
||||
msgid "Export Hyperlynx Layout"
|
||||
msgstr "Vie Hyperlynx-asettelu"
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:95 pcbnew/pcb_expr_evaluator.cpp:264
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:330 pcbnew/pcb_expr_evaluator.cpp:396
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:614 pcbnew/pcb_expr_evaluator.cpp:716
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:829
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:824
|
||||
#, c-format
|
||||
msgid "Missing argument to '%s'"
|
||||
msgstr "Puuttuva argumentti \"%s\""
|
||||
|
|
@ -32092,7 +32089,7 @@ msgstr "Jalanjäljellä ei ole etupihaa."
|
|||
msgid "Footprint has no back courtyard."
|
||||
msgstr "Jalanjäljellä ei ole takapihaa."
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1152
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1153
|
||||
msgid "must be mm, in, or mil"
|
||||
msgstr "on oltava mm, tuumaa tai mil"
|
||||
|
||||
|
|
@ -34006,7 +34003,7 @@ msgid "Width %s, gap %s, via gap %s"
|
|||
msgstr "Leveys %s, aukko %s, aukon kautta %s"
|
||||
|
||||
#: pcbnew/router/router_tool.cpp:521
|
||||
#, c-format, fuzzy
|
||||
#, fuzzy, c-format
|
||||
msgid ""
|
||||
"Event file: %s\n"
|
||||
"Board dump: %s"
|
||||
|
|
@ -37416,6 +37413,10 @@ msgstr "KiCad-kytkentäkaavio"
|
|||
msgid "KiCad Printed Circuit Board"
|
||||
msgstr "KiCad-piirilevy"
|
||||
|
||||
#, fuzzy
|
||||
#~ msgid "Net CodewxT( "
|
||||
#~ msgstr "kytkentäverkon koodi"
|
||||
|
||||
#~ msgid "Save changes to schematic before closing?"
|
||||
#~ msgstr "Tallennetaanko kaavamuutokset ennen sulkemista?"
|
||||
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@ msgid ""
|
|||
msgstr ""
|
||||
"Project-Id-Version: kicad\n"
|
||||
"Report-Msgid-Bugs-To: \n"
|
||||
"POT-Creation-Date: 2022-02-15 10:16+0100\n"
|
||||
"POT-Creation-Date: 2022-02-16 17:22-0800\n"
|
||||
"PO-Revision-Date: 2022-02-15 10:10+0100\n"
|
||||
"Last-Translator: \n"
|
||||
"Language-Team: jp-charras\n"
|
||||
|
|
@ -4627,12 +4627,12 @@ msgstr "Alias: "
|
|||
|
||||
#: common/filename_resolver.cpp:468
|
||||
#, fuzzy
|
||||
msgid "This path:wxT( "
|
||||
msgid "This path:"
|
||||
msgstr "Ce chemin:"
|
||||
|
||||
#: common/filename_resolver.cpp:471
|
||||
#, fuzzy
|
||||
msgid "Existing path:wxT( "
|
||||
msgid "Existing path:"
|
||||
msgstr "Chemin existant:"
|
||||
|
||||
#: common/filename_resolver.cpp:473
|
||||
|
|
@ -13484,9 +13484,9 @@ msgstr "NetClasses Assignées"
|
|||
msgid "Connection Name"
|
||||
msgstr "Nom de Connexion"
|
||||
|
||||
#: eeschema/sch_connection.cpp:415
|
||||
#, fuzzy
|
||||
msgid "Net CodewxT( "
|
||||
#: eeschema/sch_connection.cpp:415 pcbnew/dialogs/dialog_net_inspector.cpp:76
|
||||
#: pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr "Net Code"
|
||||
|
||||
#: eeschema/sch_connection.cpp:420 eeschema/sch_connection.cpp:433
|
||||
|
|
@ -25415,10 +25415,6 @@ msgstr "Utiliser coordonnées polaires"
|
|||
msgid "Move Item"
|
||||
msgstr "Déplacer Élément"
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:76 pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr "Net Code"
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:77 pcbnew/netinfo_item.cpp:74
|
||||
msgid "Net Name"
|
||||
msgstr "Nom Équipot"
|
||||
|
|
@ -31904,7 +31900,7 @@ msgstr "Exporter au Format Hyperlynx"
|
|||
#: pcbnew/pcb_expr_evaluator.cpp:95 pcbnew/pcb_expr_evaluator.cpp:264
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:330 pcbnew/pcb_expr_evaluator.cpp:396
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:614 pcbnew/pcb_expr_evaluator.cpp:716
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:829
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:824
|
||||
#, c-format
|
||||
msgid "Missing argument to '%s'"
|
||||
msgstr "Argument manquant à '%s'"
|
||||
|
|
@ -31926,7 +31922,7 @@ msgstr "L'empreinte n’a pas zone d'occupation sur le dessus."
|
|||
msgid "Footprint has no back courtyard."
|
||||
msgstr "L'empreinte n’a pas zone d'occupation sur le dessous."
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1152
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1153
|
||||
msgid "must be mm, in, or mil"
|
||||
msgstr "doit être mm, in, ou mil"
|
||||
|
||||
|
|
@ -37054,11 +37050,6 @@ msgstr "Exécution de remplissage des polygones..."
|
|||
msgid "[INFO] load failed: input line too long\n"
|
||||
msgstr "[INFO] chargement échouée: ligne d’entrée trop longue\n"
|
||||
|
||||
#: resources/linux/launchers/org.kicad.bitmap2component.desktop.in:5
|
||||
#: resources/linux/launchers/org.kicad.bitmap2component.desktop.in:13
|
||||
msgid "bitmap2component"
|
||||
msgstr "bitmap2component"
|
||||
|
||||
#: resources/linux/launchers/org.kicad.bitmap2component.desktop.in:10
|
||||
msgid "KiCad Image Converter"
|
||||
msgstr "Convertisseur d'Image KiCad"
|
||||
|
|
@ -37069,10 +37060,9 @@ msgstr ""
|
|||
"Créer un composant à partir d’une image bitmap pour une utilisation avec "
|
||||
"KiCad"
|
||||
|
||||
#: resources/linux/launchers/org.kicad.eeschema.desktop.in:5
|
||||
#: resources/linux/launchers/org.kicad.eeschema.desktop.in:14
|
||||
msgid "eeschema"
|
||||
msgstr "eeschema"
|
||||
#: resources/linux/launchers/org.kicad.bitmap2component.desktop.in:13
|
||||
msgid "bitmap2component"
|
||||
msgstr "bitmap2component"
|
||||
|
||||
#: resources/linux/launchers/org.kicad.eeschema.desktop.in:11
|
||||
msgid "KiCad Schematic Editor (Standalone)"
|
||||
|
|
@ -37086,10 +37076,9 @@ msgstr "Outil de Capture Schématique"
|
|||
msgid "Standalone schematic editor for KiCad schematics"
|
||||
msgstr "Editeur de schématique indépendant pour les schémas KiCad"
|
||||
|
||||
#: resources/linux/launchers/org.kicad.gerbview.desktop.in:5
|
||||
#: resources/linux/launchers/org.kicad.gerbview.desktop.in:14
|
||||
msgid "gerbview"
|
||||
msgstr "gerbview"
|
||||
#: resources/linux/launchers/org.kicad.eeschema.desktop.in:14
|
||||
msgid "eeschema"
|
||||
msgstr "eeschema"
|
||||
|
||||
#: resources/linux/launchers/org.kicad.gerbview.desktop.in:12
|
||||
msgid "Gerber File Viewer"
|
||||
|
|
@ -37099,9 +37088,9 @@ msgstr "Visionneuse de fichiers Gerber"
|
|||
msgid "View Gerber files"
|
||||
msgstr "Visualiser fichiers Gerber"
|
||||
|
||||
#: resources/linux/launchers/org.kicad.kicad.desktop.in:5
|
||||
msgid "kicad"
|
||||
msgstr "kicad"
|
||||
#: resources/linux/launchers/org.kicad.gerbview.desktop.in:14
|
||||
msgid "gerbview"
|
||||
msgstr "gerbview"
|
||||
|
||||
#: resources/linux/launchers/org.kicad.kicad.desktop.in:11
|
||||
#: resources/linux/metainfo/org.kicad.kicad.metainfo.xml.in:6
|
||||
|
|
@ -37116,10 +37105,6 @@ msgstr "Suite CAO Electronique"
|
|||
msgid "Suite of tools for schematic design and circuit board layout"
|
||||
msgstr "Suite d’outils pour la conception schématique et des circuits imprimés"
|
||||
|
||||
#: resources/linux/launchers/org.kicad.pcbcalculator.desktop.in:5
|
||||
msgid "pcbcalculator"
|
||||
msgstr "pcbcalculator"
|
||||
|
||||
#: resources/linux/launchers/org.kicad.pcbcalculator.desktop.in:10
|
||||
msgid "KiCad PCB Calculator"
|
||||
msgstr "Calculateur pour PCB KiCad"
|
||||
|
|
@ -37128,11 +37113,6 @@ msgstr "Calculateur pour PCB KiCad"
|
|||
msgid "Calculator for various electronics-related computations"
|
||||
msgstr "Calculatrice pour divers calculs liés à l’électronique"
|
||||
|
||||
#: resources/linux/launchers/org.kicad.pcbnew.desktop.in:5
|
||||
#: resources/linux/launchers/org.kicad.pcbnew.desktop.in:14
|
||||
msgid "pcbnew"
|
||||
msgstr "pcbnew"
|
||||
|
||||
#: resources/linux/launchers/org.kicad.pcbnew.desktop.in:11
|
||||
msgid "KiCad PCB Editor (Standalone)"
|
||||
msgstr "Editeur de PCB KiCad (indépendant)"
|
||||
|
|
@ -37145,6 +37125,10 @@ msgstr "Éditeur de circuit imprimé"
|
|||
msgid "Standalone circuit board editor for KiCad boards"
|
||||
msgstr "Éditeur indépendant de circuits imprimés pour les C.I. KiCad"
|
||||
|
||||
#: resources/linux/launchers/org.kicad.pcbnew.desktop.in:14
|
||||
msgid "pcbnew"
|
||||
msgstr "pcbnew"
|
||||
|
||||
#: resources/linux/metainfo/org.kicad.kicad.metainfo.xml.in:13
|
||||
msgid "An EDA suite for schematic and circuit board design"
|
||||
msgstr "Suite d’outils pour la conception schématique et des circuits imprimés"
|
||||
|
|
@ -37197,3 +37181,13 @@ msgstr "Schématique KiCad"
|
|||
#: resources/linux/mime/kicad-kicad.xml.in:27
|
||||
msgid "KiCad Printed Circuit Board"
|
||||
msgstr "Fichier Circuit Imprimé KiCad"
|
||||
|
||||
#, fuzzy
|
||||
#~ msgid "Net CodewxT( "
|
||||
#~ msgstr "Net Code"
|
||||
|
||||
#~ msgid "kicad"
|
||||
#~ msgstr "kicad"
|
||||
|
||||
#~ msgid "pcbcalculator"
|
||||
#~ msgstr "pcbcalculator"
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@ msgid ""
|
|||
msgstr ""
|
||||
"Project-Id-Version: KiCad\n"
|
||||
"Report-Msgid-Bugs-To: \n"
|
||||
"POT-Creation-Date: 2022-02-14 09:20-0800\n"
|
||||
"POT-Creation-Date: 2022-02-16 17:22-0800\n"
|
||||
"PO-Revision-Date: 2019-06-03 15:48+0200\n"
|
||||
"Last-Translator: szlldm\n"
|
||||
"Language-Team: szlldm\n"
|
||||
|
|
@ -4794,12 +4794,12 @@ msgstr "Megnevezés: "
|
|||
|
||||
#: common/filename_resolver.cpp:468
|
||||
#, fuzzy
|
||||
msgid "This path:wxT( "
|
||||
msgid "This path:"
|
||||
msgstr "Ez az útvonal: "
|
||||
|
||||
#: common/filename_resolver.cpp:471
|
||||
#, fuzzy
|
||||
msgid "Existing path:wxT( "
|
||||
msgid "Existing path:"
|
||||
msgstr "Létező útvonal: "
|
||||
|
||||
#: common/filename_resolver.cpp:473
|
||||
|
|
@ -13795,9 +13795,9 @@ msgstr "Vezetékosztály hozzárendelés"
|
|||
msgid "Connection Name"
|
||||
msgstr "Csatlakozás név"
|
||||
|
||||
#: eeschema/sch_connection.cpp:415
|
||||
#, fuzzy
|
||||
msgid "Net CodewxT( "
|
||||
#: eeschema/sch_connection.cpp:415 pcbnew/dialogs/dialog_net_inspector.cpp:76
|
||||
#: pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr "Vezeték kód"
|
||||
|
||||
#: eeschema/sch_connection.cpp:420 eeschema/sch_connection.cpp:433
|
||||
|
|
@ -19671,8 +19671,8 @@ msgid "Application failed to load:\n"
|
|||
msgstr "A Nyáktervezőnek nem sikerült betöltenie:\n"
|
||||
|
||||
#: kicad/tools/kicad_manager_control.cpp:670
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1558
|
||||
#: pcbnew/pcb_edit_frame.cpp:1588
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1551
|
||||
#: pcbnew/pcb_edit_frame.cpp:1581
|
||||
msgid "KiCad Error"
|
||||
msgstr "KiCad Hiba"
|
||||
|
||||
|
|
@ -22792,7 +22792,7 @@ msgstr "Előre definiált méretek:"
|
|||
|
||||
#: pcbnew/dialogs/dialog_board_setup.cpp:108
|
||||
#: pcbnew/dialogs/dialog_constraints_reporter.cpp:54
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1744
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1737
|
||||
#, fuzzy
|
||||
msgid "Custom Rules"
|
||||
msgstr "Egyedi rétegfelépítés"
|
||||
|
|
@ -26032,10 +26032,6 @@ msgstr "Poláris koordináta-rendszer használata"
|
|||
msgid "Move Item"
|
||||
msgstr "Elem mozgatása"
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:76 pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr "Vezeték kód"
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:77 pcbnew/netinfo_item.cpp:74
|
||||
msgid "Net Name"
|
||||
msgstr "Vezetéknév"
|
||||
|
|
@ -29725,8 +29721,8 @@ msgid ""
|
|||
" A.inDiffPair('<net_name>')\n"
|
||||
"True if `A` has net that is part of the specified differential pair.\n"
|
||||
"`<net_name>` is the base name of the differential pair. For example, "
|
||||
"`inDiffPair('CLK')`\n"
|
||||
"matches items in the `CLK_P` and `CLK_N` nets.\n"
|
||||
"`inDiffPair('/CLK')`\n"
|
||||
"matches items in the `/CLK_P` and `/CLK_N` nets.\n"
|
||||
"<br><br>\n"
|
||||
"\n"
|
||||
" AB.isCoupledDiffPair()\n"
|
||||
|
|
@ -29766,20 +29762,20 @@ msgid ""
|
|||
" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Distance between Vias of Different Nets\" \n"
|
||||
" (rule \"Distance between Vias of Different Nets\"\n"
|
||||
" (constraint hole_to_hole (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
" (rule \"Clearance between Pads of Different Nets\" \n"
|
||||
" (rule \"Clearance between Pads of Different Nets\"\n"
|
||||
" (constraint clearance (min 3.0mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Via Hole to Track Clearance\" \n"
|
||||
" (rule \"Via Hole to Track Clearance\"\n"
|
||||
" (constraint hole_clearance (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Track'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Pad to Track Clearance\" \n"
|
||||
" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n"
|
||||
"\n"
|
||||
" (rule \"Pad to Track Clearance\"\n"
|
||||
" (constraint clearance (min 0.2mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -29789,11 +29785,11 @@ msgid ""
|
|||
" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\" \n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\"\n"
|
||||
" (constraint hole_size (max 6.3mm))\n"
|
||||
" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Max Drill Hole Size PTH\" \n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size PTH\"\n"
|
||||
" (constraint hole_size (max 6.35mm))\n"
|
||||
" (condition \"A.Pad_Type == 'Through-hole'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -29801,7 +29797,7 @@ msgid ""
|
|||
" # Specify an optimal gap for a particular diff-pair\n"
|
||||
" (rule \"dp clock gap\"\n"
|
||||
" (constraint diff_pair_gap (opt \"0.8mm\"))\n"
|
||||
" (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n"
|
||||
" (condition \"A.inDiffPair('/CLK')\"))\n"
|
||||
"\n"
|
||||
" # Specify a larger clearance around any diff-pair\n"
|
||||
" (rule \"dp clearance\"\n"
|
||||
|
|
@ -32498,12 +32494,12 @@ msgstr "Aktuális panelméret"
|
|||
msgid "PCB file changes are unsaved"
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1473
|
||||
#: pcbnew/pcb_edit_frame.cpp:1466
|
||||
#, fuzzy
|
||||
msgid "The schematic for this board cannot be found."
|
||||
msgstr "Ez a művelet nem vonható vissza."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1497
|
||||
#: pcbnew/pcb_edit_frame.cpp:1490
|
||||
#, fuzzy
|
||||
msgid ""
|
||||
"Cannot update the PCB because PCB editor is opened in stand-alone mode. In "
|
||||
|
|
@ -32514,44 +32510,44 @@ msgstr ""
|
|||
"kívánt munkafolyamatok használatához mindig a KiCad keretrendszerből indítsa "
|
||||
"el a programokat."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1519
|
||||
#: pcbnew/pcb_edit_frame.cpp:1512
|
||||
msgid "Eeschema netlist"
|
||||
msgstr "Eeschema netlista"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1530
|
||||
#: pcbnew/pcb_edit_frame.cpp:1523
|
||||
msgid ""
|
||||
"Received an error while reading netlist. Please report this issue to the "
|
||||
"KiCad team using the menu Help->Report Bug."
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1557
|
||||
#: pcbnew/pcb_edit_frame.cpp:1550
|
||||
#, fuzzy, c-format
|
||||
msgid "Schematic file '%s' not found."
|
||||
msgstr "A(z) \"%s\" kapcsolási rajz fájl nem található."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1587
|
||||
#: pcbnew/pcb_edit_frame.cpp:1580
|
||||
#, fuzzy
|
||||
msgid "Eeschema failed to load."
|
||||
msgstr "A Kapcsolási rajz szerkesztőnek nem sikerült betöltenie:\n"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1738
|
||||
#: pcbnew/pcb_edit_frame.cpp:1731
|
||||
#, fuzzy
|
||||
msgid "Edit design rules"
|
||||
msgstr "Tervezési szabályok"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1750
|
||||
#: pcbnew/pcb_edit_frame.cpp:1743
|
||||
#, fuzzy
|
||||
msgid "Could not compile custom design rules."
|
||||
msgstr "Nem sikerült megnyitni a konfigurációs fájlt"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1785
|
||||
#: pcbnew/pcb_edit_frame.cpp:1778
|
||||
msgid "Export Hyperlynx Layout"
|
||||
msgstr "Nyákterv exportálása Hyperlynx formátumba"
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:95 pcbnew/pcb_expr_evaluator.cpp:264
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:330 pcbnew/pcb_expr_evaluator.cpp:396
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:614 pcbnew/pcb_expr_evaluator.cpp:716
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:829
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:824
|
||||
#, c-format
|
||||
msgid "Missing argument to '%s'"
|
||||
msgstr ""
|
||||
|
|
@ -32576,7 +32572,7 @@ msgstr "Alkatrészrajzolat határolódoboza nincs megadva"
|
|||
msgid "Footprint has no back courtyard."
|
||||
msgstr "Alkatrészrajzolat határolódoboza nincs megadva"
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1152
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1153
|
||||
msgid "must be mm, in, or mil"
|
||||
msgstr ""
|
||||
|
||||
|
|
@ -38043,6 +38039,10 @@ msgstr "Kapcsolási rajz szerkesztése"
|
|||
msgid "KiCad Printed Circuit Board"
|
||||
msgstr "KiCad nyákterv fájl (*.brd)"
|
||||
|
||||
#, fuzzy
|
||||
#~ msgid "Net CodewxT( "
|
||||
#~ msgstr "Vezeték kód"
|
||||
|
||||
#, fuzzy
|
||||
#~ msgid "Save changes to schematic before closing?"
|
||||
#~ msgstr ""
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@ msgid ""
|
|||
msgstr ""
|
||||
"Project-Id-Version: KiCad\n"
|
||||
"Report-Msgid-Bugs-To: \n"
|
||||
"POT-Creation-Date: 2022-02-14 09:20-0800\n"
|
||||
"POT-Creation-Date: 2022-02-16 17:22-0800\n"
|
||||
"PO-Revision-Date: 2021-11-22 17:30+0000\n"
|
||||
"Last-Translator: whenwesober <naomi16i_1298q@cikuh.com>\n"
|
||||
"Language-Team: Indonesian <https://hosted.weblate.org/projects/kicad/master-"
|
||||
|
|
@ -4545,12 +4545,12 @@ msgstr ""
|
|||
|
||||
#: common/filename_resolver.cpp:468
|
||||
#, fuzzy
|
||||
msgid "This path:wxT( "
|
||||
msgid "This path:"
|
||||
msgstr "Path ini:"
|
||||
|
||||
#: common/filename_resolver.cpp:471
|
||||
#, fuzzy
|
||||
msgid "Existing path:wxT( "
|
||||
msgid "Existing path:"
|
||||
msgstr "Path wujud:"
|
||||
|
||||
#: common/filename_resolver.cpp:473
|
||||
|
|
@ -12934,8 +12934,9 @@ msgstr ""
|
|||
msgid "Connection Name"
|
||||
msgstr ""
|
||||
|
||||
#: eeschema/sch_connection.cpp:415
|
||||
msgid "Net CodewxT( "
|
||||
#: eeschema/sch_connection.cpp:415 pcbnew/dialogs/dialog_net_inspector.cpp:76
|
||||
#: pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr ""
|
||||
|
||||
#: eeschema/sch_connection.cpp:420 eeschema/sch_connection.cpp:433
|
||||
|
|
@ -18481,8 +18482,8 @@ msgid "Application failed to load:\n"
|
|||
msgstr "Aplikasi gagal dimuat:\n"
|
||||
|
||||
#: kicad/tools/kicad_manager_control.cpp:670
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1558
|
||||
#: pcbnew/pcb_edit_frame.cpp:1588
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1551
|
||||
#: pcbnew/pcb_edit_frame.cpp:1581
|
||||
msgid "KiCad Error"
|
||||
msgstr "Kesalahan KiCad"
|
||||
|
||||
|
|
@ -21371,7 +21372,7 @@ msgstr ""
|
|||
|
||||
#: pcbnew/dialogs/dialog_board_setup.cpp:108
|
||||
#: pcbnew/dialogs/dialog_constraints_reporter.cpp:54
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1744
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1737
|
||||
msgid "Custom Rules"
|
||||
msgstr ""
|
||||
|
||||
|
|
@ -24323,10 +24324,6 @@ msgstr ""
|
|||
msgid "Move Item"
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:76 pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:77 pcbnew/netinfo_item.cpp:74
|
||||
msgid "Net Name"
|
||||
msgstr ""
|
||||
|
|
@ -27686,8 +27683,8 @@ msgid ""
|
|||
" A.inDiffPair('<net_name>')\n"
|
||||
"True if `A` has net that is part of the specified differential pair.\n"
|
||||
"`<net_name>` is the base name of the differential pair. For example, "
|
||||
"`inDiffPair('CLK')`\n"
|
||||
"matches items in the `CLK_P` and `CLK_N` nets.\n"
|
||||
"`inDiffPair('/CLK')`\n"
|
||||
"matches items in the `/CLK_P` and `/CLK_N` nets.\n"
|
||||
"<br><br>\n"
|
||||
"\n"
|
||||
" AB.isCoupledDiffPair()\n"
|
||||
|
|
@ -27727,20 +27724,20 @@ msgid ""
|
|||
" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Distance between Vias of Different Nets\" \n"
|
||||
" (rule \"Distance between Vias of Different Nets\"\n"
|
||||
" (constraint hole_to_hole (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
" (rule \"Clearance between Pads of Different Nets\" \n"
|
||||
" (rule \"Clearance between Pads of Different Nets\"\n"
|
||||
" (constraint clearance (min 3.0mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Via Hole to Track Clearance\" \n"
|
||||
" (rule \"Via Hole to Track Clearance\"\n"
|
||||
" (constraint hole_clearance (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Track'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Pad to Track Clearance\" \n"
|
||||
" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n"
|
||||
"\n"
|
||||
" (rule \"Pad to Track Clearance\"\n"
|
||||
" (constraint clearance (min 0.2mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -27750,11 +27747,11 @@ msgid ""
|
|||
" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\" \n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\"\n"
|
||||
" (constraint hole_size (max 6.3mm))\n"
|
||||
" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Max Drill Hole Size PTH\" \n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size PTH\"\n"
|
||||
" (constraint hole_size (max 6.35mm))\n"
|
||||
" (condition \"A.Pad_Type == 'Through-hole'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -27762,7 +27759,7 @@ msgid ""
|
|||
" # Specify an optimal gap for a particular diff-pair\n"
|
||||
" (rule \"dp clock gap\"\n"
|
||||
" (constraint diff_pair_gap (opt \"0.8mm\"))\n"
|
||||
" (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n"
|
||||
" (condition \"A.inDiffPair('/CLK')\"))\n"
|
||||
"\n"
|
||||
" # Specify a larger clearance around any diff-pair\n"
|
||||
" (rule \"dp clearance\"\n"
|
||||
|
|
@ -30246,54 +30243,54 @@ msgstr "Berkas papan sirkuit hanya bisa dibaca."
|
|||
msgid "PCB file changes are unsaved"
|
||||
msgstr "Perubahan berkas PCB tidak disimpan"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1473
|
||||
#: pcbnew/pcb_edit_frame.cpp:1466
|
||||
msgid "The schematic for this board cannot be found."
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1497
|
||||
#: pcbnew/pcb_edit_frame.cpp:1490
|
||||
msgid ""
|
||||
"Cannot update the PCB because PCB editor is opened in stand-alone mode. In "
|
||||
"order to create or update PCBs from schematics, you must launch the KiCad "
|
||||
"project manager and create a project."
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1519
|
||||
#: pcbnew/pcb_edit_frame.cpp:1512
|
||||
msgid "Eeschema netlist"
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1530
|
||||
#: pcbnew/pcb_edit_frame.cpp:1523
|
||||
msgid ""
|
||||
"Received an error while reading netlist. Please report this issue to the "
|
||||
"KiCad team using the menu Help->Report Bug."
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1557
|
||||
#: pcbnew/pcb_edit_frame.cpp:1550
|
||||
#, fuzzy, c-format
|
||||
msgid "Schematic file '%s' not found."
|
||||
msgstr "Berkas skematik \"%s\" tidak ditemukan."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1587
|
||||
#: pcbnew/pcb_edit_frame.cpp:1580
|
||||
#, fuzzy
|
||||
msgid "Eeschema failed to load."
|
||||
msgstr "Aplikasi gagal dimuat."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1738
|
||||
#: pcbnew/pcb_edit_frame.cpp:1731
|
||||
#, fuzzy
|
||||
msgid "Edit design rules"
|
||||
msgstr "Sunting Berkas"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1750
|
||||
#: pcbnew/pcb_edit_frame.cpp:1743
|
||||
msgid "Could not compile custom design rules."
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1785
|
||||
#: pcbnew/pcb_edit_frame.cpp:1778
|
||||
msgid "Export Hyperlynx Layout"
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:95 pcbnew/pcb_expr_evaluator.cpp:264
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:330 pcbnew/pcb_expr_evaluator.cpp:396
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:614 pcbnew/pcb_expr_evaluator.cpp:716
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:829
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:824
|
||||
#, c-format
|
||||
msgid "Missing argument to '%s'"
|
||||
msgstr ""
|
||||
|
|
@ -30315,7 +30312,7 @@ msgstr ""
|
|||
msgid "Footprint has no back courtyard."
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1152
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1153
|
||||
msgid "must be mm, in, or mil"
|
||||
msgstr ""
|
||||
|
||||
|
|
|
|||
|
|
@ -102,7 +102,7 @@ msgid ""
|
|||
msgstr ""
|
||||
"Project-Id-Version: KiCad\n"
|
||||
"Report-Msgid-Bugs-To: \n"
|
||||
"POT-Creation-Date: 2022-02-14 09:20-0800\n"
|
||||
"POT-Creation-Date: 2022-02-16 17:22-0800\n"
|
||||
"PO-Revision-Date: 2022-02-10 21:56+0100\n"
|
||||
"Last-Translator: Marco Ciampa <ciampix@posteo.net>\n"
|
||||
"Language-Team: Italian <https://hosted.weblate.org/projects/kicad/master-"
|
||||
|
|
@ -4706,11 +4706,13 @@ msgid "Alias: "
|
|||
msgstr "Alias: "
|
||||
|
||||
#: common/filename_resolver.cpp:468
|
||||
msgid "This path:wxT( "
|
||||
#, fuzzy
|
||||
msgid "This path:"
|
||||
msgstr "Questo percorso:wxT( "
|
||||
|
||||
#: common/filename_resolver.cpp:471
|
||||
msgid "Existing path:wxT( "
|
||||
#, fuzzy
|
||||
msgid "Existing path:"
|
||||
msgstr "Percorso esistente:wxT("
|
||||
|
||||
#: common/filename_resolver.cpp:473
|
||||
|
|
@ -13486,9 +13488,9 @@ msgstr "Netclass assegnata"
|
|||
msgid "Connection Name"
|
||||
msgstr "Nome connessione"
|
||||
|
||||
#: eeschema/sch_connection.cpp:415
|
||||
#, fuzzy
|
||||
msgid "Net CodewxT( "
|
||||
#: eeschema/sch_connection.cpp:415 pcbnew/dialogs/dialog_net_inspector.cpp:76
|
||||
#: pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr "Codice connessione"
|
||||
|
||||
#: eeschema/sch_connection.cpp:420 eeschema/sch_connection.cpp:433
|
||||
|
|
@ -19106,8 +19108,8 @@ msgid "Application failed to load:\n"
|
|||
msgstr "L'app ha fallito il caricamento:\n"
|
||||
|
||||
#: kicad/tools/kicad_manager_control.cpp:670
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1558
|
||||
#: pcbnew/pcb_edit_frame.cpp:1588
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1551
|
||||
#: pcbnew/pcb_edit_frame.cpp:1581
|
||||
msgid "KiCad Error"
|
||||
msgstr "Errore KiCad"
|
||||
|
||||
|
|
@ -22150,7 +22152,7 @@ msgstr "Dimensioni predefinite"
|
|||
|
||||
#: pcbnew/dialogs/dialog_board_setup.cpp:108
|
||||
#: pcbnew/dialogs/dialog_constraints_reporter.cpp:54
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1744
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1737
|
||||
msgid "Custom Rules"
|
||||
msgstr "Regole personalizzate"
|
||||
|
||||
|
|
@ -25222,10 +25224,6 @@ msgstr "Usa coordinate polari"
|
|||
msgid "Move Item"
|
||||
msgstr "Sposta elemento"
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:76 pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr "Codice connessione"
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:77 pcbnew/netinfo_item.cpp:74
|
||||
msgid "Net Name"
|
||||
msgstr "Nome collegamento"
|
||||
|
|
@ -28822,8 +28820,8 @@ msgid ""
|
|||
" A.inDiffPair('<net_name>')\n"
|
||||
"True if `A` has net that is part of the specified differential pair.\n"
|
||||
"`<net_name>` is the base name of the differential pair. For example, "
|
||||
"`inDiffPair('CLK')`\n"
|
||||
"matches items in the `CLK_P` and `CLK_N` nets.\n"
|
||||
"`inDiffPair('/CLK')`\n"
|
||||
"matches items in the `/CLK_P` and `/CLK_N` nets.\n"
|
||||
"<br><br>\n"
|
||||
"\n"
|
||||
" AB.isCoupledDiffPair()\n"
|
||||
|
|
@ -28863,20 +28861,20 @@ msgid ""
|
|||
" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Distance between Vias of Different Nets\" \n"
|
||||
" (rule \"Distance between Vias of Different Nets\"\n"
|
||||
" (constraint hole_to_hole (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
" (rule \"Clearance between Pads of Different Nets\" \n"
|
||||
" (rule \"Clearance between Pads of Different Nets\"\n"
|
||||
" (constraint clearance (min 3.0mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Via Hole to Track Clearance\" \n"
|
||||
" (rule \"Via Hole to Track Clearance\"\n"
|
||||
" (constraint hole_clearance (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Track'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Pad to Track Clearance\" \n"
|
||||
" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n"
|
||||
"\n"
|
||||
" (rule \"Pad to Track Clearance\"\n"
|
||||
" (constraint clearance (min 0.2mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -28886,11 +28884,11 @@ msgid ""
|
|||
" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\" \n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\"\n"
|
||||
" (constraint hole_size (max 6.3mm))\n"
|
||||
" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Max Drill Hole Size PTH\" \n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size PTH\"\n"
|
||||
" (constraint hole_size (max 6.35mm))\n"
|
||||
" (condition \"A.Pad_Type == 'Through-hole'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -28898,7 +28896,7 @@ msgid ""
|
|||
" # Specify an optimal gap for a particular diff-pair\n"
|
||||
" (rule \"dp clock gap\"\n"
|
||||
" (constraint diff_pair_gap (opt \"0.8mm\"))\n"
|
||||
" (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n"
|
||||
" (condition \"A.inDiffPair('/CLK')\"))\n"
|
||||
"\n"
|
||||
" # Specify a larger clearance around any diff-pair\n"
|
||||
" (rule \"dp clearance\"\n"
|
||||
|
|
@ -31415,11 +31413,11 @@ msgstr "Il file scheda è in sola lettura."
|
|||
msgid "PCB file changes are unsaved"
|
||||
msgstr "Cambiamenti file C.S. non salvati"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1473
|
||||
#: pcbnew/pcb_edit_frame.cpp:1466
|
||||
msgid "The schematic for this board cannot be found."
|
||||
msgstr "Schema elettrico per questa scheda non trovato."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1497
|
||||
#: pcbnew/pcb_edit_frame.cpp:1490
|
||||
msgid ""
|
||||
"Cannot update the PCB because PCB editor is opened in stand-alone mode. In "
|
||||
"order to create or update PCBs from schematics, you must launch the KiCad "
|
||||
|
|
@ -31429,11 +31427,11 @@ msgstr ""
|
|||
"Per creare/aggiornare un C.S. da uno schema elettrico, è necessario eseguire "
|
||||
"il gestore di progetti KiCad e creare un progetto."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1519
|
||||
#: pcbnew/pcb_edit_frame.cpp:1512
|
||||
msgid "Eeschema netlist"
|
||||
msgstr "Netlist Eeschema"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1530
|
||||
#: pcbnew/pcb_edit_frame.cpp:1523
|
||||
msgid ""
|
||||
"Received an error while reading netlist. Please report this issue to the "
|
||||
"KiCad team using the menu Help->Report Bug."
|
||||
|
|
@ -31441,31 +31439,31 @@ msgstr ""
|
|||
"Ricevuto errore durante la lettura della netlist. Prego trasmettere questo "
|
||||
"problema al team KiCad usando il menu Aiuto->Segnala bug."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1557
|
||||
#: pcbnew/pcb_edit_frame.cpp:1550
|
||||
#, c-format
|
||||
msgid "Schematic file '%s' not found."
|
||||
msgstr "File schema elettrico '%s' non trovato."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1587
|
||||
#: pcbnew/pcb_edit_frame.cpp:1580
|
||||
msgid "Eeschema failed to load."
|
||||
msgstr "Eeschema ha fallito il caricamento."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1738
|
||||
#: pcbnew/pcb_edit_frame.cpp:1731
|
||||
msgid "Edit design rules"
|
||||
msgstr "Modifica regole di progettazione"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1750
|
||||
#: pcbnew/pcb_edit_frame.cpp:1743
|
||||
msgid "Could not compile custom design rules."
|
||||
msgstr "Impossibile compilare le regole di progettazione personalizzate."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1785
|
||||
#: pcbnew/pcb_edit_frame.cpp:1778
|
||||
msgid "Export Hyperlynx Layout"
|
||||
msgstr "Esporta progetto in Hyperlynx"
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:95 pcbnew/pcb_expr_evaluator.cpp:264
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:330 pcbnew/pcb_expr_evaluator.cpp:396
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:614 pcbnew/pcb_expr_evaluator.cpp:716
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:829
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:824
|
||||
#, c-format
|
||||
msgid "Missing argument to '%s'"
|
||||
msgstr "Argomento mancante a \"%s\""
|
||||
|
|
@ -31487,7 +31485,7 @@ msgstr "L'impronta non ha un ingombro fronte"
|
|||
msgid "Footprint has no back courtyard."
|
||||
msgstr "L'impronta non ha un ingombro retro"
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1152
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1153
|
||||
msgid "must be mm, in, or mil"
|
||||
msgstr "deve essere mm, in o mil"
|
||||
|
||||
|
|
@ -36729,6 +36727,10 @@ msgstr "Schema non-KiCad..."
|
|||
msgid "KiCad Printed Circuit Board"
|
||||
msgstr "File di circuiti stampati KiCad"
|
||||
|
||||
#, fuzzy
|
||||
#~ msgid "Net CodewxT( "
|
||||
#~ msgstr "Codice connessione"
|
||||
|
||||
#~ msgid "kicad"
|
||||
#~ msgstr "kicad"
|
||||
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@ msgid ""
|
|||
msgstr ""
|
||||
"Project-Id-Version: kicad\n"
|
||||
"Report-Msgid-Bugs-To: \n"
|
||||
"POT-Creation-Date: 2022-02-14 09:20-0800\n"
|
||||
"POT-Creation-Date: 2022-02-16 17:22-0800\n"
|
||||
"PO-Revision-Date: 2022-02-16 13:03+0000\n"
|
||||
"Last-Translator: Tokita, Hiroshi <tokita.hiroshi@jp.fujitsu.com>\n"
|
||||
"Language-Team: Japanese <https://hosted.weblate.org/projects/kicad/v6/ja/>\n"
|
||||
|
|
@ -4563,12 +4563,12 @@ msgstr "エイリアス: "
|
|||
|
||||
#: common/filename_resolver.cpp:468
|
||||
#, fuzzy
|
||||
msgid "This path:wxT( "
|
||||
msgid "This path:"
|
||||
msgstr "このパス:"
|
||||
|
||||
#: common/filename_resolver.cpp:471
|
||||
#, fuzzy
|
||||
msgid "Existing path:wxT( "
|
||||
msgid "Existing path:"
|
||||
msgstr "存在するパス:"
|
||||
|
||||
#: common/filename_resolver.cpp:473
|
||||
|
|
@ -13305,9 +13305,9 @@ msgstr "割り当てられたネットクラス"
|
|||
msgid "Connection Name"
|
||||
msgstr "接続名"
|
||||
|
||||
#: eeschema/sch_connection.cpp:415
|
||||
#, fuzzy
|
||||
msgid "Net CodewxT( "
|
||||
#: eeschema/sch_connection.cpp:415 pcbnew/dialogs/dialog_net_inspector.cpp:76
|
||||
#: pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr "ネット コード"
|
||||
|
||||
#: eeschema/sch_connection.cpp:420 eeschema/sch_connection.cpp:433
|
||||
|
|
@ -19054,8 +19054,8 @@ msgid "Application failed to load:\n"
|
|||
msgstr "アプリケーションのロードに失敗:\n"
|
||||
|
||||
#: kicad/tools/kicad_manager_control.cpp:670
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1558
|
||||
#: pcbnew/pcb_edit_frame.cpp:1588
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1551
|
||||
#: pcbnew/pcb_edit_frame.cpp:1581
|
||||
msgid "KiCad Error"
|
||||
msgstr "KiCad エラー"
|
||||
|
||||
|
|
@ -20623,16 +20623,17 @@ msgid ""
|
|||
msgstr ""
|
||||
"最大電流を指定した場合、トレース幅は適合するように計算されます。\n"
|
||||
"\n"
|
||||
"トレース幅の一つを指定した場合、まず扱える最大電流が計算されます。それから、この電流を扱えるように別のトレース幅が計算されます。\n"
|
||||
"トレース幅の一つを指定した場合、まず扱える最大電流が計算されます。それから、"
|
||||
"この電流を扱えるように別のトレース幅が計算されます。\n"
|
||||
"\n"
|
||||
"制御する値はボールド体で表示されます。\n"
|
||||
"\n"
|
||||
"計算は、電流 35 A (外部) または 17.5 A (内部) まで、温度上昇は 100℃ まで、幅は 400mil (10mm) "
|
||||
"までの範囲で有効です。\n"
|
||||
"計算は、電流 35 A (外部) または 17.5 A (内部) まで、温度上昇は 100℃ まで、幅"
|
||||
"は 400mil (10mm) までの範囲で有効です。\n"
|
||||
"\n"
|
||||
"計算式 (IPC 2221 より)\n"
|
||||
"<center>___I = K ⋅ ΔT<sup>0.44</sup> ⋅ (W ⋅ H)<sup>0."
|
||||
"725</sup>___</center>\n"
|
||||
"<center>___I = K ⋅ ΔT<sup>0.44</sup> ⋅ (W ⋅ "
|
||||
"H)<sup>0.725</sup>___</center>\n"
|
||||
"ここでは:<br>\n"
|
||||
"__I__ = 最大電流 (A)<br>\n"
|
||||
"__dt__ = 周囲環境からの温度上昇 (℃)<br>\n"
|
||||
|
|
@ -22084,7 +22085,7 @@ msgstr "定義済みのサイズ"
|
|||
|
||||
#: pcbnew/dialogs/dialog_board_setup.cpp:108
|
||||
#: pcbnew/dialogs/dialog_constraints_reporter.cpp:54
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1744
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1737
|
||||
msgid "Custom Rules"
|
||||
msgstr "カスタムルール"
|
||||
|
||||
|
|
@ -25124,10 +25125,6 @@ msgstr "極座標を使用する"
|
|||
msgid "Move Item"
|
||||
msgstr "アイテムを移動"
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:76 pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr "ネット コード"
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:77 pcbnew/netinfo_item.cpp:74
|
||||
msgid "Net Name"
|
||||
msgstr "ネット名"
|
||||
|
|
@ -28558,6 +28555,7 @@ msgid "Check rule syntax"
|
|||
msgstr "ルールの文法をチェック"
|
||||
|
||||
#: pcbnew/dialogs/panel_setup_rules_help_md.h:2
|
||||
#, fuzzy
|
||||
msgid ""
|
||||
"### Top-level Clauses\n"
|
||||
"\n"
|
||||
|
|
@ -28683,8 +28681,8 @@ msgid ""
|
|||
" A.inDiffPair('<net_name>')\n"
|
||||
"True if `A` has net that is part of the specified differential pair.\n"
|
||||
"`<net_name>` is the base name of the differential pair. For example, "
|
||||
"`inDiffPair('CLK')`\n"
|
||||
"matches items in the `CLK_P` and `CLK_N` nets.\n"
|
||||
"`inDiffPair('/CLK')`\n"
|
||||
"matches items in the `/CLK_P` and `/CLK_N` nets.\n"
|
||||
"<br><br>\n"
|
||||
"\n"
|
||||
" AB.isCoupledDiffPair()\n"
|
||||
|
|
@ -28724,20 +28722,20 @@ msgid ""
|
|||
" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Distance between Vias of Different Nets\" \n"
|
||||
" (rule \"Distance between Vias of Different Nets\"\n"
|
||||
" (constraint hole_to_hole (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
" (rule \"Clearance between Pads of Different Nets\" \n"
|
||||
" (rule \"Clearance between Pads of Different Nets\"\n"
|
||||
" (constraint clearance (min 3.0mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Via Hole to Track Clearance\" \n"
|
||||
" (rule \"Via Hole to Track Clearance\"\n"
|
||||
" (constraint hole_clearance (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Track'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Pad to Track Clearance\" \n"
|
||||
" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n"
|
||||
"\n"
|
||||
" (rule \"Pad to Track Clearance\"\n"
|
||||
" (constraint clearance (min 0.2mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -28747,11 +28745,11 @@ msgid ""
|
|||
" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\" \n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\"\n"
|
||||
" (constraint hole_size (max 6.3mm))\n"
|
||||
" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Max Drill Hole Size PTH\" \n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size PTH\"\n"
|
||||
" (constraint hole_size (max 6.35mm))\n"
|
||||
" (condition \"A.Pad_Type == 'Through-hole'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -28759,7 +28757,7 @@ msgid ""
|
|||
" # Specify an optimal gap for a particular diff-pair\n"
|
||||
" (rule \"dp clock gap\"\n"
|
||||
" (constraint diff_pair_gap (opt \"0.8mm\"))\n"
|
||||
" (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n"
|
||||
" (condition \"A.inDiffPair('/CLK')\"))\n"
|
||||
"\n"
|
||||
" # Specify a larger clearance around any diff-pair\n"
|
||||
" (rule \"dp clearance\"\n"
|
||||
|
|
@ -31472,11 +31470,11 @@ msgstr "基板ファイルは読み込み専用です。"
|
|||
msgid "PCB file changes are unsaved"
|
||||
msgstr "基板ファイルの変更は保存されていません"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1473
|
||||
#: pcbnew/pcb_edit_frame.cpp:1466
|
||||
msgid "The schematic for this board cannot be found."
|
||||
msgstr "この基板の回路図が見つけられません。"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1497
|
||||
#: pcbnew/pcb_edit_frame.cpp:1490
|
||||
msgid ""
|
||||
"Cannot update the PCB because PCB editor is opened in stand-alone mode. In "
|
||||
"order to create or update PCBs from schematics, you must launch the KiCad "
|
||||
|
|
@ -31486,11 +31484,11 @@ msgstr ""
|
|||
"きません。回路図から基板を作成または更新するには、KiCad プロジェクト マネー"
|
||||
"ジャーを起動して、プロジェクトを作成しなければなりません。"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1519
|
||||
#: pcbnew/pcb_edit_frame.cpp:1512
|
||||
msgid "Eeschema netlist"
|
||||
msgstr "Eeschema ネットリスト"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1530
|
||||
#: pcbnew/pcb_edit_frame.cpp:1523
|
||||
msgid ""
|
||||
"Received an error while reading netlist. Please report this issue to the "
|
||||
"KiCad team using the menu Help->Report Bug."
|
||||
|
|
@ -31498,31 +31496,31 @@ msgstr ""
|
|||
"ネットリストの読み取り中にエラーが発生しました。 メニューのヘルプ > バグをレ"
|
||||
"ポート からKiCadチームにこの問題を報告してください。"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1557
|
||||
#: pcbnew/pcb_edit_frame.cpp:1550
|
||||
#, c-format
|
||||
msgid "Schematic file '%s' not found."
|
||||
msgstr "回路図ファイル '%s' が見つかりません。"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1587
|
||||
#: pcbnew/pcb_edit_frame.cpp:1580
|
||||
msgid "Eeschema failed to load."
|
||||
msgstr "Eeschema のロードに失敗しました。"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1738
|
||||
#: pcbnew/pcb_edit_frame.cpp:1731
|
||||
msgid "Edit design rules"
|
||||
msgstr "デザインルールを編集"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1750
|
||||
#: pcbnew/pcb_edit_frame.cpp:1743
|
||||
msgid "Could not compile custom design rules."
|
||||
msgstr "カスタム デザインルールをコンパイルできません。"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1785
|
||||
#: pcbnew/pcb_edit_frame.cpp:1778
|
||||
msgid "Export Hyperlynx Layout"
|
||||
msgstr "HyperLynx レイアウトをエクスポート"
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:95 pcbnew/pcb_expr_evaluator.cpp:264
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:330 pcbnew/pcb_expr_evaluator.cpp:396
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:614 pcbnew/pcb_expr_evaluator.cpp:716
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:829
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:824
|
||||
#, c-format
|
||||
msgid "Missing argument to '%s'"
|
||||
msgstr "'%s' への引数がありません"
|
||||
|
|
@ -31544,7 +31542,7 @@ msgstr "フットプリントに表面のコートヤードがありません。
|
|||
msgid "Footprint has no back courtyard."
|
||||
msgstr "フットプリントに裏面のコートヤードがありません。"
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1152
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1153
|
||||
msgid "must be mm, in, or mil"
|
||||
msgstr "mm、in、または mil でなければなりません"
|
||||
|
||||
|
|
@ -36725,6 +36723,10 @@ msgstr "KiCad 回路図ファイル"
|
|||
msgid "KiCad Printed Circuit Board"
|
||||
msgstr "KiCad プリント基板ファイル"
|
||||
|
||||
#, fuzzy
|
||||
#~ msgid "Net CodewxT( "
|
||||
#~ msgstr "ネット コード"
|
||||
|
||||
#~ msgid "Save changes to schematic before closing?"
|
||||
#~ msgstr "閉じる前に回路図の変更を保存しますか?"
|
||||
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@ msgid ""
|
|||
msgstr ""
|
||||
"Project-Id-Version: kicad\n"
|
||||
"Report-Msgid-Bugs-To: \n"
|
||||
"POT-Creation-Date: 2022-02-14 09:20-0800\n"
|
||||
"POT-Creation-Date: 2022-02-16 17:22-0800\n"
|
||||
"PO-Revision-Date: 2022-02-14 17:18+0000\n"
|
||||
"Last-Translator: 김랑기 <korearf@gmail.com>\n"
|
||||
"Language-Team: Korean <https://hosted.weblate.org/projects/kicad/v6/ko/>\n"
|
||||
|
|
@ -4552,12 +4552,12 @@ msgstr "별칭: "
|
|||
|
||||
#: common/filename_resolver.cpp:468
|
||||
#, fuzzy
|
||||
msgid "This path:wxT( "
|
||||
msgid "This path:"
|
||||
msgstr "이 경로:"
|
||||
|
||||
#: common/filename_resolver.cpp:471
|
||||
#, fuzzy
|
||||
msgid "Existing path:wxT( "
|
||||
msgid "Existing path:"
|
||||
msgstr "기존 경로:"
|
||||
|
||||
#: common/filename_resolver.cpp:473
|
||||
|
|
@ -13238,9 +13238,9 @@ msgstr "할당된 네트클래스"
|
|||
msgid "Connection Name"
|
||||
msgstr "연결 이름"
|
||||
|
||||
#: eeschema/sch_connection.cpp:415
|
||||
#, fuzzy
|
||||
msgid "Net CodewxT( "
|
||||
#: eeschema/sch_connection.cpp:415 pcbnew/dialogs/dialog_net_inspector.cpp:76
|
||||
#: pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr "네트 코드"
|
||||
|
||||
#: eeschema/sch_connection.cpp:420 eeschema/sch_connection.cpp:433
|
||||
|
|
@ -18948,8 +18948,8 @@ msgid "Application failed to load:\n"
|
|||
msgstr "응용 프로그램 불러오기 실패:\n"
|
||||
|
||||
#: kicad/tools/kicad_manager_control.cpp:670
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1558
|
||||
#: pcbnew/pcb_edit_frame.cpp:1588
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1551
|
||||
#: pcbnew/pcb_edit_frame.cpp:1581
|
||||
msgid "KiCad Error"
|
||||
msgstr "KiCad 오류"
|
||||
|
||||
|
|
@ -21978,7 +21978,7 @@ msgstr "사전 정의된 크기"
|
|||
|
||||
#: pcbnew/dialogs/dialog_board_setup.cpp:108
|
||||
#: pcbnew/dialogs/dialog_constraints_reporter.cpp:54
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1744
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1737
|
||||
msgid "Custom Rules"
|
||||
msgstr "사용자 정의 규칙"
|
||||
|
||||
|
|
@ -24999,10 +24999,6 @@ msgstr "극 좌표계 사용"
|
|||
msgid "Move Item"
|
||||
msgstr "항목 이동"
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:76 pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr "네트 코드"
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:77 pcbnew/netinfo_item.cpp:74
|
||||
msgid "Net Name"
|
||||
msgstr "네트 이름"
|
||||
|
|
@ -28407,6 +28403,7 @@ msgid "Check rule syntax"
|
|||
msgstr "규칙 문법을 체크"
|
||||
|
||||
#: pcbnew/dialogs/panel_setup_rules_help_md.h:2
|
||||
#, fuzzy
|
||||
msgid ""
|
||||
"### Top-level Clauses\n"
|
||||
"\n"
|
||||
|
|
@ -28532,8 +28529,8 @@ msgid ""
|
|||
" A.inDiffPair('<net_name>')\n"
|
||||
"True if `A` has net that is part of the specified differential pair.\n"
|
||||
"`<net_name>` is the base name of the differential pair. For example, "
|
||||
"`inDiffPair('CLK')`\n"
|
||||
"matches items in the `CLK_P` and `CLK_N` nets.\n"
|
||||
"`inDiffPair('/CLK')`\n"
|
||||
"matches items in the `/CLK_P` and `/CLK_N` nets.\n"
|
||||
"<br><br>\n"
|
||||
"\n"
|
||||
" AB.isCoupledDiffPair()\n"
|
||||
|
|
@ -28573,20 +28570,20 @@ msgid ""
|
|||
" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Distance between Vias of Different Nets\" \n"
|
||||
" (rule \"Distance between Vias of Different Nets\"\n"
|
||||
" (constraint hole_to_hole (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
" (rule \"Clearance between Pads of Different Nets\" \n"
|
||||
" (rule \"Clearance between Pads of Different Nets\"\n"
|
||||
" (constraint clearance (min 3.0mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Via Hole to Track Clearance\" \n"
|
||||
" (rule \"Via Hole to Track Clearance\"\n"
|
||||
" (constraint hole_clearance (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Track'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Pad to Track Clearance\" \n"
|
||||
" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n"
|
||||
"\n"
|
||||
" (rule \"Pad to Track Clearance\"\n"
|
||||
" (constraint clearance (min 0.2mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -28596,11 +28593,11 @@ msgid ""
|
|||
" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\" \n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\"\n"
|
||||
" (constraint hole_size (max 6.3mm))\n"
|
||||
" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Max Drill Hole Size PTH\" \n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size PTH\"\n"
|
||||
" (constraint hole_size (max 6.35mm))\n"
|
||||
" (condition \"A.Pad_Type == 'Through-hole'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -28608,7 +28605,7 @@ msgid ""
|
|||
" # Specify an optimal gap for a particular diff-pair\n"
|
||||
" (rule \"dp clock gap\"\n"
|
||||
" (constraint diff_pair_gap (opt \"0.8mm\"))\n"
|
||||
" (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n"
|
||||
" (condition \"A.inDiffPair('/CLK')\"))\n"
|
||||
"\n"
|
||||
" # Specify a larger clearance around any diff-pair\n"
|
||||
" (rule \"dp clearance\"\n"
|
||||
|
|
@ -31305,11 +31302,11 @@ msgstr "기판 파일은 읽기 전용입니다."
|
|||
msgid "PCB file changes are unsaved"
|
||||
msgstr "PCB 파일 변경점이 저장되지 않음"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1473
|
||||
#: pcbnew/pcb_edit_frame.cpp:1466
|
||||
msgid "The schematic for this board cannot be found."
|
||||
msgstr "이 기판의 회로도를 찾을 수 없습니다."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1497
|
||||
#: pcbnew/pcb_edit_frame.cpp:1490
|
||||
msgid ""
|
||||
"Cannot update the PCB because PCB editor is opened in stand-alone mode. In "
|
||||
"order to create or update PCBs from schematics, you must launch the KiCad "
|
||||
|
|
@ -31319,11 +31316,11 @@ msgstr ""
|
|||
"다. 회로도로부터 PCB를 생성하거나 업데이트하려면, KiCad 프로젝트 매니저를 실"
|
||||
"행하여 프로젝트를 생성하세요."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1519
|
||||
#: pcbnew/pcb_edit_frame.cpp:1512
|
||||
msgid "Eeschema netlist"
|
||||
msgstr "Eeschema 네트리스트"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1530
|
||||
#: pcbnew/pcb_edit_frame.cpp:1523
|
||||
msgid ""
|
||||
"Received an error while reading netlist. Please report this issue to the "
|
||||
"KiCad team using the menu Help->Report Bug."
|
||||
|
|
@ -31331,31 +31328,31 @@ msgstr ""
|
|||
"넷리스트를 읽는 동안 오류가 발생했습니다. 도움말->버그 보고 메뉴를 사용하여 "
|
||||
"KiCad 팀에 이 문제를 보고하십시오."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1557
|
||||
#: pcbnew/pcb_edit_frame.cpp:1550
|
||||
#, c-format
|
||||
msgid "Schematic file '%s' not found."
|
||||
msgstr "회로도 파일 '%s'을(를) 찾을 수 없습니다."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1587
|
||||
#: pcbnew/pcb_edit_frame.cpp:1580
|
||||
msgid "Eeschema failed to load."
|
||||
msgstr "Eeschema 로드에 실패했습니다."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1738
|
||||
#: pcbnew/pcb_edit_frame.cpp:1731
|
||||
msgid "Edit design rules"
|
||||
msgstr "디자인 규칙 편집"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1750
|
||||
#: pcbnew/pcb_edit_frame.cpp:1743
|
||||
msgid "Could not compile custom design rules."
|
||||
msgstr "사용자 정의 디자인 규칙을 컴파일할 수 없습니다."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1785
|
||||
#: pcbnew/pcb_edit_frame.cpp:1778
|
||||
msgid "Export Hyperlynx Layout"
|
||||
msgstr "Hyperlynx 레이아웃 내보내기"
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:95 pcbnew/pcb_expr_evaluator.cpp:264
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:330 pcbnew/pcb_expr_evaluator.cpp:396
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:614 pcbnew/pcb_expr_evaluator.cpp:716
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:829
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:824
|
||||
#, c-format
|
||||
msgid "Missing argument to '%s'"
|
||||
msgstr "'%s'에 대한 인수가 없습니다"
|
||||
|
|
@ -31377,7 +31374,7 @@ msgstr "풋프린트에 전면 코트야드가 없습니다."
|
|||
msgid "Footprint has no back courtyard."
|
||||
msgstr "풋프린트에 후면 코트야드가 없습니다."
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1152
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1153
|
||||
msgid "must be mm, in, or mil"
|
||||
msgstr "mm, in 또는 mil이어야 합니다"
|
||||
|
||||
|
|
@ -36545,6 +36542,10 @@ msgstr "KiCad 회로도"
|
|||
msgid "KiCad Printed Circuit Board"
|
||||
msgstr "KiCad 인쇄 회로 기판"
|
||||
|
||||
#, fuzzy
|
||||
#~ msgid "Net CodewxT( "
|
||||
#~ msgstr "네트 코드"
|
||||
|
||||
#~ msgid "Save changes to schematic before closing?"
|
||||
#~ msgstr "회로도를 닫기 전에 변경 내용을 저장 하겠습니까?"
|
||||
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@ msgid ""
|
|||
msgstr ""
|
||||
"Project-Id-Version: KiCad 4.0\n"
|
||||
"Report-Msgid-Bugs-To: \n"
|
||||
"POT-Creation-Date: 2022-02-14 09:20-0800\n"
|
||||
"POT-Creation-Date: 2022-02-16 17:22-0800\n"
|
||||
"PO-Revision-Date: 2021-08-20 19:52+0000\n"
|
||||
"Last-Translator: Seth Hillbrand <seth@kipro-pcb.com>\n"
|
||||
"Language-Team: Lithuanian <https://hosted.weblate.org/projects/kicad/master-"
|
||||
|
|
@ -4712,12 +4712,12 @@ msgstr "Pseudonimas: "
|
|||
|
||||
#: common/filename_resolver.cpp:468
|
||||
#, fuzzy
|
||||
msgid "This path:wxT( "
|
||||
msgid "This path:"
|
||||
msgstr "Šis kelias:"
|
||||
|
||||
#: common/filename_resolver.cpp:471
|
||||
#, fuzzy
|
||||
msgid "Existing path:wxT( "
|
||||
msgid "Existing path:"
|
||||
msgstr "Esamas kelias:"
|
||||
|
||||
#: common/filename_resolver.cpp:473
|
||||
|
|
@ -13578,9 +13578,9 @@ msgstr "Priskirtas „Netclass“"
|
|||
msgid "Connection Name"
|
||||
msgstr "Ryšio pavadinimas"
|
||||
|
||||
#: eeschema/sch_connection.cpp:415
|
||||
#, fuzzy
|
||||
msgid "Net CodewxT( "
|
||||
#: eeschema/sch_connection.cpp:415 pcbnew/dialogs/dialog_net_inspector.cpp:76
|
||||
#: pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr "Grandinės kodas"
|
||||
|
||||
#: eeschema/sch_connection.cpp:420 eeschema/sch_connection.cpp:433
|
||||
|
|
@ -19509,8 +19509,8 @@ msgid "Application failed to load:\n"
|
|||
msgstr "Nepavyko įkelti programos:\n"
|
||||
|
||||
#: kicad/tools/kicad_manager_control.cpp:670
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1558
|
||||
#: pcbnew/pcb_edit_frame.cpp:1588
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1551
|
||||
#: pcbnew/pcb_edit_frame.cpp:1581
|
||||
msgid "KiCad Error"
|
||||
msgstr "KiCad klaida"
|
||||
|
||||
|
|
@ -22672,7 +22672,7 @@ msgstr "Iš anksto nustatyti dydžiai"
|
|||
|
||||
#: pcbnew/dialogs/dialog_board_setup.cpp:108
|
||||
#: pcbnew/dialogs/dialog_constraints_reporter.cpp:54
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1744
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1737
|
||||
#, fuzzy
|
||||
msgid "Custom Rules"
|
||||
msgstr "Tinkinto sluoksnio rinkinys"
|
||||
|
|
@ -25765,10 +25765,6 @@ msgstr "Naudoti polines koordinates"
|
|||
msgid "Move Item"
|
||||
msgstr "Perkelti elementą"
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:76 pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr "Grandinės kodas"
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:77 pcbnew/netinfo_item.cpp:74
|
||||
msgid "Net Name"
|
||||
msgstr "Grandinės pavadinimas"
|
||||
|
|
@ -29370,8 +29366,8 @@ msgid ""
|
|||
" A.inDiffPair('<net_name>')\n"
|
||||
"True if `A` has net that is part of the specified differential pair.\n"
|
||||
"`<net_name>` is the base name of the differential pair. For example, "
|
||||
"`inDiffPair('CLK')`\n"
|
||||
"matches items in the `CLK_P` and `CLK_N` nets.\n"
|
||||
"`inDiffPair('/CLK')`\n"
|
||||
"matches items in the `/CLK_P` and `/CLK_N` nets.\n"
|
||||
"<br><br>\n"
|
||||
"\n"
|
||||
" AB.isCoupledDiffPair()\n"
|
||||
|
|
@ -29411,20 +29407,20 @@ msgid ""
|
|||
" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Distance between Vias of Different Nets\" \n"
|
||||
" (rule \"Distance between Vias of Different Nets\"\n"
|
||||
" (constraint hole_to_hole (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
" (rule \"Clearance between Pads of Different Nets\" \n"
|
||||
" (rule \"Clearance between Pads of Different Nets\"\n"
|
||||
" (constraint clearance (min 3.0mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Via Hole to Track Clearance\" \n"
|
||||
" (rule \"Via Hole to Track Clearance\"\n"
|
||||
" (constraint hole_clearance (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Track'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Pad to Track Clearance\" \n"
|
||||
" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n"
|
||||
"\n"
|
||||
" (rule \"Pad to Track Clearance\"\n"
|
||||
" (constraint clearance (min 0.2mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -29434,11 +29430,11 @@ msgid ""
|
|||
" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\" \n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\"\n"
|
||||
" (constraint hole_size (max 6.3mm))\n"
|
||||
" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Max Drill Hole Size PTH\" \n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size PTH\"\n"
|
||||
" (constraint hole_size (max 6.35mm))\n"
|
||||
" (condition \"A.Pad_Type == 'Through-hole'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -29446,7 +29442,7 @@ msgid ""
|
|||
" # Specify an optimal gap for a particular diff-pair\n"
|
||||
" (rule \"dp clock gap\"\n"
|
||||
" (constraint diff_pair_gap (opt \"0.8mm\"))\n"
|
||||
" (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n"
|
||||
" (condition \"A.inDiffPair('/CLK')\"))\n"
|
||||
"\n"
|
||||
" # Specify a larger clearance around any diff-pair\n"
|
||||
" (rule \"dp clearance\"\n"
|
||||
|
|
@ -32025,11 +32021,11 @@ msgstr "Tik lentos plotas"
|
|||
msgid "PCB file changes are unsaved"
|
||||
msgstr "PCB failo pakeitimai neišsaugoti"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1473
|
||||
#: pcbnew/pcb_edit_frame.cpp:1466
|
||||
msgid "The schematic for this board cannot be found."
|
||||
msgstr "Šios lentos schemos rasti negalima."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1497
|
||||
#: pcbnew/pcb_edit_frame.cpp:1490
|
||||
#, fuzzy
|
||||
msgid ""
|
||||
"Cannot update the PCB because PCB editor is opened in stand-alone mode. In "
|
||||
|
|
@ -32040,44 +32036,44 @@ msgstr ""
|
|||
"Norėdami sukurti ar atnaujinti PCB iš schemų, turite paleisti „KiCad“ "
|
||||
"projektų valdytoją ir sukurti projektą."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1519
|
||||
#: pcbnew/pcb_edit_frame.cpp:1512
|
||||
msgid "Eeschema netlist"
|
||||
msgstr "„Eeschema“ tinklaraštis"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1530
|
||||
#: pcbnew/pcb_edit_frame.cpp:1523
|
||||
msgid ""
|
||||
"Received an error while reading netlist. Please report this issue to the "
|
||||
"KiCad team using the menu Help->Report Bug."
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1557
|
||||
#: pcbnew/pcb_edit_frame.cpp:1550
|
||||
#, fuzzy, c-format
|
||||
msgid "Schematic file '%s' not found."
|
||||
msgstr "Scheminis failas „%s“ nerastas."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1587
|
||||
#: pcbnew/pcb_edit_frame.cpp:1580
|
||||
#, fuzzy
|
||||
msgid "Eeschema failed to load."
|
||||
msgstr "Eeschemos nepavyko įkelti:\n"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1738
|
||||
#: pcbnew/pcb_edit_frame.cpp:1731
|
||||
#, fuzzy
|
||||
msgid "Edit design rules"
|
||||
msgstr "Projektavimo taisyklės"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1750
|
||||
#: pcbnew/pcb_edit_frame.cpp:1743
|
||||
#, fuzzy
|
||||
msgid "Could not compile custom design rules."
|
||||
msgstr "KDR neišsami: nepavyko sudaryti projektavimo taisyklių. "
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1785
|
||||
#: pcbnew/pcb_edit_frame.cpp:1778
|
||||
msgid "Export Hyperlynx Layout"
|
||||
msgstr "Eksportuoti „Hyperlynx“ maketą"
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:95 pcbnew/pcb_expr_evaluator.cpp:264
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:330 pcbnew/pcb_expr_evaluator.cpp:396
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:614 pcbnew/pcb_expr_evaluator.cpp:716
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:829
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:824
|
||||
#, c-format
|
||||
msgid "Missing argument to '%s'"
|
||||
msgstr "Trūksta argumento „%s“"
|
||||
|
|
@ -32099,7 +32095,7 @@ msgstr "Pėdsakas neturi priekinio kiemo."
|
|||
msgid "Footprint has no back courtyard."
|
||||
msgstr "Pėdsakas neturi vidinio kiemo."
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1152
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1153
|
||||
msgid "must be mm, in, or mil"
|
||||
msgstr "turi būti mm, coliais arba mil"
|
||||
|
||||
|
|
@ -37447,6 +37443,10 @@ msgstr "Redaguoti schemą"
|
|||
msgid "KiCad Printed Circuit Board"
|
||||
msgstr "KiCad spausdintinių plokščių failai"
|
||||
|
||||
#, fuzzy
|
||||
#~ msgid "Net CodewxT( "
|
||||
#~ msgstr "Grandinės kodas"
|
||||
|
||||
#~ msgid "Save changes to schematic before closing?"
|
||||
#~ msgstr "Išsaugoti schemos pakeitimus prieš uždarant?"
|
||||
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@ msgid ""
|
|||
msgstr ""
|
||||
"Project-Id-Version: KiCad 6.0\n"
|
||||
"Report-Msgid-Bugs-To: \n"
|
||||
"POT-Creation-Date: 2022-02-14 09:20-0800\n"
|
||||
"POT-Creation-Date: 2022-02-16 17:22-0800\n"
|
||||
"PO-Revision-Date: 2021-01-13 14:21+0000\n"
|
||||
"Last-Translator: Rihards Skuja <rhssk@posteo.eu>\n"
|
||||
"Language-Team: Latvian <https://hosted.weblate.org/projects/kicad/master-"
|
||||
|
|
@ -4488,11 +4488,11 @@ msgid "Alias: "
|
|||
msgstr ""
|
||||
|
||||
#: common/filename_resolver.cpp:468
|
||||
msgid "This path:wxT( "
|
||||
msgid "This path:"
|
||||
msgstr ""
|
||||
|
||||
#: common/filename_resolver.cpp:471
|
||||
msgid "Existing path:wxT( "
|
||||
msgid "Existing path:"
|
||||
msgstr ""
|
||||
|
||||
#: common/filename_resolver.cpp:473
|
||||
|
|
@ -12742,8 +12742,9 @@ msgstr ""
|
|||
msgid "Connection Name"
|
||||
msgstr ""
|
||||
|
||||
#: eeschema/sch_connection.cpp:415
|
||||
msgid "Net CodewxT( "
|
||||
#: eeschema/sch_connection.cpp:415 pcbnew/dialogs/dialog_net_inspector.cpp:76
|
||||
#: pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr ""
|
||||
|
||||
#: eeschema/sch_connection.cpp:420 eeschema/sch_connection.cpp:433
|
||||
|
|
@ -18121,8 +18122,8 @@ msgid "Application failed to load:\n"
|
|||
msgstr ""
|
||||
|
||||
#: kicad/tools/kicad_manager_control.cpp:670
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1558
|
||||
#: pcbnew/pcb_edit_frame.cpp:1588
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1551
|
||||
#: pcbnew/pcb_edit_frame.cpp:1581
|
||||
msgid "KiCad Error"
|
||||
msgstr ""
|
||||
|
||||
|
|
@ -20981,7 +20982,7 @@ msgstr ""
|
|||
|
||||
#: pcbnew/dialogs/dialog_board_setup.cpp:108
|
||||
#: pcbnew/dialogs/dialog_constraints_reporter.cpp:54
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1744
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1737
|
||||
msgid "Custom Rules"
|
||||
msgstr ""
|
||||
|
||||
|
|
@ -23882,10 +23883,6 @@ msgstr ""
|
|||
msgid "Move Item"
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:76 pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:77 pcbnew/netinfo_item.cpp:74
|
||||
msgid "Net Name"
|
||||
msgstr ""
|
||||
|
|
@ -27226,8 +27223,8 @@ msgid ""
|
|||
" A.inDiffPair('<net_name>')\n"
|
||||
"True if `A` has net that is part of the specified differential pair.\n"
|
||||
"`<net_name>` is the base name of the differential pair. For example, "
|
||||
"`inDiffPair('CLK')`\n"
|
||||
"matches items in the `CLK_P` and `CLK_N` nets.\n"
|
||||
"`inDiffPair('/CLK')`\n"
|
||||
"matches items in the `/CLK_P` and `/CLK_N` nets.\n"
|
||||
"<br><br>\n"
|
||||
"\n"
|
||||
" AB.isCoupledDiffPair()\n"
|
||||
|
|
@ -27267,20 +27264,20 @@ msgid ""
|
|||
" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Distance between Vias of Different Nets\" \n"
|
||||
" (rule \"Distance between Vias of Different Nets\"\n"
|
||||
" (constraint hole_to_hole (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
" (rule \"Clearance between Pads of Different Nets\" \n"
|
||||
" (rule \"Clearance between Pads of Different Nets\"\n"
|
||||
" (constraint clearance (min 3.0mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Via Hole to Track Clearance\" \n"
|
||||
" (rule \"Via Hole to Track Clearance\"\n"
|
||||
" (constraint hole_clearance (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Track'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Pad to Track Clearance\" \n"
|
||||
" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n"
|
||||
"\n"
|
||||
" (rule \"Pad to Track Clearance\"\n"
|
||||
" (constraint clearance (min 0.2mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -27290,11 +27287,11 @@ msgid ""
|
|||
" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\" \n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\"\n"
|
||||
" (constraint hole_size (max 6.3mm))\n"
|
||||
" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Max Drill Hole Size PTH\" \n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size PTH\"\n"
|
||||
" (constraint hole_size (max 6.35mm))\n"
|
||||
" (condition \"A.Pad_Type == 'Through-hole'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -27302,7 +27299,7 @@ msgid ""
|
|||
" # Specify an optimal gap for a particular diff-pair\n"
|
||||
" (rule \"dp clock gap\"\n"
|
||||
" (constraint diff_pair_gap (opt \"0.8mm\"))\n"
|
||||
" (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n"
|
||||
" (condition \"A.inDiffPair('/CLK')\"))\n"
|
||||
"\n"
|
||||
" # Specify a larger clearance around any diff-pair\n"
|
||||
" (rule \"dp clearance\"\n"
|
||||
|
|
@ -29726,52 +29723,52 @@ msgstr ""
|
|||
msgid "PCB file changes are unsaved"
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1473
|
||||
#: pcbnew/pcb_edit_frame.cpp:1466
|
||||
msgid "The schematic for this board cannot be found."
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1497
|
||||
#: pcbnew/pcb_edit_frame.cpp:1490
|
||||
msgid ""
|
||||
"Cannot update the PCB because PCB editor is opened in stand-alone mode. In "
|
||||
"order to create or update PCBs from schematics, you must launch the KiCad "
|
||||
"project manager and create a project."
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1519
|
||||
#: pcbnew/pcb_edit_frame.cpp:1512
|
||||
msgid "Eeschema netlist"
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1530
|
||||
#: pcbnew/pcb_edit_frame.cpp:1523
|
||||
msgid ""
|
||||
"Received an error while reading netlist. Please report this issue to the "
|
||||
"KiCad team using the menu Help->Report Bug."
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1557
|
||||
#: pcbnew/pcb_edit_frame.cpp:1550
|
||||
#, c-format
|
||||
msgid "Schematic file '%s' not found."
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1587
|
||||
#: pcbnew/pcb_edit_frame.cpp:1580
|
||||
msgid "Eeschema failed to load."
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1738
|
||||
#: pcbnew/pcb_edit_frame.cpp:1731
|
||||
msgid "Edit design rules"
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1750
|
||||
#: pcbnew/pcb_edit_frame.cpp:1743
|
||||
msgid "Could not compile custom design rules."
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1785
|
||||
#: pcbnew/pcb_edit_frame.cpp:1778
|
||||
msgid "Export Hyperlynx Layout"
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:95 pcbnew/pcb_expr_evaluator.cpp:264
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:330 pcbnew/pcb_expr_evaluator.cpp:396
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:614 pcbnew/pcb_expr_evaluator.cpp:716
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:829
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:824
|
||||
#, c-format
|
||||
msgid "Missing argument to '%s'"
|
||||
msgstr ""
|
||||
|
|
@ -29793,7 +29790,7 @@ msgstr ""
|
|||
msgid "Footprint has no back courtyard."
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1152
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1153
|
||||
msgid "must be mm, in, or mil"
|
||||
msgstr ""
|
||||
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ msgid ""
|
|||
msgstr ""
|
||||
"Project-Id-Version: KiCad\n"
|
||||
"Report-Msgid-Bugs-To: \n"
|
||||
"POT-Creation-Date: 2022-02-14 09:20-0800\n"
|
||||
"POT-Creation-Date: 2022-02-16 17:22-0800\n"
|
||||
"PO-Revision-Date: 2021-10-22 19:22+0000\n"
|
||||
"Last-Translator: CJ van der Hoeven <KeesEnJoa@gmail.com>\n"
|
||||
"Language-Team: Dutch <https://hosted.weblate.org/projects/kicad/master-"
|
||||
|
|
@ -4610,12 +4610,12 @@ msgstr "Alias: "
|
|||
|
||||
#: common/filename_resolver.cpp:468
|
||||
#, fuzzy
|
||||
msgid "This path:wxT( "
|
||||
msgid "This path:"
|
||||
msgstr "Deze weg:"
|
||||
|
||||
#: common/filename_resolver.cpp:471
|
||||
#, fuzzy
|
||||
msgid "Existing path:wxT( "
|
||||
msgid "Existing path:"
|
||||
msgstr "Bestaand pad:"
|
||||
|
||||
#: common/filename_resolver.cpp:473
|
||||
|
|
@ -13416,9 +13416,9 @@ msgstr "Toegewezen Netclass"
|
|||
msgid "Connection Name"
|
||||
msgstr "Verbindingsnaam"
|
||||
|
||||
#: eeschema/sch_connection.cpp:415
|
||||
#, fuzzy
|
||||
msgid "Net CodewxT( "
|
||||
#: eeschema/sch_connection.cpp:415 pcbnew/dialogs/dialog_net_inspector.cpp:76
|
||||
#: pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr "Net Code"
|
||||
|
||||
#: eeschema/sch_connection.cpp:420 eeschema/sch_connection.cpp:433
|
||||
|
|
@ -19202,8 +19202,8 @@ msgid "Application failed to load:\n"
|
|||
msgstr "Applicatie kan niet worden geladen:\n"
|
||||
|
||||
#: kicad/tools/kicad_manager_control.cpp:670
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1558
|
||||
#: pcbnew/pcb_edit_frame.cpp:1588
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1551
|
||||
#: pcbnew/pcb_edit_frame.cpp:1581
|
||||
msgid "KiCad Error"
|
||||
msgstr "KiCad-fout"
|
||||
|
||||
|
|
@ -22268,7 +22268,7 @@ msgstr "Voor-gedefiniëerde afmetingen"
|
|||
|
||||
#: pcbnew/dialogs/dialog_board_setup.cpp:108
|
||||
#: pcbnew/dialogs/dialog_constraints_reporter.cpp:54
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1744
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1737
|
||||
msgid "Custom Rules"
|
||||
msgstr "Aangepaste DRC regels"
|
||||
|
||||
|
|
@ -25334,10 +25334,6 @@ msgstr "Gebruik poolcoördinaten"
|
|||
msgid "Move Item"
|
||||
msgstr "Item verplaatsen"
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:76 pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr "Net Code"
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:77 pcbnew/netinfo_item.cpp:74
|
||||
msgid "Net Name"
|
||||
msgstr "Net Naam"
|
||||
|
|
@ -28953,8 +28949,8 @@ msgid ""
|
|||
" A.inDiffPair('<net_name>')\n"
|
||||
"True if `A` has net that is part of the specified differential pair.\n"
|
||||
"`<net_name>` is the base name of the differential pair. For example, "
|
||||
"`inDiffPair('CLK')`\n"
|
||||
"matches items in the `CLK_P` and `CLK_N` nets.\n"
|
||||
"`inDiffPair('/CLK')`\n"
|
||||
"matches items in the `/CLK_P` and `/CLK_N` nets.\n"
|
||||
"<br><br>\n"
|
||||
"\n"
|
||||
" AB.isCoupledDiffPair()\n"
|
||||
|
|
@ -28994,20 +28990,20 @@ msgid ""
|
|||
" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Distance between Vias of Different Nets\" \n"
|
||||
" (rule \"Distance between Vias of Different Nets\"\n"
|
||||
" (constraint hole_to_hole (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
" (rule \"Clearance between Pads of Different Nets\" \n"
|
||||
" (rule \"Clearance between Pads of Different Nets\"\n"
|
||||
" (constraint clearance (min 3.0mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Via Hole to Track Clearance\" \n"
|
||||
" (rule \"Via Hole to Track Clearance\"\n"
|
||||
" (constraint hole_clearance (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Track'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Pad to Track Clearance\" \n"
|
||||
" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n"
|
||||
"\n"
|
||||
" (rule \"Pad to Track Clearance\"\n"
|
||||
" (constraint clearance (min 0.2mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -29017,11 +29013,11 @@ msgid ""
|
|||
" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\" \n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\"\n"
|
||||
" (constraint hole_size (max 6.3mm))\n"
|
||||
" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Max Drill Hole Size PTH\" \n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size PTH\"\n"
|
||||
" (constraint hole_size (max 6.35mm))\n"
|
||||
" (condition \"A.Pad_Type == 'Through-hole'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -29029,7 +29025,7 @@ msgid ""
|
|||
" # Specify an optimal gap for a particular diff-pair\n"
|
||||
" (rule \"dp clock gap\"\n"
|
||||
" (constraint diff_pair_gap (opt \"0.8mm\"))\n"
|
||||
" (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n"
|
||||
" (condition \"A.inDiffPair('/CLK')\"))\n"
|
||||
"\n"
|
||||
" # Specify a larger clearance around any diff-pair\n"
|
||||
" (rule \"dp clearance\"\n"
|
||||
|
|
@ -31547,11 +31543,11 @@ msgstr "Board-bestand is 'alleen-lezen'."
|
|||
msgid "PCB file changes are unsaved"
|
||||
msgstr "Wijzigingen in PCB-bestanden worden niet opgeslagen"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1473
|
||||
#: pcbnew/pcb_edit_frame.cpp:1466
|
||||
msgid "The schematic for this board cannot be found."
|
||||
msgstr "Het schema voor dit bord is niet gevonden."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1497
|
||||
#: pcbnew/pcb_edit_frame.cpp:1490
|
||||
msgid ""
|
||||
"Cannot update the PCB because PCB editor is opened in stand-alone mode. In "
|
||||
"order to create or update PCBs from schematics, you must launch the KiCad "
|
||||
|
|
@ -31561,11 +31557,11 @@ msgstr ""
|
|||
"PCB's van schema's te maken of bij te werken, moet u de KiCad-project-"
|
||||
"manager starten en een project aanmaken."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1519
|
||||
#: pcbnew/pcb_edit_frame.cpp:1512
|
||||
msgid "Eeschema netlist"
|
||||
msgstr "Eeschema-netlijst"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1530
|
||||
#: pcbnew/pcb_edit_frame.cpp:1523
|
||||
msgid ""
|
||||
"Received an error while reading netlist. Please report this issue to the "
|
||||
"KiCad team using the menu Help->Report Bug."
|
||||
|
|
@ -31573,31 +31569,31 @@ msgstr ""
|
|||
"Fout bij het lezen van de netlist. Rapporteer dit probleem aub aan het "
|
||||
"KiCad team dmv het menu 'Help->Bug rapporteren'."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1557
|
||||
#: pcbnew/pcb_edit_frame.cpp:1550
|
||||
#, c-format
|
||||
msgid "Schematic file '%s' not found."
|
||||
msgstr "Schema-bestand '%s' niet gevonden."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1587
|
||||
#: pcbnew/pcb_edit_frame.cpp:1580
|
||||
msgid "Eeschema failed to load."
|
||||
msgstr "Eeschema kan niet worden geladen."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1738
|
||||
#: pcbnew/pcb_edit_frame.cpp:1731
|
||||
msgid "Edit design rules"
|
||||
msgstr "Ontwerpregels bewerken"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1750
|
||||
#: pcbnew/pcb_edit_frame.cpp:1743
|
||||
msgid "Could not compile custom design rules."
|
||||
msgstr "Kon geen aangepaste ontwerpregels compileren."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1785
|
||||
#: pcbnew/pcb_edit_frame.cpp:1778
|
||||
msgid "Export Hyperlynx Layout"
|
||||
msgstr "Exporteer Hyperlynx Layout"
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:95 pcbnew/pcb_expr_evaluator.cpp:264
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:330 pcbnew/pcb_expr_evaluator.cpp:396
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:614 pcbnew/pcb_expr_evaluator.cpp:716
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:829
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:824
|
||||
#, c-format
|
||||
msgid "Missing argument to '%s'"
|
||||
msgstr "Ontbrekend argument voor '%s'"
|
||||
|
|
@ -31619,7 +31615,7 @@ msgstr "Footprint heeft geen voortuin."
|
|||
msgid "Footprint has no back courtyard."
|
||||
msgstr "Footprint heeft geen achtertuin."
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1152
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1153
|
||||
msgid "must be mm, in, or mil"
|
||||
msgstr "moet mm, in of mil zijn"
|
||||
|
||||
|
|
@ -36860,6 +36856,10 @@ msgstr "KiCad schema"
|
|||
msgid "KiCad Printed Circuit Board"
|
||||
msgstr "KiCad PCB (Printed Circuit Board)"
|
||||
|
||||
#, fuzzy
|
||||
#~ msgid "Net CodewxT( "
|
||||
#~ msgstr "Net Code"
|
||||
|
||||
#~ msgid "Save changes to schematic before closing?"
|
||||
#~ msgstr "Wijzigingen in schema opslaan voordat u afsluit?"
|
||||
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@ msgid ""
|
|||
msgstr ""
|
||||
"Project-Id-Version: 5.99\n"
|
||||
"Report-Msgid-Bugs-To: \n"
|
||||
"POT-Creation-Date: 2022-02-14 09:20-0800\n"
|
||||
"POT-Creation-Date: 2022-02-16 17:22-0800\n"
|
||||
"PO-Revision-Date: 2021-12-12 21:48+0000\n"
|
||||
"Last-Translator: Allan Nordhøy <epost@anotheragency.no>\n"
|
||||
"Language-Team: Norwegian Bokmål <https://hosted.weblate.org/projects/kicad/"
|
||||
|
|
@ -4704,12 +4704,12 @@ msgstr "Kallenavn: "
|
|||
|
||||
#: common/filename_resolver.cpp:468
|
||||
#, fuzzy
|
||||
msgid "This path:wxT( "
|
||||
msgid "This path:"
|
||||
msgstr "Denne veien:"
|
||||
|
||||
#: common/filename_resolver.cpp:471
|
||||
#, fuzzy
|
||||
msgid "Existing path:wxT( "
|
||||
msgid "Existing path:"
|
||||
msgstr "Eksisterende sti:"
|
||||
|
||||
#: common/filename_resolver.cpp:473
|
||||
|
|
@ -13606,9 +13606,9 @@ msgstr "Tildelt Netclass"
|
|||
msgid "Connection Name"
|
||||
msgstr "Oppkoblingsnavn"
|
||||
|
||||
#: eeschema/sch_connection.cpp:415
|
||||
#, fuzzy
|
||||
msgid "Net CodewxT( "
|
||||
#: eeschema/sch_connection.cpp:415 pcbnew/dialogs/dialog_net_inspector.cpp:76
|
||||
#: pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr "Netto kode"
|
||||
|
||||
#: eeschema/sch_connection.cpp:420 eeschema/sch_connection.cpp:433
|
||||
|
|
@ -19516,8 +19516,8 @@ msgid "Application failed to load:\n"
|
|||
msgstr "Appen kunne ikke lastes inn:\n"
|
||||
|
||||
#: kicad/tools/kicad_manager_control.cpp:670
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1558
|
||||
#: pcbnew/pcb_edit_frame.cpp:1588
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1551
|
||||
#: pcbnew/pcb_edit_frame.cpp:1581
|
||||
msgid "KiCad Error"
|
||||
msgstr "KiCad-feil"
|
||||
|
||||
|
|
@ -22683,7 +22683,7 @@ msgstr "Forhåndsdefinerte størrelser:"
|
|||
|
||||
#: pcbnew/dialogs/dialog_board_setup.cpp:108
|
||||
#: pcbnew/dialogs/dialog_constraints_reporter.cpp:54
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1744
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1737
|
||||
#, fuzzy
|
||||
msgid "Custom Rules"
|
||||
msgstr "Egendefinert lagsett"
|
||||
|
|
@ -25773,10 +25773,6 @@ msgstr "Bruk polarkoordinater"
|
|||
msgid "Move Item"
|
||||
msgstr "Flyttet oppføringer"
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:76 pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr "Netto kode"
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:77 pcbnew/netinfo_item.cpp:74
|
||||
msgid "Net Name"
|
||||
msgstr "Netto navn"
|
||||
|
|
@ -29371,8 +29367,8 @@ msgid ""
|
|||
" A.inDiffPair('<net_name>')\n"
|
||||
"True if `A` has net that is part of the specified differential pair.\n"
|
||||
"`<net_name>` is the base name of the differential pair. For example, "
|
||||
"`inDiffPair('CLK')`\n"
|
||||
"matches items in the `CLK_P` and `CLK_N` nets.\n"
|
||||
"`inDiffPair('/CLK')`\n"
|
||||
"matches items in the `/CLK_P` and `/CLK_N` nets.\n"
|
||||
"<br><br>\n"
|
||||
"\n"
|
||||
" AB.isCoupledDiffPair()\n"
|
||||
|
|
@ -29412,20 +29408,20 @@ msgid ""
|
|||
" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Distance between Vias of Different Nets\" \n"
|
||||
" (rule \"Distance between Vias of Different Nets\"\n"
|
||||
" (constraint hole_to_hole (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
" (rule \"Clearance between Pads of Different Nets\" \n"
|
||||
" (rule \"Clearance between Pads of Different Nets\"\n"
|
||||
" (constraint clearance (min 3.0mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Via Hole to Track Clearance\" \n"
|
||||
" (rule \"Via Hole to Track Clearance\"\n"
|
||||
" (constraint hole_clearance (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Track'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Pad to Track Clearance\" \n"
|
||||
" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n"
|
||||
"\n"
|
||||
" (rule \"Pad to Track Clearance\"\n"
|
||||
" (constraint clearance (min 0.2mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -29435,11 +29431,11 @@ msgid ""
|
|||
" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\" \n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\"\n"
|
||||
" (constraint hole_size (max 6.3mm))\n"
|
||||
" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Max Drill Hole Size PTH\" \n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size PTH\"\n"
|
||||
" (constraint hole_size (max 6.35mm))\n"
|
||||
" (condition \"A.Pad_Type == 'Through-hole'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -29447,7 +29443,7 @@ msgid ""
|
|||
" # Specify an optimal gap for a particular diff-pair\n"
|
||||
" (rule \"dp clock gap\"\n"
|
||||
" (constraint diff_pair_gap (opt \"0.8mm\"))\n"
|
||||
" (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n"
|
||||
" (condition \"A.inDiffPair('/CLK')\"))\n"
|
||||
"\n"
|
||||
" # Specify a larger clearance around any diff-pair\n"
|
||||
" (rule \"dp clearance\"\n"
|
||||
|
|
@ -32022,11 +32018,11 @@ msgstr "Bare styreområdet"
|
|||
msgid "PCB file changes are unsaved"
|
||||
msgstr "PCB-filendringer er ikke lagret"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1473
|
||||
#: pcbnew/pcb_edit_frame.cpp:1466
|
||||
msgid "The schematic for this board cannot be found."
|
||||
msgstr "Skjemaet for dette brettet kan ikke bli funnet."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1497
|
||||
#: pcbnew/pcb_edit_frame.cpp:1490
|
||||
#, fuzzy
|
||||
msgid ""
|
||||
"Cannot update the PCB because PCB editor is opened in stand-alone mode. In "
|
||||
|
|
@ -32037,43 +32033,43 @@ msgstr ""
|
|||
"opprette eller oppdatere PCB fra skjemaer, må du starte KiCad-prosjektleder "
|
||||
"og opprette et prosjekt."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1519
|
||||
#: pcbnew/pcb_edit_frame.cpp:1512
|
||||
msgid "Eeschema netlist"
|
||||
msgstr "Eeschema netlist"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1530
|
||||
#: pcbnew/pcb_edit_frame.cpp:1523
|
||||
msgid ""
|
||||
"Received an error while reading netlist. Please report this issue to the "
|
||||
"KiCad team using the menu Help->Report Bug."
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1557
|
||||
#: pcbnew/pcb_edit_frame.cpp:1550
|
||||
#, fuzzy, c-format
|
||||
msgid "Schematic file '%s' not found."
|
||||
msgstr "Skjematisk fil \"%s\" ble ikke funnet."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1587
|
||||
#: pcbnew/pcb_edit_frame.cpp:1580
|
||||
#, fuzzy
|
||||
msgid "Eeschema failed to load."
|
||||
msgstr "Eeschema kunne ikke lastes inn:\n"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1738
|
||||
#: pcbnew/pcb_edit_frame.cpp:1731
|
||||
#, fuzzy
|
||||
msgid "Edit design rules"
|
||||
msgstr "Designregler"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1750
|
||||
#: pcbnew/pcb_edit_frame.cpp:1743
|
||||
msgid "Could not compile custom design rules."
|
||||
msgstr "Kunne ikke kompilere egendefinerte designregler."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1785
|
||||
#: pcbnew/pcb_edit_frame.cpp:1778
|
||||
msgid "Export Hyperlynx Layout"
|
||||
msgstr "Eksporter Hyperlynx Layout"
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:95 pcbnew/pcb_expr_evaluator.cpp:264
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:330 pcbnew/pcb_expr_evaluator.cpp:396
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:614 pcbnew/pcb_expr_evaluator.cpp:716
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:829
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:824
|
||||
#, c-format
|
||||
msgid "Missing argument to '%s'"
|
||||
msgstr "Manglende argument til '%s'"
|
||||
|
|
@ -32095,7 +32091,7 @@ msgstr "Fotavtrykk har ingen gårdsplass."
|
|||
msgid "Footprint has no back courtyard."
|
||||
msgstr "Fotavtrykk har ingen bakgård."
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1152
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1153
|
||||
msgid "must be mm, in, or mil"
|
||||
msgstr "må være mm, in eller mil"
|
||||
|
||||
|
|
@ -37442,6 +37438,10 @@ msgstr "Rediger skjematisk"
|
|||
msgid "KiCad Printed Circuit Board"
|
||||
msgstr "KiCad kretskortfiler"
|
||||
|
||||
#, fuzzy
|
||||
#~ msgid "Net CodewxT( "
|
||||
#~ msgstr "Netto kode"
|
||||
|
||||
#~ msgid "Save changes to schematic before closing?"
|
||||
#~ msgstr "Vil du lagre endringene i skjemaet før du lukker det?"
|
||||
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@ msgid ""
|
|||
msgstr ""
|
||||
"Project-Id-Version: kicad\n"
|
||||
"Report-Msgid-Bugs-To: \n"
|
||||
"POT-Creation-Date: 2022-02-14 09:20-0800\n"
|
||||
"POT-Creation-Date: 2022-02-16 17:22-0800\n"
|
||||
"PO-Revision-Date: 2022-02-16 12:55+0000\n"
|
||||
"Last-Translator: ZbeeGin <zbeegin@op.pl>\n"
|
||||
"Language-Team: Polish <https://hosted.weblate.org/projects/kicad/v6/pl/>\n"
|
||||
|
|
@ -4592,12 +4592,12 @@ msgstr "Alias: "
|
|||
|
||||
#: common/filename_resolver.cpp:468
|
||||
#, fuzzy
|
||||
msgid "This path:wxT( "
|
||||
msgid "This path:"
|
||||
msgstr "Ścieżka obecna:"
|
||||
|
||||
#: common/filename_resolver.cpp:471
|
||||
#, fuzzy
|
||||
msgid "Existing path:wxT( "
|
||||
msgid "Existing path:"
|
||||
msgstr "Istniejąca ścieżka:"
|
||||
|
||||
#: common/filename_resolver.cpp:473
|
||||
|
|
@ -13397,9 +13397,9 @@ msgstr "Przydzielona klasa sieci"
|
|||
msgid "Connection Name"
|
||||
msgstr "Nazwa połączenia"
|
||||
|
||||
#: eeschema/sch_connection.cpp:415
|
||||
#, fuzzy
|
||||
msgid "Net CodewxT( "
|
||||
#: eeschema/sch_connection.cpp:415 pcbnew/dialogs/dialog_net_inspector.cpp:76
|
||||
#: pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr "Kod sieci"
|
||||
|
||||
#: eeschema/sch_connection.cpp:420 eeschema/sch_connection.cpp:433
|
||||
|
|
@ -19166,8 +19166,8 @@ msgid "Application failed to load:\n"
|
|||
msgstr "Aplikacja nie mogła załadować:\n"
|
||||
|
||||
#: kicad/tools/kicad_manager_control.cpp:670
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1558
|
||||
#: pcbnew/pcb_edit_frame.cpp:1588
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1551
|
||||
#: pcbnew/pcb_edit_frame.cpp:1581
|
||||
msgid "KiCad Error"
|
||||
msgstr "Błąd programu KiCad"
|
||||
|
||||
|
|
@ -20751,16 +20751,16 @@ msgstr ""
|
|||
"Wartość kontrolna jest pokazywana jako pogrubiona.\n"
|
||||
"\n"
|
||||
"Obliczenia dotyczą prądów do 35A (zewnętrzne ścieżki) lub 17,5A (wewnętrzne "
|
||||
"ścieżki), przy wzroście temperatury do 100 st. C i szerokości do 400milsów ("
|
||||
"10 mm).\n"
|
||||
"ścieżki), przy wzroście temperatury do 100 st. C i szerokości do 400milsów "
|
||||
"(10 mm).\n"
|
||||
"\n"
|
||||
"Wzór z normy IPC 2221 to\n"
|
||||
"<center>___I = K ⋅ ΔT<sup>0.44</sup> ⋅ (W ⋅ H)<sup>0."
|
||||
"725</sup>___</center>\n"
|
||||
"<center>___I = K ⋅ ΔT<sup>0.44</sup> ⋅ (W ⋅ "
|
||||
"H)<sup>0.725</sup>___</center>\n"
|
||||
"gdzie:<br>\n"
|
||||
"___I___ = maksymalny prąd w amperach<br>\n"
|
||||
"___ΔT___ = wzrost temperatury powyżej temperatury otoczenia w "
|
||||
"°C<br>\n"
|
||||
"___ΔT___ = wzrost temperatury powyżej temperatury otoczenia w °"
|
||||
"C<br>\n"
|
||||
"___W___ = szerokość milsach<br>\n"
|
||||
"___H___ = grubość (wysokość miedzi) w milsach<br>\n"
|
||||
"___K___ = 0.024 dla ścieżek wewnętrznych lub 0.048 dla ścieżek zewnętrznych\n"
|
||||
|
|
@ -22218,7 +22218,7 @@ msgstr "Zdefiniowane rozmiary"
|
|||
|
||||
#: pcbnew/dialogs/dialog_board_setup.cpp:108
|
||||
#: pcbnew/dialogs/dialog_constraints_reporter.cpp:54
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1744
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1737
|
||||
msgid "Custom Rules"
|
||||
msgstr "Reguły użytkownika"
|
||||
|
||||
|
|
@ -25291,10 +25291,6 @@ msgstr "Użyj współrzędnych polarnych"
|
|||
msgid "Move Item"
|
||||
msgstr "Przesuń element"
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:76 pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr "Kod sieci"
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:77 pcbnew/netinfo_item.cpp:74
|
||||
msgid "Net Name"
|
||||
msgstr "Nazwa sieci"
|
||||
|
|
@ -28782,6 +28778,7 @@ msgid "Check rule syntax"
|
|||
msgstr "Sprawdź składnię reguł"
|
||||
|
||||
#: pcbnew/dialogs/panel_setup_rules_help_md.h:2
|
||||
#, fuzzy
|
||||
msgid ""
|
||||
"### Top-level Clauses\n"
|
||||
"\n"
|
||||
|
|
@ -28907,8 +28904,8 @@ msgid ""
|
|||
" A.inDiffPair('<net_name>')\n"
|
||||
"True if `A` has net that is part of the specified differential pair.\n"
|
||||
"`<net_name>` is the base name of the differential pair. For example, "
|
||||
"`inDiffPair('CLK')`\n"
|
||||
"matches items in the `CLK_P` and `CLK_N` nets.\n"
|
||||
"`inDiffPair('/CLK')`\n"
|
||||
"matches items in the `/CLK_P` and `/CLK_N` nets.\n"
|
||||
"<br><br>\n"
|
||||
"\n"
|
||||
" AB.isCoupledDiffPair()\n"
|
||||
|
|
@ -28948,20 +28945,20 @@ msgid ""
|
|||
" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Distance between Vias of Different Nets\" \n"
|
||||
" (rule \"Distance between Vias of Different Nets\"\n"
|
||||
" (constraint hole_to_hole (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
" (rule \"Clearance between Pads of Different Nets\" \n"
|
||||
" (rule \"Clearance between Pads of Different Nets\"\n"
|
||||
" (constraint clearance (min 3.0mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Via Hole to Track Clearance\" \n"
|
||||
" (rule \"Via Hole to Track Clearance\"\n"
|
||||
" (constraint hole_clearance (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Track'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Pad to Track Clearance\" \n"
|
||||
" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n"
|
||||
"\n"
|
||||
" (rule \"Pad to Track Clearance\"\n"
|
||||
" (constraint clearance (min 0.2mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -28971,11 +28968,11 @@ msgid ""
|
|||
" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\" \n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\"\n"
|
||||
" (constraint hole_size (max 6.3mm))\n"
|
||||
" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Max Drill Hole Size PTH\" \n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size PTH\"\n"
|
||||
" (constraint hole_size (max 6.35mm))\n"
|
||||
" (condition \"A.Pad_Type == 'Through-hole'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -28983,7 +28980,7 @@ msgid ""
|
|||
" # Specify an optimal gap for a particular diff-pair\n"
|
||||
" (rule \"dp clock gap\"\n"
|
||||
" (constraint diff_pair_gap (opt \"0.8mm\"))\n"
|
||||
" (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n"
|
||||
" (condition \"A.inDiffPair('/CLK')\"))\n"
|
||||
"\n"
|
||||
" # Specify a larger clearance around any diff-pair\n"
|
||||
" (rule \"dp clearance\"\n"
|
||||
|
|
@ -31705,11 +31702,11 @@ msgstr "Plik z płytką jest tylko do odczytu."
|
|||
msgid "PCB file changes are unsaved"
|
||||
msgstr "Zmiany w pliku PCB nie są zapisane"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1473
|
||||
#: pcbnew/pcb_edit_frame.cpp:1466
|
||||
msgid "The schematic for this board cannot be found."
|
||||
msgstr "Schemat dla tej płytki nie może zostać znaleziony."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1497
|
||||
#: pcbnew/pcb_edit_frame.cpp:1490
|
||||
msgid ""
|
||||
"Cannot update the PCB because PCB editor is opened in stand-alone mode. In "
|
||||
"order to create or update PCBs from schematics, you must launch the KiCad "
|
||||
|
|
@ -31719,11 +31716,11 @@ msgstr ""
|
|||
"samodzielna aplikacja. By utworzyć lub uaktualnić PCB na podstawie schematu "
|
||||
"należy uruchomić Menedżer programu KiCad oraz utworzyć projekt."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1519
|
||||
#: pcbnew/pcb_edit_frame.cpp:1512
|
||||
msgid "Eeschema netlist"
|
||||
msgstr "Lista sieci Eeschema"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1530
|
||||
#: pcbnew/pcb_edit_frame.cpp:1523
|
||||
msgid ""
|
||||
"Received an error while reading netlist. Please report this issue to the "
|
||||
"KiCad team using the menu Help->Report Bug."
|
||||
|
|
@ -31731,31 +31728,31 @@ msgstr ""
|
|||
"Wystąpił błąd podczas odczytywania listy sieci. Proszę zgłosić ten problem "
|
||||
"zespołowi programu KiCad, korzystając z menu Pomoc->Raportuj błąd."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1557
|
||||
#: pcbnew/pcb_edit_frame.cpp:1550
|
||||
#, c-format
|
||||
msgid "Schematic file '%s' not found."
|
||||
msgstr "Plik ze schematem '%s' nie został znaleziony."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1587
|
||||
#: pcbnew/pcb_edit_frame.cpp:1580
|
||||
msgid "Eeschema failed to load."
|
||||
msgstr "Eeschema nie może załadować."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1738
|
||||
#: pcbnew/pcb_edit_frame.cpp:1731
|
||||
msgid "Edit design rules"
|
||||
msgstr "Edycja reguł projektowych"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1750
|
||||
#: pcbnew/pcb_edit_frame.cpp:1743
|
||||
msgid "Could not compile custom design rules."
|
||||
msgstr "Nie można skompilować reguł projektowych."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1785
|
||||
#: pcbnew/pcb_edit_frame.cpp:1778
|
||||
msgid "Export Hyperlynx Layout"
|
||||
msgstr "Eksportuje obwód drukowany dla Hyperlynx"
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:95 pcbnew/pcb_expr_evaluator.cpp:264
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:330 pcbnew/pcb_expr_evaluator.cpp:396
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:614 pcbnew/pcb_expr_evaluator.cpp:716
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:829
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:824
|
||||
#, c-format
|
||||
msgid "Missing argument to '%s'"
|
||||
msgstr "Brakujący argument dla '%s'"
|
||||
|
|
@ -31777,7 +31774,7 @@ msgstr "Footprint nie ma określonego pola zajętości na warstwie górnej."
|
|||
msgid "Footprint has no back courtyard."
|
||||
msgstr "Footprint nie ma określonego pola zajętości na warstwie dolnej."
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1152
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1153
|
||||
msgid "must be mm, in, or mil"
|
||||
msgstr "musi być mm, cal, lub mils"
|
||||
|
||||
|
|
@ -34038,11 +34035,13 @@ msgstr ""
|
|||
|
||||
#: pcbnew/tools/board_editor_control.cpp:1445
|
||||
msgid "Some zone priorities did not match and were not merged."
|
||||
msgstr "Niektóre priorytety stref nie pasowały do siebie i nie zostały scalone."
|
||||
msgstr ""
|
||||
"Niektóre priorytety stref nie pasowały do siebie i nie zostały scalone."
|
||||
|
||||
#: pcbnew/tools/board_editor_control.cpp:1451
|
||||
msgid "Some zones were rule areas and were not merged."
|
||||
msgstr "Niektóre ze stref są strefami z ograniczeniami i nie zostały połączone."
|
||||
msgstr ""
|
||||
"Niektóre ze stref są strefami z ograniczeniami i nie zostały połączone."
|
||||
|
||||
#: pcbnew/tools/board_editor_control.cpp:1457
|
||||
msgid "Some zone layer sets did not match and were not merged."
|
||||
|
|
@ -37021,6 +37020,10 @@ msgstr "Schemat KiCad"
|
|||
msgid "KiCad Printed Circuit Board"
|
||||
msgstr "Obwód drukowany KiCad"
|
||||
|
||||
#, fuzzy
|
||||
#~ msgid "Net CodewxT( "
|
||||
#~ msgstr "Kod sieci"
|
||||
|
||||
#~ msgid "Save changes to schematic before closing?"
|
||||
#~ msgstr "Zapisać zmiany w schemacie przed zamknięciem?"
|
||||
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@ msgid ""
|
|||
msgstr ""
|
||||
"Project-Id-Version: kicad\n"
|
||||
"Report-Msgid-Bugs-To: \n"
|
||||
"POT-Creation-Date: 2022-02-14 09:20-0800\n"
|
||||
"POT-Creation-Date: 2022-02-16 17:22-0800\n"
|
||||
"PO-Revision-Date: 2022-01-03 10:45+0000\n"
|
||||
"Last-Translator: Rafael Silva <perigoso@riseup.net>\n"
|
||||
"Language-Team: Portuguese <https://hosted.weblate.org/projects/kicad/v6/pt/"
|
||||
|
|
@ -4611,12 +4611,12 @@ msgstr "Alias: "
|
|||
|
||||
#: common/filename_resolver.cpp:468
|
||||
#, fuzzy
|
||||
msgid "This path:wxT( "
|
||||
msgid "This path:"
|
||||
msgstr "Este caminho:"
|
||||
|
||||
#: common/filename_resolver.cpp:471
|
||||
#, fuzzy
|
||||
msgid "Existing path:wxT( "
|
||||
msgid "Existing path:"
|
||||
msgstr "Caminho existente:"
|
||||
|
||||
#: common/filename_resolver.cpp:473
|
||||
|
|
@ -13430,9 +13430,9 @@ msgstr "Netclass atribuído"
|
|||
msgid "Connection Name"
|
||||
msgstr "Nome da Conexão"
|
||||
|
||||
#: eeschema/sch_connection.cpp:415
|
||||
#, fuzzy
|
||||
msgid "Net CodewxT( "
|
||||
#: eeschema/sch_connection.cpp:415 pcbnew/dialogs/dialog_net_inspector.cpp:76
|
||||
#: pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr "Código de Rede"
|
||||
|
||||
#: eeschema/sch_connection.cpp:420 eeschema/sch_connection.cpp:433
|
||||
|
|
@ -19216,8 +19216,8 @@ msgid "Application failed to load:\n"
|
|||
msgstr "Falha ao carregar a aplicação:\n"
|
||||
|
||||
#: kicad/tools/kicad_manager_control.cpp:670
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1558
|
||||
#: pcbnew/pcb_edit_frame.cpp:1588
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1551
|
||||
#: pcbnew/pcb_edit_frame.cpp:1581
|
||||
msgid "KiCad Error"
|
||||
msgstr "Erro do KiCad"
|
||||
|
||||
|
|
@ -22274,7 +22274,7 @@ msgstr "Tamanhos pré-definidos"
|
|||
|
||||
#: pcbnew/dialogs/dialog_board_setup.cpp:108
|
||||
#: pcbnew/dialogs/dialog_constraints_reporter.cpp:54
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1744
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1737
|
||||
msgid "Custom Rules"
|
||||
msgstr "Regras personalizadas"
|
||||
|
||||
|
|
@ -25337,10 +25337,6 @@ msgstr "Utilizar coordenadas polares"
|
|||
msgid "Move Item"
|
||||
msgstr "Mover Item"
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:76 pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr "Código de Rede"
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:77 pcbnew/netinfo_item.cpp:74
|
||||
msgid "Net Name"
|
||||
msgstr "Nome da ligação"
|
||||
|
|
@ -28817,6 +28813,7 @@ msgid "Check rule syntax"
|
|||
msgstr "Verifique a sintaxe da regra"
|
||||
|
||||
#: pcbnew/dialogs/panel_setup_rules_help_md.h:2
|
||||
#, fuzzy
|
||||
msgid ""
|
||||
"### Top-level Clauses\n"
|
||||
"\n"
|
||||
|
|
@ -28942,8 +28939,8 @@ msgid ""
|
|||
" A.inDiffPair('<net_name>')\n"
|
||||
"True if `A` has net that is part of the specified differential pair.\n"
|
||||
"`<net_name>` is the base name of the differential pair. For example, "
|
||||
"`inDiffPair('CLK')`\n"
|
||||
"matches items in the `CLK_P` and `CLK_N` nets.\n"
|
||||
"`inDiffPair('/CLK')`\n"
|
||||
"matches items in the `/CLK_P` and `/CLK_N` nets.\n"
|
||||
"<br><br>\n"
|
||||
"\n"
|
||||
" AB.isCoupledDiffPair()\n"
|
||||
|
|
@ -28983,20 +28980,20 @@ msgid ""
|
|||
" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Distance between Vias of Different Nets\" \n"
|
||||
" (rule \"Distance between Vias of Different Nets\"\n"
|
||||
" (constraint hole_to_hole (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
" (rule \"Clearance between Pads of Different Nets\" \n"
|
||||
" (rule \"Clearance between Pads of Different Nets\"\n"
|
||||
" (constraint clearance (min 3.0mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Via Hole to Track Clearance\" \n"
|
||||
" (rule \"Via Hole to Track Clearance\"\n"
|
||||
" (constraint hole_clearance (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Track'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Pad to Track Clearance\" \n"
|
||||
" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n"
|
||||
"\n"
|
||||
" (rule \"Pad to Track Clearance\"\n"
|
||||
" (constraint clearance (min 0.2mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -29006,11 +29003,11 @@ msgid ""
|
|||
" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\" \n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\"\n"
|
||||
" (constraint hole_size (max 6.3mm))\n"
|
||||
" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Max Drill Hole Size PTH\" \n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size PTH\"\n"
|
||||
" (constraint hole_size (max 6.35mm))\n"
|
||||
" (condition \"A.Pad_Type == 'Through-hole'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -29018,7 +29015,7 @@ msgid ""
|
|||
" # Specify an optimal gap for a particular diff-pair\n"
|
||||
" (rule \"dp clock gap\"\n"
|
||||
" (constraint diff_pair_gap (opt \"0.8mm\"))\n"
|
||||
" (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n"
|
||||
" (condition \"A.inDiffPair('/CLK')\"))\n"
|
||||
"\n"
|
||||
" # Specify a larger clearance around any diff-pair\n"
|
||||
" (rule \"dp clearance\"\n"
|
||||
|
|
@ -31752,11 +31749,11 @@ msgstr "O arquivo da placa é somente leitura."
|
|||
msgid "PCB file changes are unsaved"
|
||||
msgstr "As alterações do ficheiro da PCI não foram desfeitas"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1473
|
||||
#: pcbnew/pcb_edit_frame.cpp:1466
|
||||
msgid "The schematic for this board cannot be found."
|
||||
msgstr "O esquema para esta placa não pode ser encontrado."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1497
|
||||
#: pcbnew/pcb_edit_frame.cpp:1490
|
||||
msgid ""
|
||||
"Cannot update the PCB because PCB editor is opened in stand-alone mode. In "
|
||||
"order to create or update PCBs from schematics, you must launch the KiCad "
|
||||
|
|
@ -31766,11 +31763,11 @@ msgstr ""
|
|||
"autônomo. Para criar ou atualizar as PCIs a partir dos esquemas, você deve "
|
||||
"iniciar o gerenciamento do projeto KiCad e criar um projeto."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1519
|
||||
#: pcbnew/pcb_edit_frame.cpp:1512
|
||||
msgid "Eeschema netlist"
|
||||
msgstr "Netlist Eeschema"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1530
|
||||
#: pcbnew/pcb_edit_frame.cpp:1523
|
||||
msgid ""
|
||||
"Received an error while reading netlist. Please report this issue to the "
|
||||
"KiCad team using the menu Help->Report Bug."
|
||||
|
|
@ -31778,31 +31775,31 @@ msgstr ""
|
|||
"Recebi um erro ao ler a netlist. Relate este problema para a equipa KiCad "
|
||||
"usando o menu Ajuda->Relate um problema."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1557
|
||||
#: pcbnew/pcb_edit_frame.cpp:1550
|
||||
#, c-format
|
||||
msgid "Schematic file '%s' not found."
|
||||
msgstr "Arquivo do esquema '%s' não foi encontrado."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1587
|
||||
#: pcbnew/pcb_edit_frame.cpp:1580
|
||||
msgid "Eeschema failed to load."
|
||||
msgstr "Houve uma falha no Eeschema ao carregar."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1738
|
||||
#: pcbnew/pcb_edit_frame.cpp:1731
|
||||
msgid "Edit design rules"
|
||||
msgstr "Edita regras do desenho"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1750
|
||||
#: pcbnew/pcb_edit_frame.cpp:1743
|
||||
msgid "Could not compile custom design rules."
|
||||
msgstr "Não foi possível compilar regras personalizadas do desenho."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1785
|
||||
#: pcbnew/pcb_edit_frame.cpp:1778
|
||||
msgid "Export Hyperlynx Layout"
|
||||
msgstr "Exportar Layout Hyperlynx"
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:95 pcbnew/pcb_expr_evaluator.cpp:264
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:330 pcbnew/pcb_expr_evaluator.cpp:396
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:614 pcbnew/pcb_expr_evaluator.cpp:716
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:829
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:824
|
||||
#, c-format
|
||||
msgid "Missing argument to '%s'"
|
||||
msgstr "Faltando argumento para '%s'"
|
||||
|
|
@ -31824,7 +31821,7 @@ msgstr "O footprint não tem pátio frontal."
|
|||
msgid "Footprint has no back courtyard."
|
||||
msgstr "O footprint não tem pátio atrás."
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1152
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1153
|
||||
msgid "must be mm, in, or mil"
|
||||
msgstr "deve ser mm, pol ou mil"
|
||||
|
||||
|
|
@ -37085,6 +37082,10 @@ msgstr "Esquema KiCad"
|
|||
msgid "KiCad Printed Circuit Board"
|
||||
msgstr "Placa de circuito impresso KiCad"
|
||||
|
||||
#, fuzzy
|
||||
#~ msgid "Net CodewxT( "
|
||||
#~ msgstr "Código de Rede"
|
||||
|
||||
#~ msgid "Save changes to schematic before closing?"
|
||||
#~ msgstr "Salve as alterações no esquema antes de fechar?"
|
||||
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@ msgid ""
|
|||
msgstr ""
|
||||
"Project-Id-Version: kicad\n"
|
||||
"Report-Msgid-Bugs-To: \n"
|
||||
"POT-Creation-Date: 2022-02-14 09:20-0800\n"
|
||||
"POT-Creation-Date: 2022-02-16 17:22-0800\n"
|
||||
"PO-Revision-Date: 2022-02-16 13:03+0000\n"
|
||||
"Last-Translator: Wellington Terumi Uemura <wellingtonuemura@gmail.com>\n"
|
||||
"Language-Team: Portuguese (Brazil) <https://hosted.weblate.org/projects/"
|
||||
|
|
@ -4627,11 +4627,13 @@ msgid "Alias: "
|
|||
msgstr "Alias: "
|
||||
|
||||
#: common/filename_resolver.cpp:468
|
||||
msgid "This path:wxT( "
|
||||
#, fuzzy
|
||||
msgid "This path:"
|
||||
msgstr "Este caminho:wxT( "
|
||||
|
||||
#: common/filename_resolver.cpp:471
|
||||
msgid "Existing path:wxT( "
|
||||
#, fuzzy
|
||||
msgid "Existing path:"
|
||||
msgstr "Caminho existente:wxT( "
|
||||
|
||||
#: common/filename_resolver.cpp:473
|
||||
|
|
@ -13457,9 +13459,10 @@ msgstr "Netclass atribuído"
|
|||
msgid "Connection Name"
|
||||
msgstr "Nome da conexão"
|
||||
|
||||
#: eeschema/sch_connection.cpp:415
|
||||
msgid "Net CodewxT( "
|
||||
msgstr "Rede CodewxT( "
|
||||
#: eeschema/sch_connection.cpp:415 pcbnew/dialogs/dialog_net_inspector.cpp:76
|
||||
#: pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr "Código da rede"
|
||||
|
||||
#: eeschema/sch_connection.cpp:420 eeschema/sch_connection.cpp:433
|
||||
#, c-format
|
||||
|
|
@ -19243,8 +19246,8 @@ msgid "Application failed to load:\n"
|
|||
msgstr "Houve uma falha ao carregar o aplicativo:\n"
|
||||
|
||||
#: kicad/tools/kicad_manager_control.cpp:670
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1558
|
||||
#: pcbnew/pcb_edit_frame.cpp:1588
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1551
|
||||
#: pcbnew/pcb_edit_frame.cpp:1581
|
||||
msgid "KiCad Error"
|
||||
msgstr "Erro do KiCad"
|
||||
|
||||
|
|
@ -22307,7 +22310,7 @@ msgstr "Tamanhos pré-definidos"
|
|||
|
||||
#: pcbnew/dialogs/dialog_board_setup.cpp:108
|
||||
#: pcbnew/dialogs/dialog_constraints_reporter.cpp:54
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1744
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1737
|
||||
msgid "Custom Rules"
|
||||
msgstr "Regras personalizadas"
|
||||
|
||||
|
|
@ -25380,10 +25383,6 @@ msgstr "Utiliza coordenadas polares"
|
|||
msgid "Move Item"
|
||||
msgstr "Move o Item"
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:76 pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr "Código da rede"
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:77 pcbnew/netinfo_item.cpp:74
|
||||
msgid "Net Name"
|
||||
msgstr "Nome da rede"
|
||||
|
|
@ -28861,6 +28860,7 @@ msgid "Check rule syntax"
|
|||
msgstr "Verifique a sintaxe da regra"
|
||||
|
||||
#: pcbnew/dialogs/panel_setup_rules_help_md.h:2
|
||||
#, fuzzy
|
||||
msgid ""
|
||||
"### Top-level Clauses\n"
|
||||
"\n"
|
||||
|
|
@ -28986,8 +28986,8 @@ msgid ""
|
|||
" A.inDiffPair('<net_name>')\n"
|
||||
"True if `A` has net that is part of the specified differential pair.\n"
|
||||
"`<net_name>` is the base name of the differential pair. For example, "
|
||||
"`inDiffPair('CLK')`\n"
|
||||
"matches items in the `CLK_P` and `CLK_N` nets.\n"
|
||||
"`inDiffPair('/CLK')`\n"
|
||||
"matches items in the `/CLK_P` and `/CLK_N` nets.\n"
|
||||
"<br><br>\n"
|
||||
"\n"
|
||||
" AB.isCoupledDiffPair()\n"
|
||||
|
|
@ -29027,20 +29027,20 @@ msgid ""
|
|||
" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Distance between Vias of Different Nets\" \n"
|
||||
" (rule \"Distance between Vias of Different Nets\"\n"
|
||||
" (constraint hole_to_hole (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
" (rule \"Clearance between Pads of Different Nets\" \n"
|
||||
" (rule \"Clearance between Pads of Different Nets\"\n"
|
||||
" (constraint clearance (min 3.0mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Via Hole to Track Clearance\" \n"
|
||||
" (rule \"Via Hole to Track Clearance\"\n"
|
||||
" (constraint hole_clearance (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Track'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Pad to Track Clearance\" \n"
|
||||
" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n"
|
||||
"\n"
|
||||
" (rule \"Pad to Track Clearance\"\n"
|
||||
" (constraint clearance (min 0.2mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -29050,11 +29050,11 @@ msgid ""
|
|||
" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\" \n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\"\n"
|
||||
" (constraint hole_size (max 6.3mm))\n"
|
||||
" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Max Drill Hole Size PTH\" \n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size PTH\"\n"
|
||||
" (constraint hole_size (max 6.35mm))\n"
|
||||
" (condition \"A.Pad_Type == 'Through-hole'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -29062,7 +29062,7 @@ msgid ""
|
|||
" # Specify an optimal gap for a particular diff-pair\n"
|
||||
" (rule \"dp clock gap\"\n"
|
||||
" (constraint diff_pair_gap (opt \"0.8mm\"))\n"
|
||||
" (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n"
|
||||
" (condition \"A.inDiffPair('/CLK')\"))\n"
|
||||
"\n"
|
||||
" # Specify a larger clearance around any diff-pair\n"
|
||||
" (rule \"dp clearance\"\n"
|
||||
|
|
@ -31802,11 +31802,11 @@ msgstr "O arquivo da placa é somente leitura."
|
|||
msgid "PCB file changes are unsaved"
|
||||
msgstr "As alterações do arquivo da PCI não foram desfeitas"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1473
|
||||
#: pcbnew/pcb_edit_frame.cpp:1466
|
||||
msgid "The schematic for this board cannot be found."
|
||||
msgstr "O esquema para esta placa não pode ser encontrado."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1497
|
||||
#: pcbnew/pcb_edit_frame.cpp:1490
|
||||
msgid ""
|
||||
"Cannot update the PCB because PCB editor is opened in stand-alone mode. In "
|
||||
"order to create or update PCBs from schematics, you must launch the KiCad "
|
||||
|
|
@ -31816,11 +31816,11 @@ msgstr ""
|
|||
"autônomo. Para criar ou atualizar as PCIs a partir dos esquemas, você deve "
|
||||
"iniciar o gerenciamento do projeto KiCad e criar um projeto."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1519
|
||||
#: pcbnew/pcb_edit_frame.cpp:1512
|
||||
msgid "Eeschema netlist"
|
||||
msgstr "Netlist Eeschema"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1530
|
||||
#: pcbnew/pcb_edit_frame.cpp:1523
|
||||
msgid ""
|
||||
"Received an error while reading netlist. Please report this issue to the "
|
||||
"KiCad team using the menu Help->Report Bug."
|
||||
|
|
@ -31828,31 +31828,31 @@ msgstr ""
|
|||
"Recebi um erro ao ler a netlist. Relate este problema para a equipe KiCad "
|
||||
"usando o menu Ajuda->Relate um problema."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1557
|
||||
#: pcbnew/pcb_edit_frame.cpp:1550
|
||||
#, c-format
|
||||
msgid "Schematic file '%s' not found."
|
||||
msgstr "Arquivo do esquema '%s' não foi encontrado."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1587
|
||||
#: pcbnew/pcb_edit_frame.cpp:1580
|
||||
msgid "Eeschema failed to load."
|
||||
msgstr "Houve uma falha no Eeschema ao carregar."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1738
|
||||
#: pcbnew/pcb_edit_frame.cpp:1731
|
||||
msgid "Edit design rules"
|
||||
msgstr "Edita regras do desenho"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1750
|
||||
#: pcbnew/pcb_edit_frame.cpp:1743
|
||||
msgid "Could not compile custom design rules."
|
||||
msgstr "Não foi possível compilar regras personalizadas do desenho."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1785
|
||||
#: pcbnew/pcb_edit_frame.cpp:1778
|
||||
msgid "Export Hyperlynx Layout"
|
||||
msgstr "Exporta layout Hyperlynx"
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:95 pcbnew/pcb_expr_evaluator.cpp:264
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:330 pcbnew/pcb_expr_evaluator.cpp:396
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:614 pcbnew/pcb_expr_evaluator.cpp:716
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:829
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:824
|
||||
#, c-format
|
||||
msgid "Missing argument to '%s'"
|
||||
msgstr "Faltando argumento para '%s'"
|
||||
|
|
@ -31874,7 +31874,7 @@ msgstr "O footprint não tem pedaço frontal."
|
|||
msgid "Footprint has no back courtyard."
|
||||
msgstr "O footprint não tem pedaço atrás."
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1152
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1153
|
||||
msgid "must be mm, in, or mil"
|
||||
msgstr "deve ser mm, pol ou mil"
|
||||
|
||||
|
|
@ -37136,6 +37136,9 @@ msgstr "Esquema KiCad"
|
|||
msgid "KiCad Printed Circuit Board"
|
||||
msgstr "Placa de circuito impresso KiCad"
|
||||
|
||||
#~ msgid "Net CodewxT( "
|
||||
#~ msgstr "Rede CodewxT( "
|
||||
|
||||
#~ msgid "Save changes to schematic before closing?"
|
||||
#~ msgstr "Salve as alterações no esquema antes de fechar?"
|
||||
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@ msgid ""
|
|||
msgstr ""
|
||||
"Project-Id-Version: KiCad\n"
|
||||
"Report-Msgid-Bugs-To: \n"
|
||||
"POT-Creation-Date: 2022-02-14 09:20-0800\n"
|
||||
"POT-Creation-Date: 2022-02-16 17:22-0800\n"
|
||||
"PO-Revision-Date: 2021-12-09 16:57+0000\n"
|
||||
"Last-Translator: Adrian Scripcă <benishor@gmail.com>\n"
|
||||
"Language-Team: Romanian <https://hosted.weblate.org/projects/kicad/master-"
|
||||
|
|
@ -4654,12 +4654,12 @@ msgstr "Alias: "
|
|||
|
||||
#: common/filename_resolver.cpp:468
|
||||
#, fuzzy
|
||||
msgid "This path:wxT( "
|
||||
msgid "This path:"
|
||||
msgstr "Această cale:"
|
||||
|
||||
#: common/filename_resolver.cpp:471
|
||||
#, fuzzy
|
||||
msgid "Existing path:wxT( "
|
||||
msgid "Existing path:"
|
||||
msgstr "Calea existentă:"
|
||||
|
||||
#: common/filename_resolver.cpp:473
|
||||
|
|
@ -13303,8 +13303,9 @@ msgstr "Netclass alocat"
|
|||
msgid "Connection Name"
|
||||
msgstr ""
|
||||
|
||||
#: eeschema/sch_connection.cpp:415
|
||||
msgid "Net CodewxT( "
|
||||
#: eeschema/sch_connection.cpp:415 pcbnew/dialogs/dialog_net_inspector.cpp:76
|
||||
#: pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr ""
|
||||
|
||||
#: eeschema/sch_connection.cpp:420 eeschema/sch_connection.cpp:433
|
||||
|
|
@ -18908,8 +18909,8 @@ msgid "Application failed to load:\n"
|
|||
msgstr ""
|
||||
|
||||
#: kicad/tools/kicad_manager_control.cpp:670
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1558
|
||||
#: pcbnew/pcb_edit_frame.cpp:1588
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1551
|
||||
#: pcbnew/pcb_edit_frame.cpp:1581
|
||||
msgid "KiCad Error"
|
||||
msgstr ""
|
||||
|
||||
|
|
@ -21820,7 +21821,7 @@ msgstr ""
|
|||
|
||||
#: pcbnew/dialogs/dialog_board_setup.cpp:108
|
||||
#: pcbnew/dialogs/dialog_constraints_reporter.cpp:54
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1744
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1737
|
||||
msgid "Custom Rules"
|
||||
msgstr ""
|
||||
|
||||
|
|
@ -24742,10 +24743,6 @@ msgstr ""
|
|||
msgid "Move Item"
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:76 pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:77 pcbnew/netinfo_item.cpp:74
|
||||
msgid "Net Name"
|
||||
msgstr ""
|
||||
|
|
@ -28126,8 +28123,8 @@ msgid ""
|
|||
" A.inDiffPair('<net_name>')\n"
|
||||
"True if `A` has net that is part of the specified differential pair.\n"
|
||||
"`<net_name>` is the base name of the differential pair. For example, "
|
||||
"`inDiffPair('CLK')`\n"
|
||||
"matches items in the `CLK_P` and `CLK_N` nets.\n"
|
||||
"`inDiffPair('/CLK')`\n"
|
||||
"matches items in the `/CLK_P` and `/CLK_N` nets.\n"
|
||||
"<br><br>\n"
|
||||
"\n"
|
||||
" AB.isCoupledDiffPair()\n"
|
||||
|
|
@ -28167,20 +28164,20 @@ msgid ""
|
|||
" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Distance between Vias of Different Nets\" \n"
|
||||
" (rule \"Distance between Vias of Different Nets\"\n"
|
||||
" (constraint hole_to_hole (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
" (rule \"Clearance between Pads of Different Nets\" \n"
|
||||
" (rule \"Clearance between Pads of Different Nets\"\n"
|
||||
" (constraint clearance (min 3.0mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Via Hole to Track Clearance\" \n"
|
||||
" (rule \"Via Hole to Track Clearance\"\n"
|
||||
" (constraint hole_clearance (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Track'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Pad to Track Clearance\" \n"
|
||||
" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n"
|
||||
"\n"
|
||||
" (rule \"Pad to Track Clearance\"\n"
|
||||
" (constraint clearance (min 0.2mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -28190,11 +28187,11 @@ msgid ""
|
|||
" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\" \n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\"\n"
|
||||
" (constraint hole_size (max 6.3mm))\n"
|
||||
" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Max Drill Hole Size PTH\" \n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size PTH\"\n"
|
||||
" (constraint hole_size (max 6.35mm))\n"
|
||||
" (condition \"A.Pad_Type == 'Through-hole'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -28202,7 +28199,7 @@ msgid ""
|
|||
" # Specify an optimal gap for a particular diff-pair\n"
|
||||
" (rule \"dp clock gap\"\n"
|
||||
" (constraint diff_pair_gap (opt \"0.8mm\"))\n"
|
||||
" (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n"
|
||||
" (condition \"A.inDiffPair('/CLK')\"))\n"
|
||||
"\n"
|
||||
" # Specify a larger clearance around any diff-pair\n"
|
||||
" (rule \"dp clearance\"\n"
|
||||
|
|
@ -30863,53 +30860,53 @@ msgstr ""
|
|||
msgid "PCB file changes are unsaved"
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1473
|
||||
#: pcbnew/pcb_edit_frame.cpp:1466
|
||||
msgid "The schematic for this board cannot be found."
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1497
|
||||
#: pcbnew/pcb_edit_frame.cpp:1490
|
||||
msgid ""
|
||||
"Cannot update the PCB because PCB editor is opened in stand-alone mode. In "
|
||||
"order to create or update PCBs from schematics, you must launch the KiCad "
|
||||
"project manager and create a project."
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1519
|
||||
#: pcbnew/pcb_edit_frame.cpp:1512
|
||||
msgid "Eeschema netlist"
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1530
|
||||
#: pcbnew/pcb_edit_frame.cpp:1523
|
||||
msgid ""
|
||||
"Received an error while reading netlist. Please report this issue to the "
|
||||
"KiCad team using the menu Help->Report Bug."
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1557
|
||||
#: pcbnew/pcb_edit_frame.cpp:1550
|
||||
#, fuzzy, c-format
|
||||
msgid "Schematic file '%s' not found."
|
||||
msgstr "Fișierul %s nu a fost găsit."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1587
|
||||
#: pcbnew/pcb_edit_frame.cpp:1580
|
||||
#, fuzzy
|
||||
msgid "Eeschema failed to load."
|
||||
msgstr "Nu s-a putut încărca biblioteca kiface \"%s\"."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1738
|
||||
#: pcbnew/pcb_edit_frame.cpp:1731
|
||||
msgid "Edit design rules"
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1750
|
||||
#: pcbnew/pcb_edit_frame.cpp:1743
|
||||
msgid "Could not compile custom design rules."
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1785
|
||||
#: pcbnew/pcb_edit_frame.cpp:1778
|
||||
msgid "Export Hyperlynx Layout"
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:95 pcbnew/pcb_expr_evaluator.cpp:264
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:330 pcbnew/pcb_expr_evaluator.cpp:396
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:614 pcbnew/pcb_expr_evaluator.cpp:716
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:829
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:824
|
||||
#, c-format
|
||||
msgid "Missing argument to '%s'"
|
||||
msgstr ""
|
||||
|
|
@ -30931,7 +30928,7 @@ msgstr ""
|
|||
msgid "Footprint has no back courtyard."
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1152
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1153
|
||||
msgid "must be mm, in, or mil"
|
||||
msgstr ""
|
||||
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@ msgid ""
|
|||
msgstr ""
|
||||
"Project-Id-Version: KiCad\n"
|
||||
"Report-Msgid-Bugs-To: \n"
|
||||
"POT-Creation-Date: 2022-02-14 09:20-0800\n"
|
||||
"POT-Creation-Date: 2022-02-16 17:22-0800\n"
|
||||
"PO-Revision-Date: 2022-02-01 13:58+0000\n"
|
||||
"Last-Translator: dsa-t <dudesuchamazing@gmail.com>\n"
|
||||
"Language-Team: Russian <https://hosted.weblate.org/projects/kicad/v6/ru/>\n"
|
||||
|
|
@ -4615,12 +4615,12 @@ msgstr "Псевдоним: "
|
|||
|
||||
#: common/filename_resolver.cpp:468
|
||||
#, fuzzy
|
||||
msgid "This path:wxT( "
|
||||
msgid "This path:"
|
||||
msgstr "Текущий путь:"
|
||||
|
||||
#: common/filename_resolver.cpp:471
|
||||
#, fuzzy
|
||||
msgid "Existing path:wxT( "
|
||||
msgid "Existing path:"
|
||||
msgstr "Существующий путь:"
|
||||
|
||||
#: common/filename_resolver.cpp:473
|
||||
|
|
@ -13345,9 +13345,9 @@ msgstr "Присвоенный класс цепей"
|
|||
msgid "Connection Name"
|
||||
msgstr "Имя соединения"
|
||||
|
||||
#: eeschema/sch_connection.cpp:415
|
||||
#, fuzzy
|
||||
msgid "Net CodewxT( "
|
||||
#: eeschema/sch_connection.cpp:415 pcbnew/dialogs/dialog_net_inspector.cpp:76
|
||||
#: pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr "Код цепи"
|
||||
|
||||
#: eeschema/sch_connection.cpp:420 eeschema/sch_connection.cpp:433
|
||||
|
|
@ -19071,8 +19071,8 @@ msgid "Application failed to load:\n"
|
|||
msgstr "Не удалось запустить приложение:\n"
|
||||
|
||||
#: kicad/tools/kicad_manager_control.cpp:670
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1558
|
||||
#: pcbnew/pcb_edit_frame.cpp:1588
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1551
|
||||
#: pcbnew/pcb_edit_frame.cpp:1581
|
||||
msgid "KiCad Error"
|
||||
msgstr "Ошибка KiCad"
|
||||
|
||||
|
|
@ -22120,7 +22120,7 @@ msgstr "Пред.установленные размеры"
|
|||
|
||||
#: pcbnew/dialogs/dialog_board_setup.cpp:108
|
||||
#: pcbnew/dialogs/dialog_constraints_reporter.cpp:54
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1744
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1737
|
||||
msgid "Custom Rules"
|
||||
msgstr "Особые правила"
|
||||
|
||||
|
|
@ -25189,10 +25189,6 @@ msgstr "Использовать полярные координаты"
|
|||
msgid "Move Item"
|
||||
msgstr "Переместить элемент"
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:76 pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr "Код цепи"
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:77 pcbnew/netinfo_item.cpp:74
|
||||
msgid "Net Name"
|
||||
msgstr "Имя цепи"
|
||||
|
|
@ -28651,6 +28647,7 @@ msgid "Check rule syntax"
|
|||
msgstr "Проверить синтаксис правил"
|
||||
|
||||
#: pcbnew/dialogs/panel_setup_rules_help_md.h:2
|
||||
#, fuzzy
|
||||
msgid ""
|
||||
"### Top-level Clauses\n"
|
||||
"\n"
|
||||
|
|
@ -28776,8 +28773,8 @@ msgid ""
|
|||
" A.inDiffPair('<net_name>')\n"
|
||||
"True if `A` has net that is part of the specified differential pair.\n"
|
||||
"`<net_name>` is the base name of the differential pair. For example, "
|
||||
"`inDiffPair('CLK')`\n"
|
||||
"matches items in the `CLK_P` and `CLK_N` nets.\n"
|
||||
"`inDiffPair('/CLK')`\n"
|
||||
"matches items in the `/CLK_P` and `/CLK_N` nets.\n"
|
||||
"<br><br>\n"
|
||||
"\n"
|
||||
" AB.isCoupledDiffPair()\n"
|
||||
|
|
@ -28817,20 +28814,20 @@ msgid ""
|
|||
" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Distance between Vias of Different Nets\" \n"
|
||||
" (rule \"Distance between Vias of Different Nets\"\n"
|
||||
" (constraint hole_to_hole (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
" (rule \"Clearance between Pads of Different Nets\" \n"
|
||||
" (rule \"Clearance between Pads of Different Nets\"\n"
|
||||
" (constraint clearance (min 3.0mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Via Hole to Track Clearance\" \n"
|
||||
" (rule \"Via Hole to Track Clearance\"\n"
|
||||
" (constraint hole_clearance (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Track'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Pad to Track Clearance\" \n"
|
||||
" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n"
|
||||
"\n"
|
||||
" (rule \"Pad to Track Clearance\"\n"
|
||||
" (constraint clearance (min 0.2mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -28840,11 +28837,11 @@ msgid ""
|
|||
" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\" \n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\"\n"
|
||||
" (constraint hole_size (max 6.3mm))\n"
|
||||
" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Max Drill Hole Size PTH\" \n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size PTH\"\n"
|
||||
" (constraint hole_size (max 6.35mm))\n"
|
||||
" (condition \"A.Pad_Type == 'Through-hole'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -28852,7 +28849,7 @@ msgid ""
|
|||
" # Specify an optimal gap for a particular diff-pair\n"
|
||||
" (rule \"dp clock gap\"\n"
|
||||
" (constraint diff_pair_gap (opt \"0.8mm\"))\n"
|
||||
" (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n"
|
||||
" (condition \"A.inDiffPair('/CLK')\"))\n"
|
||||
"\n"
|
||||
" # Specify a larger clearance around any diff-pair\n"
|
||||
" (rule \"dp clearance\"\n"
|
||||
|
|
@ -31569,11 +31566,11 @@ msgstr "Файл платы доступен только для чтения."
|
|||
msgid "PCB file changes are unsaved"
|
||||
msgstr "Изменения файла платы не сохранены"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1473
|
||||
#: pcbnew/pcb_edit_frame.cpp:1466
|
||||
msgid "The schematic for this board cannot be found."
|
||||
msgstr "Не удалось найти схему для этой платы."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1497
|
||||
#: pcbnew/pcb_edit_frame.cpp:1490
|
||||
msgid ""
|
||||
"Cannot update the PCB because PCB editor is opened in stand-alone mode. In "
|
||||
"order to create or update PCBs from schematics, you must launch the KiCad "
|
||||
|
|
@ -31583,11 +31580,11 @@ msgstr ""
|
|||
"проектов. Для того чтобы создать или обновить плату из редактора схем, нужно "
|
||||
"запустить менеджер проектов KiCad и создать проект."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1519
|
||||
#: pcbnew/pcb_edit_frame.cpp:1512
|
||||
msgid "Eeschema netlist"
|
||||
msgstr "Список цепей Eeschema"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1530
|
||||
#: pcbnew/pcb_edit_frame.cpp:1523
|
||||
msgid ""
|
||||
"Received an error while reading netlist. Please report this issue to the "
|
||||
"KiCad team using the menu Help->Report Bug."
|
||||
|
|
@ -31595,31 +31592,31 @@ msgstr ""
|
|||
"При считывании списка цепей получена ошибка. Сообщите об этой проблеме "
|
||||
"команду KiCad с помощью меню Справка -> Сообщить об ошибке."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1557
|
||||
#: pcbnew/pcb_edit_frame.cpp:1550
|
||||
#, c-format
|
||||
msgid "Schematic file '%s' not found."
|
||||
msgstr "Файл схемы '%s' не найден."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1587
|
||||
#: pcbnew/pcb_edit_frame.cpp:1580
|
||||
msgid "Eeschema failed to load."
|
||||
msgstr "Не удалось загрузить Eeschema."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1738
|
||||
#: pcbnew/pcb_edit_frame.cpp:1731
|
||||
msgid "Edit design rules"
|
||||
msgstr "Правила проектирования"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1750
|
||||
#: pcbnew/pcb_edit_frame.cpp:1743
|
||||
msgid "Could not compile custom design rules."
|
||||
msgstr "Не удалось скомпилировать особые правила проектирования."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1785
|
||||
#: pcbnew/pcb_edit_frame.cpp:1778
|
||||
msgid "Export Hyperlynx Layout"
|
||||
msgstr "Экспорт макета Hyperlynx"
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:95 pcbnew/pcb_expr_evaluator.cpp:264
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:330 pcbnew/pcb_expr_evaluator.cpp:396
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:614 pcbnew/pcb_expr_evaluator.cpp:716
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:829
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:824
|
||||
#, c-format
|
||||
msgid "Missing argument to '%s'"
|
||||
msgstr "Отсутствует аргумент для '%s'"
|
||||
|
|
@ -31642,7 +31639,7 @@ msgstr "Посад.место не имеет области установки
|
|||
msgid "Footprint has no back courtyard."
|
||||
msgstr "Посад.место не имеет области установки снизу."
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1152
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1153
|
||||
msgid "must be mm, in, or mil"
|
||||
msgstr "должно быть mm, in, или mil"
|
||||
|
||||
|
|
@ -36857,6 +36854,10 @@ msgstr "Схема KiCad"
|
|||
msgid "KiCad Printed Circuit Board"
|
||||
msgstr "Печатная плата KiCad"
|
||||
|
||||
#, fuzzy
|
||||
#~ msgid "Net CodewxT( "
|
||||
#~ msgstr "Код цепи"
|
||||
|
||||
#~ msgid "Save changes to schematic before closing?"
|
||||
#~ msgstr "Сохранить изменения в схеме перед закрытием?"
|
||||
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@ msgid ""
|
|||
msgstr ""
|
||||
"Project-Id-Version: kicad\n"
|
||||
"Report-Msgid-Bugs-To: \n"
|
||||
"POT-Creation-Date: 2022-02-14 09:20-0800\n"
|
||||
"POT-Creation-Date: 2022-02-16 17:22-0800\n"
|
||||
"PO-Revision-Date: 2022-02-01 13:58+0000\n"
|
||||
"Last-Translator: Jakub Janek <shaman.janek@gmail.com>\n"
|
||||
"Language-Team: Slovak <https://hosted.weblate.org/projects/kicad/v6/sk/>\n"
|
||||
|
|
@ -4708,12 +4708,12 @@ msgstr "Alias: "
|
|||
|
||||
#: common/filename_resolver.cpp:468
|
||||
#, fuzzy
|
||||
msgid "This path:wxT( "
|
||||
msgid "This path:"
|
||||
msgstr "Táto cesta:"
|
||||
|
||||
#: common/filename_resolver.cpp:471
|
||||
#, fuzzy
|
||||
msgid "Existing path:wxT( "
|
||||
msgid "Existing path:"
|
||||
msgstr "Existujúca cesta:"
|
||||
|
||||
#: common/filename_resolver.cpp:473
|
||||
|
|
@ -13584,9 +13584,9 @@ msgstr "Priradená trieda spojov"
|
|||
msgid "Connection Name"
|
||||
msgstr "Názov pripojenia"
|
||||
|
||||
#: eeschema/sch_connection.cpp:415
|
||||
#, fuzzy
|
||||
msgid "Net CodewxT( "
|
||||
#: eeschema/sch_connection.cpp:415 pcbnew/dialogs/dialog_net_inspector.cpp:76
|
||||
#: pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr "Kód siete"
|
||||
|
||||
#: eeschema/sch_connection.cpp:420 eeschema/sch_connection.cpp:433
|
||||
|
|
@ -19501,8 +19501,8 @@ msgid "Application failed to load:\n"
|
|||
msgstr "Načítanie aplikácie sa nezdarilo:\n"
|
||||
|
||||
#: kicad/tools/kicad_manager_control.cpp:670
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1558
|
||||
#: pcbnew/pcb_edit_frame.cpp:1588
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1551
|
||||
#: pcbnew/pcb_edit_frame.cpp:1581
|
||||
msgid "KiCad Error"
|
||||
msgstr "Chyba KiCad"
|
||||
|
||||
|
|
@ -22669,7 +22669,7 @@ msgstr "Preddefinované veľkosti:"
|
|||
|
||||
#: pcbnew/dialogs/dialog_board_setup.cpp:108
|
||||
#: pcbnew/dialogs/dialog_constraints_reporter.cpp:54
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1744
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1737
|
||||
#, fuzzy
|
||||
msgid "Custom Rules"
|
||||
msgstr "Sada vlastných vrstiev"
|
||||
|
|
@ -25772,10 +25772,6 @@ msgstr "Použite polárne súradnice"
|
|||
msgid "Move Item"
|
||||
msgstr "Presunúť položku"
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:76 pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr "Kód siete"
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:77 pcbnew/netinfo_item.cpp:74
|
||||
msgid "Net Name"
|
||||
msgstr "Meno siete"
|
||||
|
|
@ -29378,8 +29374,8 @@ msgid ""
|
|||
" A.inDiffPair('<net_name>')\n"
|
||||
"True if `A` has net that is part of the specified differential pair.\n"
|
||||
"`<net_name>` is the base name of the differential pair. For example, "
|
||||
"`inDiffPair('CLK')`\n"
|
||||
"matches items in the `CLK_P` and `CLK_N` nets.\n"
|
||||
"`inDiffPair('/CLK')`\n"
|
||||
"matches items in the `/CLK_P` and `/CLK_N` nets.\n"
|
||||
"<br><br>\n"
|
||||
"\n"
|
||||
" AB.isCoupledDiffPair()\n"
|
||||
|
|
@ -29419,20 +29415,20 @@ msgid ""
|
|||
" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Distance between Vias of Different Nets\" \n"
|
||||
" (rule \"Distance between Vias of Different Nets\"\n"
|
||||
" (constraint hole_to_hole (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
" (rule \"Clearance between Pads of Different Nets\" \n"
|
||||
" (rule \"Clearance between Pads of Different Nets\"\n"
|
||||
" (constraint clearance (min 3.0mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Via Hole to Track Clearance\" \n"
|
||||
" (rule \"Via Hole to Track Clearance\"\n"
|
||||
" (constraint hole_clearance (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Track'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Pad to Track Clearance\" \n"
|
||||
" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n"
|
||||
"\n"
|
||||
" (rule \"Pad to Track Clearance\"\n"
|
||||
" (constraint clearance (min 0.2mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -29442,11 +29438,11 @@ msgid ""
|
|||
" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\" \n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\"\n"
|
||||
" (constraint hole_size (max 6.3mm))\n"
|
||||
" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Max Drill Hole Size PTH\" \n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size PTH\"\n"
|
||||
" (constraint hole_size (max 6.35mm))\n"
|
||||
" (condition \"A.Pad_Type == 'Through-hole'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -29454,7 +29450,7 @@ msgid ""
|
|||
" # Specify an optimal gap for a particular diff-pair\n"
|
||||
" (rule \"dp clock gap\"\n"
|
||||
" (constraint diff_pair_gap (opt \"0.8mm\"))\n"
|
||||
" (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n"
|
||||
" (condition \"A.inDiffPair('/CLK')\"))\n"
|
||||
"\n"
|
||||
" # Specify a larger clearance around any diff-pair\n"
|
||||
" (rule \"dp clearance\"\n"
|
||||
|
|
@ -32032,11 +32028,11 @@ msgstr "Iba plocha na palube"
|
|||
msgid "PCB file changes are unsaved"
|
||||
msgstr "Zmeny súborov PCB sa neuložia"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1473
|
||||
#: pcbnew/pcb_edit_frame.cpp:1466
|
||||
msgid "The schematic for this board cannot be found."
|
||||
msgstr "Schéma pre túto dosku sa nenašla."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1497
|
||||
#: pcbnew/pcb_edit_frame.cpp:1490
|
||||
#, fuzzy
|
||||
msgid ""
|
||||
"Cannot update the PCB because PCB editor is opened in stand-alone mode. In "
|
||||
|
|
@ -32047,43 +32043,43 @@ msgstr ""
|
|||
"samostatnom režime. Ak chcete vytvoriť alebo aktualizovať PCB zo schém, "
|
||||
"musíte spustiť projektového manažéra KiCad a vytvoriť projekt."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1519
|
||||
#: pcbnew/pcb_edit_frame.cpp:1512
|
||||
msgid "Eeschema netlist"
|
||||
msgstr "Netlist systému Eeschema"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1530
|
||||
#: pcbnew/pcb_edit_frame.cpp:1523
|
||||
msgid ""
|
||||
"Received an error while reading netlist. Please report this issue to the "
|
||||
"KiCad team using the menu Help->Report Bug."
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1557
|
||||
#: pcbnew/pcb_edit_frame.cpp:1550
|
||||
#, fuzzy, c-format
|
||||
msgid "Schematic file '%s' not found."
|
||||
msgstr "Schematický súbor „%s“ sa nenašiel."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1587
|
||||
#: pcbnew/pcb_edit_frame.cpp:1580
|
||||
#, fuzzy
|
||||
msgid "Eeschema failed to load."
|
||||
msgstr "Eeschema sa nepodarilo načítať:\n"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1738
|
||||
#: pcbnew/pcb_edit_frame.cpp:1731
|
||||
#, fuzzy
|
||||
msgid "Edit design rules"
|
||||
msgstr "Pravidlá návrhu"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1750
|
||||
#: pcbnew/pcb_edit_frame.cpp:1743
|
||||
msgid "Could not compile custom design rules."
|
||||
msgstr "Neporadilo sa zostaviť vlastné pravidlá návrhu."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1785
|
||||
#: pcbnew/pcb_edit_frame.cpp:1778
|
||||
msgid "Export Hyperlynx Layout"
|
||||
msgstr "Exportovať rozloženie Hyperlynx"
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:95 pcbnew/pcb_expr_evaluator.cpp:264
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:330 pcbnew/pcb_expr_evaluator.cpp:396
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:614 pcbnew/pcb_expr_evaluator.cpp:716
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:829
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:824
|
||||
#, c-format
|
||||
msgid "Missing argument to '%s'"
|
||||
msgstr "Chýbajúci argument pre „%s“"
|
||||
|
|
@ -32105,7 +32101,7 @@ msgstr "Stopa nemá predné nádvorie."
|
|||
msgid "Footprint has no back courtyard."
|
||||
msgstr "Stopa nemá zadné nádvorie."
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1152
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1153
|
||||
msgid "must be mm, in, or mil"
|
||||
msgstr "musia byť mm, in alebo mil"
|
||||
|
||||
|
|
@ -37435,6 +37431,10 @@ msgstr "Upraviť schému"
|
|||
msgid "KiCad Printed Circuit Board"
|
||||
msgstr "&Navrhnúť dosku plošného spoja"
|
||||
|
||||
#, fuzzy
|
||||
#~ msgid "Net CodewxT( "
|
||||
#~ msgstr "Kód siete"
|
||||
|
||||
#~ msgid "Save changes to schematic before closing?"
|
||||
#~ msgstr "Uložiť zmeny do schémy pred zatvorením?"
|
||||
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@ msgid ""
|
|||
msgstr ""
|
||||
"Project-Id-Version: kicad\n"
|
||||
"Report-Msgid-Bugs-To: \n"
|
||||
"POT-Creation-Date: 2022-02-14 09:20-0800\n"
|
||||
"POT-Creation-Date: 2022-02-16 17:22-0800\n"
|
||||
"PO-Revision-Date: 2022-02-01 13:58+0000\n"
|
||||
"Last-Translator: Dejan Smole <dejko1@hotmail.com>\n"
|
||||
"Language-Team: Slovenian <https://hosted.weblate.org/projects/kicad/v6/sl/>\n"
|
||||
|
|
@ -4686,12 +4686,12 @@ msgstr "Vzdevek: "
|
|||
|
||||
#: common/filename_resolver.cpp:468
|
||||
#, fuzzy
|
||||
msgid "This path:wxT( "
|
||||
msgid "This path:"
|
||||
msgstr "Ta pot:"
|
||||
|
||||
#: common/filename_resolver.cpp:471
|
||||
#, fuzzy
|
||||
msgid "Existing path:wxT( "
|
||||
msgid "Existing path:"
|
||||
msgstr "Obstoječa pot:"
|
||||
|
||||
#: common/filename_resolver.cpp:473
|
||||
|
|
@ -13547,9 +13547,9 @@ msgstr "Dodeljeni Netclass"
|
|||
msgid "Connection Name"
|
||||
msgstr "Ime povezave"
|
||||
|
||||
#: eeschema/sch_connection.cpp:415
|
||||
#, fuzzy
|
||||
msgid "Net CodewxT( "
|
||||
#: eeschema/sch_connection.cpp:415 pcbnew/dialogs/dialog_net_inspector.cpp:76
|
||||
#: pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr "Oznaka vezi"
|
||||
|
||||
#: eeschema/sch_connection.cpp:420 eeschema/sch_connection.cpp:433
|
||||
|
|
@ -19472,8 +19472,8 @@ msgid "Application failed to load:\n"
|
|||
msgstr "Aplikacije ni bilo mogoče naložiti:\n"
|
||||
|
||||
#: kicad/tools/kicad_manager_control.cpp:670
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1558
|
||||
#: pcbnew/pcb_edit_frame.cpp:1588
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1551
|
||||
#: pcbnew/pcb_edit_frame.cpp:1581
|
||||
msgid "KiCad Error"
|
||||
msgstr "Napaka KiCad"
|
||||
|
||||
|
|
@ -22638,7 +22638,7 @@ msgstr "Vnaprej določene velikosti:"
|
|||
|
||||
#: pcbnew/dialogs/dialog_board_setup.cpp:108
|
||||
#: pcbnew/dialogs/dialog_constraints_reporter.cpp:54
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1744
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1737
|
||||
#, fuzzy
|
||||
msgid "Custom Rules"
|
||||
msgstr "Nabor slojev po meri"
|
||||
|
|
@ -25736,10 +25736,6 @@ msgstr "Uporabite polarne koordinate"
|
|||
msgid "Move Item"
|
||||
msgstr "Premakni element"
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:76 pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr "Oznaka vezi"
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:77 pcbnew/netinfo_item.cpp:74
|
||||
msgid "Net Name"
|
||||
msgstr "Oznaka vezi"
|
||||
|
|
@ -29330,8 +29326,8 @@ msgid ""
|
|||
" A.inDiffPair('<net_name>')\n"
|
||||
"True if `A` has net that is part of the specified differential pair.\n"
|
||||
"`<net_name>` is the base name of the differential pair. For example, "
|
||||
"`inDiffPair('CLK')`\n"
|
||||
"matches items in the `CLK_P` and `CLK_N` nets.\n"
|
||||
"`inDiffPair('/CLK')`\n"
|
||||
"matches items in the `/CLK_P` and `/CLK_N` nets.\n"
|
||||
"<br><br>\n"
|
||||
"\n"
|
||||
" AB.isCoupledDiffPair()\n"
|
||||
|
|
@ -29371,20 +29367,20 @@ msgid ""
|
|||
" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Distance between Vias of Different Nets\" \n"
|
||||
" (rule \"Distance between Vias of Different Nets\"\n"
|
||||
" (constraint hole_to_hole (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
" (rule \"Clearance between Pads of Different Nets\" \n"
|
||||
" (rule \"Clearance between Pads of Different Nets\"\n"
|
||||
" (constraint clearance (min 3.0mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Via Hole to Track Clearance\" \n"
|
||||
" (rule \"Via Hole to Track Clearance\"\n"
|
||||
" (constraint hole_clearance (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Track'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Pad to Track Clearance\" \n"
|
||||
" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n"
|
||||
"\n"
|
||||
" (rule \"Pad to Track Clearance\"\n"
|
||||
" (constraint clearance (min 0.2mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -29394,11 +29390,11 @@ msgid ""
|
|||
" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\" \n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\"\n"
|
||||
" (constraint hole_size (max 6.3mm))\n"
|
||||
" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Max Drill Hole Size PTH\" \n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size PTH\"\n"
|
||||
" (constraint hole_size (max 6.35mm))\n"
|
||||
" (condition \"A.Pad_Type == 'Through-hole'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -29406,7 +29402,7 @@ msgid ""
|
|||
" # Specify an optimal gap for a particular diff-pair\n"
|
||||
" (rule \"dp clock gap\"\n"
|
||||
" (constraint diff_pair_gap (opt \"0.8mm\"))\n"
|
||||
" (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n"
|
||||
" (condition \"A.inDiffPair('/CLK')\"))\n"
|
||||
"\n"
|
||||
" # Specify a larger clearance around any diff-pair\n"
|
||||
" (rule \"dp clearance\"\n"
|
||||
|
|
@ -31982,11 +31978,11 @@ msgstr "Samo območje plošče"
|
|||
msgid "PCB file changes are unsaved"
|
||||
msgstr "Spremembe datotek PCB niso shranjene"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1473
|
||||
#: pcbnew/pcb_edit_frame.cpp:1466
|
||||
msgid "The schematic for this board cannot be found."
|
||||
msgstr "Sheme za to ploščo ni mogoče najti."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1497
|
||||
#: pcbnew/pcb_edit_frame.cpp:1490
|
||||
#, fuzzy
|
||||
msgid ""
|
||||
"Cannot update the PCB because PCB editor is opened in stand-alone mode. In "
|
||||
|
|
@ -31997,44 +31993,44 @@ msgstr ""
|
|||
"želite iz shem ustvariti ali posodobiti PCB, morate zagnati vodjo projekta "
|
||||
"KiCad in ustvariti projekt."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1519
|
||||
#: pcbnew/pcb_edit_frame.cpp:1512
|
||||
msgid "Eeschema netlist"
|
||||
msgstr "Eeschema netlist"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1530
|
||||
#: pcbnew/pcb_edit_frame.cpp:1523
|
||||
msgid ""
|
||||
"Received an error while reading netlist. Please report this issue to the "
|
||||
"KiCad team using the menu Help->Report Bug."
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1557
|
||||
#: pcbnew/pcb_edit_frame.cpp:1550
|
||||
#, fuzzy, c-format
|
||||
msgid "Schematic file '%s' not found."
|
||||
msgstr "Shematske datoteke \"%s\" ni mogoče najti."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1587
|
||||
#: pcbnew/pcb_edit_frame.cpp:1580
|
||||
#, fuzzy
|
||||
msgid "Eeschema failed to load."
|
||||
msgstr "Eescheme ni uspelo naložiti:\n"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1738
|
||||
#: pcbnew/pcb_edit_frame.cpp:1731
|
||||
#, fuzzy
|
||||
msgid "Edit design rules"
|
||||
msgstr "Pravila oblikovanja"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1750
|
||||
#: pcbnew/pcb_edit_frame.cpp:1743
|
||||
#, fuzzy
|
||||
msgid "Could not compile custom design rules."
|
||||
msgstr "DRK nepopoln: pravil oblikovanja ni bilo mogoče sestaviti. "
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1785
|
||||
#: pcbnew/pcb_edit_frame.cpp:1778
|
||||
msgid "Export Hyperlynx Layout"
|
||||
msgstr "Izvozi postavitev Hyperlynx"
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:95 pcbnew/pcb_expr_evaluator.cpp:264
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:330 pcbnew/pcb_expr_evaluator.cpp:396
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:614 pcbnew/pcb_expr_evaluator.cpp:716
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:829
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:824
|
||||
#, c-format
|
||||
msgid "Missing argument to '%s'"
|
||||
msgstr "Manjkajoči argument za '%s'"
|
||||
|
|
@ -32056,7 +32052,7 @@ msgstr "Footprint nima sprednjega dvorišča."
|
|||
msgid "Footprint has no back courtyard."
|
||||
msgstr "Footprint nima zadnjega dvorišča."
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1152
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1153
|
||||
msgid "must be mm, in, or mil"
|
||||
msgstr "mora biti mm, in ali mil"
|
||||
|
||||
|
|
@ -37380,6 +37376,10 @@ msgstr "Uredi shemo"
|
|||
msgid "KiCad Printed Circuit Board"
|
||||
msgstr "Datoteke tiskanih vezij KiCad"
|
||||
|
||||
#, fuzzy
|
||||
#~ msgid "Net CodewxT( "
|
||||
#~ msgstr "Oznaka vezi"
|
||||
|
||||
#~ msgid "Save changes to schematic before closing?"
|
||||
#~ msgstr "Ali želite shraniti spremembe v shemo, preden zaprete?"
|
||||
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@ msgid ""
|
|||
msgstr ""
|
||||
"Project-Id-Version: KiCad\n"
|
||||
"Report-Msgid-Bugs-To: \n"
|
||||
"POT-Creation-Date: 2022-02-14 09:20-0800\n"
|
||||
"POT-Creation-Date: 2022-02-16 17:22-0800\n"
|
||||
"PO-Revision-Date: 2021-11-05 13:01+0000\n"
|
||||
"Last-Translator: ___davidpr <david.pribic95@gmail.com>\n"
|
||||
"Language-Team: Serbian <https://hosted.weblate.org/projects/kicad/master-"
|
||||
|
|
@ -4661,12 +4661,12 @@ msgstr ""
|
|||
|
||||
#: common/filename_resolver.cpp:468
|
||||
#, fuzzy
|
||||
msgid "This path:wxT( "
|
||||
msgid "This path:"
|
||||
msgstr "Претражи путање:"
|
||||
|
||||
#: common/filename_resolver.cpp:471
|
||||
#, fuzzy
|
||||
msgid "Existing path:wxT( "
|
||||
msgid "Existing path:"
|
||||
msgstr "Постојећа путања:"
|
||||
|
||||
#: common/filename_resolver.cpp:473
|
||||
|
|
@ -13461,8 +13461,9 @@ msgstr ""
|
|||
msgid "Connection Name"
|
||||
msgstr "Име конекције"
|
||||
|
||||
#: eeschema/sch_connection.cpp:415
|
||||
msgid "Net CodewxT( "
|
||||
#: eeschema/sch_connection.cpp:415 pcbnew/dialogs/dialog_net_inspector.cpp:76
|
||||
#: pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr ""
|
||||
|
||||
#: eeschema/sch_connection.cpp:420 eeschema/sch_connection.cpp:433
|
||||
|
|
@ -19255,8 +19256,8 @@ msgid "Application failed to load:\n"
|
|||
msgstr ""
|
||||
|
||||
#: kicad/tools/kicad_manager_control.cpp:670
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1558
|
||||
#: pcbnew/pcb_edit_frame.cpp:1588
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1551
|
||||
#: pcbnew/pcb_edit_frame.cpp:1581
|
||||
msgid "KiCad Error"
|
||||
msgstr "KiCad грешка"
|
||||
|
||||
|
|
@ -22331,7 +22332,7 @@ msgstr "Додај поље"
|
|||
|
||||
#: pcbnew/dialogs/dialog_board_setup.cpp:108
|
||||
#: pcbnew/dialogs/dialog_constraints_reporter.cpp:54
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1744
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1737
|
||||
#, fuzzy
|
||||
msgid "Custom Rules"
|
||||
msgstr "Изабери језик"
|
||||
|
|
@ -25430,10 +25431,6 @@ msgstr ""
|
|||
msgid "Move Item"
|
||||
msgstr "Помјери"
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:76 pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:77 pcbnew/netinfo_item.cpp:74
|
||||
msgid "Net Name"
|
||||
msgstr "Име мреже"
|
||||
|
|
@ -28939,8 +28936,8 @@ msgid ""
|
|||
" A.inDiffPair('<net_name>')\n"
|
||||
"True if `A` has net that is part of the specified differential pair.\n"
|
||||
"`<net_name>` is the base name of the differential pair. For example, "
|
||||
"`inDiffPair('CLK')`\n"
|
||||
"matches items in the `CLK_P` and `CLK_N` nets.\n"
|
||||
"`inDiffPair('/CLK')`\n"
|
||||
"matches items in the `/CLK_P` and `/CLK_N` nets.\n"
|
||||
"<br><br>\n"
|
||||
"\n"
|
||||
" AB.isCoupledDiffPair()\n"
|
||||
|
|
@ -28980,20 +28977,20 @@ msgid ""
|
|||
" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Distance between Vias of Different Nets\" \n"
|
||||
" (rule \"Distance between Vias of Different Nets\"\n"
|
||||
" (constraint hole_to_hole (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
" (rule \"Clearance between Pads of Different Nets\" \n"
|
||||
" (rule \"Clearance between Pads of Different Nets\"\n"
|
||||
" (constraint clearance (min 3.0mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Via Hole to Track Clearance\" \n"
|
||||
" (rule \"Via Hole to Track Clearance\"\n"
|
||||
" (constraint hole_clearance (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Track'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Pad to Track Clearance\" \n"
|
||||
" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n"
|
||||
"\n"
|
||||
" (rule \"Pad to Track Clearance\"\n"
|
||||
" (constraint clearance (min 0.2mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -29003,11 +29000,11 @@ msgid ""
|
|||
" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\" \n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\"\n"
|
||||
" (constraint hole_size (max 6.3mm))\n"
|
||||
" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Max Drill Hole Size PTH\" \n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size PTH\"\n"
|
||||
" (constraint hole_size (max 6.35mm))\n"
|
||||
" (condition \"A.Pad_Type == 'Through-hole'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -29015,7 +29012,7 @@ msgid ""
|
|||
" # Specify an optimal gap for a particular diff-pair\n"
|
||||
" (rule \"dp clock gap\"\n"
|
||||
" (constraint diff_pair_gap (opt \"0.8mm\"))\n"
|
||||
" (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n"
|
||||
" (condition \"A.inDiffPair('/CLK')\"))\n"
|
||||
"\n"
|
||||
" # Specify a larger clearance around any diff-pair\n"
|
||||
" (rule \"dp clearance\"\n"
|
||||
|
|
@ -31598,54 +31595,54 @@ msgstr "фајл не постоји"
|
|||
msgid "PCB file changes are unsaved"
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1473
|
||||
#: pcbnew/pcb_edit_frame.cpp:1466
|
||||
msgid "The schematic for this board cannot be found."
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1497
|
||||
#: pcbnew/pcb_edit_frame.cpp:1490
|
||||
msgid ""
|
||||
"Cannot update the PCB because PCB editor is opened in stand-alone mode. In "
|
||||
"order to create or update PCBs from schematics, you must launch the KiCad "
|
||||
"project manager and create a project."
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1519
|
||||
#: pcbnew/pcb_edit_frame.cpp:1512
|
||||
msgid "Eeschema netlist"
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1530
|
||||
#: pcbnew/pcb_edit_frame.cpp:1523
|
||||
msgid ""
|
||||
"Received an error while reading netlist. Please report this issue to the "
|
||||
"KiCad team using the menu Help->Report Bug."
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1557
|
||||
#: pcbnew/pcb_edit_frame.cpp:1550
|
||||
#, fuzzy, c-format
|
||||
msgid "Schematic file '%s' not found."
|
||||
msgstr "Фајл '%s' није пронађен."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1587
|
||||
#: pcbnew/pcb_edit_frame.cpp:1580
|
||||
#, fuzzy
|
||||
msgid "Eeschema failed to load."
|
||||
msgstr "Попуњавање зона"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1738
|
||||
#: pcbnew/pcb_edit_frame.cpp:1731
|
||||
#, fuzzy
|
||||
msgid "Edit design rules"
|
||||
msgstr "Дизајн"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1750
|
||||
#: pcbnew/pcb_edit_frame.cpp:1743
|
||||
msgid "Could not compile custom design rules."
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1785
|
||||
#: pcbnew/pcb_edit_frame.cpp:1778
|
||||
msgid "Export Hyperlynx Layout"
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:95 pcbnew/pcb_expr_evaluator.cpp:264
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:330 pcbnew/pcb_expr_evaluator.cpp:396
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:614 pcbnew/pcb_expr_evaluator.cpp:716
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:829
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:824
|
||||
#, c-format
|
||||
msgid "Missing argument to '%s'"
|
||||
msgstr ""
|
||||
|
|
@ -31669,7 +31666,7 @@ msgstr "Попуњавање зона"
|
|||
msgid "Footprint has no back courtyard."
|
||||
msgstr "Попуњавање зона"
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1152
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1153
|
||||
msgid "must be mm, in, or mil"
|
||||
msgstr ""
|
||||
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ msgid ""
|
|||
msgstr ""
|
||||
"Project-Id-Version: \n"
|
||||
"Report-Msgid-Bugs-To: \n"
|
||||
"POT-Creation-Date: 2022-02-14 09:20-0800\n"
|
||||
"POT-Creation-Date: 2022-02-16 17:22-0800\n"
|
||||
"PO-Revision-Date: 2022-02-17 01:22+0000\n"
|
||||
"Last-Translator: Henrik Kauhanen <henrik@kauhanen.se>\n"
|
||||
"Language-Team: Swedish <https://hosted.weblate.org/projects/kicad/v6/sv/>\n"
|
||||
|
|
@ -4585,12 +4585,12 @@ msgstr "Alias: "
|
|||
|
||||
#: common/filename_resolver.cpp:468
|
||||
#, fuzzy
|
||||
msgid "This path:wxT( "
|
||||
msgid "This path:"
|
||||
msgstr "Denna sökväg:"
|
||||
|
||||
#: common/filename_resolver.cpp:471
|
||||
#, fuzzy
|
||||
msgid "Existing path:wxT( "
|
||||
msgid "Existing path:"
|
||||
msgstr "Befintlig sökväg:"
|
||||
|
||||
#: common/filename_resolver.cpp:473
|
||||
|
|
@ -13332,9 +13332,9 @@ msgstr "Tilldelad Netclass"
|
|||
msgid "Connection Name"
|
||||
msgstr "Anslutningens namn"
|
||||
|
||||
#: eeschema/sch_connection.cpp:415
|
||||
#, fuzzy
|
||||
msgid "Net CodewxT( "
|
||||
#: eeschema/sch_connection.cpp:415 pcbnew/dialogs/dialog_net_inspector.cpp:76
|
||||
#: pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr "Nettokod"
|
||||
|
||||
#: eeschema/sch_connection.cpp:420 eeschema/sch_connection.cpp:433
|
||||
|
|
@ -19065,8 +19065,8 @@ msgid "Application failed to load:\n"
|
|||
msgstr "Programmet kunde inte laddas:\n"
|
||||
|
||||
#: kicad/tools/kicad_manager_control.cpp:670
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1558
|
||||
#: pcbnew/pcb_edit_frame.cpp:1588
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1551
|
||||
#: pcbnew/pcb_edit_frame.cpp:1581
|
||||
msgid "KiCad Error"
|
||||
msgstr "KiCad-fel"
|
||||
|
||||
|
|
@ -22107,7 +22107,7 @@ msgstr "Fördefinierade storlekar"
|
|||
|
||||
#: pcbnew/dialogs/dialog_board_setup.cpp:108
|
||||
#: pcbnew/dialogs/dialog_constraints_reporter.cpp:54
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1744
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1737
|
||||
msgid "Custom Rules"
|
||||
msgstr "Anpassade regler"
|
||||
|
||||
|
|
@ -25152,10 +25152,6 @@ msgstr "Använd polära koordinater"
|
|||
msgid "Move Item"
|
||||
msgstr "Flytta objekt"
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:76 pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr "Nettokod"
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:77 pcbnew/netinfo_item.cpp:74
|
||||
msgid "Net Name"
|
||||
msgstr "Nätnamn"
|
||||
|
|
@ -28532,8 +28528,8 @@ msgid ""
|
|||
"Final clearance value is the sum of this value and the clearance value ratio."
|
||||
msgstr ""
|
||||
"Globalt spelrum mellan lödytor och lödpasta.\n"
|
||||
"Detta värde kan ersättas av lokala värden för ett fotavtryck eller en lödyta."
|
||||
"\n"
|
||||
"Detta värde kan ersättas av lokala värden för ett fotavtryck eller en "
|
||||
"lödyta.\n"
|
||||
"Slutligt värde är summan av detta värde och avståndsförhållandet."
|
||||
|
||||
#: pcbnew/dialogs/panel_setup_mask_and_paste_base.cpp:100
|
||||
|
|
@ -28554,8 +28550,8 @@ msgid ""
|
|||
msgstr ""
|
||||
"Globalt marginalförhållande i procent mellan lödyta och lödpasta.\n"
|
||||
"Ett värde på 10 betyder att marginalen är 10 procent av lödytans storlek.\n"
|
||||
"Detta värde kan ersättas av lokala värden för ett fotavtryck eller en lödyta."
|
||||
"\n"
|
||||
"Detta värde kan ersättas av lokala värden för ett fotavtryck eller en "
|
||||
"lödyta.\n"
|
||||
"Slutlig marginal är summan av detta värde och marginalvärdet."
|
||||
|
||||
#: pcbnew/dialogs/panel_setup_mask_and_paste_base.cpp:115
|
||||
|
|
@ -28721,8 +28717,8 @@ msgid ""
|
|||
" A.inDiffPair('<net_name>')\n"
|
||||
"True if `A` has net that is part of the specified differential pair.\n"
|
||||
"`<net_name>` is the base name of the differential pair. For example, "
|
||||
"`inDiffPair('CLK')`\n"
|
||||
"matches items in the `CLK_P` and `CLK_N` nets.\n"
|
||||
"`inDiffPair('/CLK')`\n"
|
||||
"matches items in the `/CLK_P` and `/CLK_N` nets.\n"
|
||||
"<br><br>\n"
|
||||
"\n"
|
||||
" AB.isCoupledDiffPair()\n"
|
||||
|
|
@ -28762,20 +28758,20 @@ msgid ""
|
|||
" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Distance between Vias of Different Nets\" \n"
|
||||
" (rule \"Distance between Vias of Different Nets\"\n"
|
||||
" (constraint hole_to_hole (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
" (rule \"Clearance between Pads of Different Nets\" \n"
|
||||
" (rule \"Clearance between Pads of Different Nets\"\n"
|
||||
" (constraint clearance (min 3.0mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Via Hole to Track Clearance\" \n"
|
||||
" (rule \"Via Hole to Track Clearance\"\n"
|
||||
" (constraint hole_clearance (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Track'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Pad to Track Clearance\" \n"
|
||||
" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n"
|
||||
"\n"
|
||||
" (rule \"Pad to Track Clearance\"\n"
|
||||
" (constraint clearance (min 0.2mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -28785,11 +28781,11 @@ msgid ""
|
|||
" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\" \n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\"\n"
|
||||
" (constraint hole_size (max 6.3mm))\n"
|
||||
" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Max Drill Hole Size PTH\" \n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size PTH\"\n"
|
||||
" (constraint hole_size (max 6.35mm))\n"
|
||||
" (condition \"A.Pad_Type == 'Through-hole'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -28797,7 +28793,7 @@ msgid ""
|
|||
" # Specify an optimal gap for a particular diff-pair\n"
|
||||
" (rule \"dp clock gap\"\n"
|
||||
" (constraint diff_pair_gap (opt \"0.8mm\"))\n"
|
||||
" (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n"
|
||||
" (condition \"A.inDiffPair('/CLK')\"))\n"
|
||||
"\n"
|
||||
" # Specify a larger clearance around any diff-pair\n"
|
||||
" (rule \"dp clearance\"\n"
|
||||
|
|
@ -31310,11 +31306,11 @@ msgstr "Mönsterkortsfilen är skrivskyddad."
|
|||
msgid "PCB file changes are unsaved"
|
||||
msgstr "PCB-filändringar sparas inte"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1473
|
||||
#: pcbnew/pcb_edit_frame.cpp:1466
|
||||
msgid "The schematic for this board cannot be found."
|
||||
msgstr "Kretsschemat för detta mönsterkort kan inte hittas."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1497
|
||||
#: pcbnew/pcb_edit_frame.cpp:1490
|
||||
msgid ""
|
||||
"Cannot update the PCB because PCB editor is opened in stand-alone mode. In "
|
||||
"order to create or update PCBs from schematics, you must launch the KiCad "
|
||||
|
|
@ -31324,11 +31320,11 @@ msgstr ""
|
|||
"fristående läge. För att skapa eller uppdatera mönsterkort från scheman "
|
||||
"måste du starta KiCads projekthanterare och skapa ett projekt."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1519
|
||||
#: pcbnew/pcb_edit_frame.cpp:1512
|
||||
msgid "Eeschema netlist"
|
||||
msgstr "Eeschema-nätlista"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1530
|
||||
#: pcbnew/pcb_edit_frame.cpp:1523
|
||||
msgid ""
|
||||
"Received an error while reading netlist. Please report this issue to the "
|
||||
"KiCad team using the menu Help->Report Bug."
|
||||
|
|
@ -31336,31 +31332,31 @@ msgstr ""
|
|||
"Stötte på ett fel under inläsning av nätlistan. Vänligen rapportera detta "
|
||||
"problem till KiCad-teamet genom menyn Hjälp -> Rapportera fel."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1557
|
||||
#: pcbnew/pcb_edit_frame.cpp:1550
|
||||
#, c-format
|
||||
msgid "Schematic file '%s' not found."
|
||||
msgstr "Kretsschemafil '%s' hittades inte."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1587
|
||||
#: pcbnew/pcb_edit_frame.cpp:1580
|
||||
msgid "Eeschema failed to load."
|
||||
msgstr "Eeschema kunde inte ladda."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1738
|
||||
#: pcbnew/pcb_edit_frame.cpp:1731
|
||||
msgid "Edit design rules"
|
||||
msgstr "Ändra designregler"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1750
|
||||
#: pcbnew/pcb_edit_frame.cpp:1743
|
||||
msgid "Could not compile custom design rules."
|
||||
msgstr "Kunde inte kompilera anpassade designregler."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1785
|
||||
#: pcbnew/pcb_edit_frame.cpp:1778
|
||||
msgid "Export Hyperlynx Layout"
|
||||
msgstr "Exportera Hyperlynx Layout"
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:95 pcbnew/pcb_expr_evaluator.cpp:264
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:330 pcbnew/pcb_expr_evaluator.cpp:396
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:614 pcbnew/pcb_expr_evaluator.cpp:716
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:829
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:824
|
||||
#, c-format
|
||||
msgid "Missing argument to '%s'"
|
||||
msgstr "Argumentet saknas till '%s'"
|
||||
|
|
@ -31382,7 +31378,7 @@ msgstr "Fotavtryck har ingen innergård."
|
|||
msgid "Footprint has no back courtyard."
|
||||
msgstr "Footprint har ingen bakgård."
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1152
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1153
|
||||
msgid "must be mm, in, or mil"
|
||||
msgstr "måste vara mm, in eller mil"
|
||||
|
||||
|
|
@ -36569,6 +36565,10 @@ msgstr "KiCad schema"
|
|||
msgid "KiCad Printed Circuit Board"
|
||||
msgstr "KiCad-mönsterkort"
|
||||
|
||||
#, fuzzy
|
||||
#~ msgid "Net CodewxT( "
|
||||
#~ msgstr "Nettokod"
|
||||
|
||||
#~ msgid "Save changes to schematic before closing?"
|
||||
#~ msgstr "Spara ändringar i schemat före stängning?"
|
||||
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@ msgid ""
|
|||
msgstr ""
|
||||
"Project-Id-Version: KiCad\n"
|
||||
"Report-Msgid-Bugs-To: \n"
|
||||
"POT-Creation-Date: 2022-02-14 09:20-0800\n"
|
||||
"POT-Creation-Date: 2022-02-16 17:22-0800\n"
|
||||
"PO-Revision-Date: 2021-12-17 00:56+0000\n"
|
||||
"Last-Translator: boonchai k. <kicadthai@gmail.com>\n"
|
||||
"Language-Team: Thai <https://hosted.weblate.org/projects/kicad/master-source/"
|
||||
|
|
@ -4499,12 +4499,12 @@ msgstr "แฝง: "
|
|||
|
||||
#: common/filename_resolver.cpp:468
|
||||
#, fuzzy
|
||||
msgid "This path:wxT( "
|
||||
msgid "This path:"
|
||||
msgstr "เส้นทางนี้:"
|
||||
|
||||
#: common/filename_resolver.cpp:471
|
||||
#, fuzzy
|
||||
msgid "Existing path:wxT( "
|
||||
msgid "Existing path:"
|
||||
msgstr "เส้นทางที่มีอยู่:"
|
||||
|
||||
#: common/filename_resolver.cpp:473
|
||||
|
|
@ -13130,9 +13130,9 @@ msgstr "กำหนดเน็ตคลาส"
|
|||
msgid "Connection Name"
|
||||
msgstr "ชื่อการเชื่อมต่อ"
|
||||
|
||||
#: eeschema/sch_connection.cpp:415
|
||||
#, fuzzy
|
||||
msgid "Net CodewxT( "
|
||||
#: eeschema/sch_connection.cpp:415 pcbnew/dialogs/dialog_net_inspector.cpp:76
|
||||
#: pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr "รหัสเน็ต"
|
||||
|
||||
#: eeschema/sch_connection.cpp:420 eeschema/sch_connection.cpp:433
|
||||
|
|
@ -18768,8 +18768,8 @@ msgid "Application failed to load:\n"
|
|||
msgstr "ไม่สามารถโหลดแอปพลิเคชัน:\n"
|
||||
|
||||
#: kicad/tools/kicad_manager_control.cpp:670
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1558
|
||||
#: pcbnew/pcb_edit_frame.cpp:1588
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1551
|
||||
#: pcbnew/pcb_edit_frame.cpp:1581
|
||||
msgid "KiCad Error"
|
||||
msgstr "KiCad ผิดพลาด"
|
||||
|
||||
|
|
@ -21788,7 +21788,7 @@ msgstr "ขนาดที่กําหนดไว้ล่วงหน้า
|
|||
|
||||
#: pcbnew/dialogs/dialog_board_setup.cpp:108
|
||||
#: pcbnew/dialogs/dialog_constraints_reporter.cpp:54
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1744
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1737
|
||||
msgid "Custom Rules"
|
||||
msgstr "กฎที่กำหนดเอง"
|
||||
|
||||
|
|
@ -24781,10 +24781,6 @@ msgstr "ใช้พิกัดเชิงขั้ว"
|
|||
msgid "Move Item"
|
||||
msgstr "ย้ายชิ้นส่วน"
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:76 pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr "รหัสเน็ต"
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:77 pcbnew/netinfo_item.cpp:74
|
||||
msgid "Net Name"
|
||||
msgstr "ชื่อเน็ต"
|
||||
|
|
@ -28139,6 +28135,7 @@ msgid "Check rule syntax"
|
|||
msgstr "ตรวจสอบไวยากรณ์ของกฎ"
|
||||
|
||||
#: pcbnew/dialogs/panel_setup_rules_help_md.h:2
|
||||
#, fuzzy
|
||||
msgid ""
|
||||
"### Top-level Clauses\n"
|
||||
"\n"
|
||||
|
|
@ -28264,8 +28261,8 @@ msgid ""
|
|||
" A.inDiffPair('<net_name>')\n"
|
||||
"True if `A` has net that is part of the specified differential pair.\n"
|
||||
"`<net_name>` is the base name of the differential pair. For example, "
|
||||
"`inDiffPair('CLK')`\n"
|
||||
"matches items in the `CLK_P` and `CLK_N` nets.\n"
|
||||
"`inDiffPair('/CLK')`\n"
|
||||
"matches items in the `/CLK_P` and `/CLK_N` nets.\n"
|
||||
"<br><br>\n"
|
||||
"\n"
|
||||
" AB.isCoupledDiffPair()\n"
|
||||
|
|
@ -28305,20 +28302,20 @@ msgid ""
|
|||
" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Distance between Vias of Different Nets\" \n"
|
||||
" (rule \"Distance between Vias of Different Nets\"\n"
|
||||
" (constraint hole_to_hole (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
" (rule \"Clearance between Pads of Different Nets\" \n"
|
||||
" (rule \"Clearance between Pads of Different Nets\"\n"
|
||||
" (constraint clearance (min 3.0mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Via Hole to Track Clearance\" \n"
|
||||
" (rule \"Via Hole to Track Clearance\"\n"
|
||||
" (constraint hole_clearance (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Track'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Pad to Track Clearance\" \n"
|
||||
" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n"
|
||||
"\n"
|
||||
" (rule \"Pad to Track Clearance\"\n"
|
||||
" (constraint clearance (min 0.2mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -28328,11 +28325,11 @@ msgid ""
|
|||
" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\" \n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\"\n"
|
||||
" (constraint hole_size (max 6.3mm))\n"
|
||||
" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Max Drill Hole Size PTH\" \n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size PTH\"\n"
|
||||
" (constraint hole_size (max 6.35mm))\n"
|
||||
" (condition \"A.Pad_Type == 'Through-hole'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -28340,7 +28337,7 @@ msgid ""
|
|||
" # Specify an optimal gap for a particular diff-pair\n"
|
||||
" (rule \"dp clock gap\"\n"
|
||||
" (constraint diff_pair_gap (opt \"0.8mm\"))\n"
|
||||
" (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n"
|
||||
" (condition \"A.inDiffPair('/CLK')\"))\n"
|
||||
"\n"
|
||||
" # Specify a larger clearance around any diff-pair\n"
|
||||
" (rule \"dp clearance\"\n"
|
||||
|
|
@ -31022,11 +31019,11 @@ msgstr "ไฟล์บอร์ดอ่านอย่างเดียวเ
|
|||
msgid "PCB file changes are unsaved"
|
||||
msgstr "การเปลี่ยนแปลงไฟล์พีซีบีไม่ได้รับการบันทึก"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1473
|
||||
#: pcbnew/pcb_edit_frame.cpp:1466
|
||||
msgid "The schematic for this board cannot be found."
|
||||
msgstr "ไม่พบแผนวงจรสำหรับบอร์ดนี้"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1497
|
||||
#: pcbnew/pcb_edit_frame.cpp:1490
|
||||
msgid ""
|
||||
"Cannot update the PCB because PCB editor is opened in stand-alone mode. In "
|
||||
"order to create or update PCBs from schematics, you must launch the KiCad "
|
||||
|
|
@ -31035,11 +31032,11 @@ msgstr ""
|
|||
"ไม่สามารถปรับปรุงพีซีบี เนื่องจากตัวแก้ไขพีซีบีถูกเปิดในโหมดโดดเดี่ยว ในการสร้างหรืออัปเดตพีซีบี "
|
||||
"จากวงจรคุณต้องเปิดตัวจัดการโครงการ KiCad และสร้างโปรเจ็ก"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1519
|
||||
#: pcbnew/pcb_edit_frame.cpp:1512
|
||||
msgid "Eeschema netlist"
|
||||
msgstr "รายชื่อเน็ตของ Eeschema"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1530
|
||||
#: pcbnew/pcb_edit_frame.cpp:1523
|
||||
msgid ""
|
||||
"Received an error while reading netlist. Please report this issue to the "
|
||||
"KiCad team using the menu Help->Report Bug."
|
||||
|
|
@ -31047,31 +31044,31 @@ msgstr ""
|
|||
"ได้รับแจ้งข้อผิดพลาดระหว่างอ่านรายชื่อเน็ต กรุณารายงานปัญหานี้แก่ทีมงาน KiCad โดยใช้เมนู "
|
||||
"ช่วยเหลือ->รายงานข้อผิดพลาด"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1557
|
||||
#: pcbnew/pcb_edit_frame.cpp:1550
|
||||
#, c-format
|
||||
msgid "Schematic file '%s' not found."
|
||||
msgstr "ไฟล์วงจร '%s' หาไม่พบ"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1587
|
||||
#: pcbnew/pcb_edit_frame.cpp:1580
|
||||
msgid "Eeschema failed to load."
|
||||
msgstr "Eeschema ไม่สามารถโหลด"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1738
|
||||
#: pcbnew/pcb_edit_frame.cpp:1731
|
||||
msgid "Edit design rules"
|
||||
msgstr "แก้ไขกฏการออกแบบ"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1750
|
||||
#: pcbnew/pcb_edit_frame.cpp:1743
|
||||
msgid "Could not compile custom design rules."
|
||||
msgstr "ไม่สามารถรวบรวมกฎการออกแบบที่กำหนดเอง"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1785
|
||||
#: pcbnew/pcb_edit_frame.cpp:1778
|
||||
msgid "Export Hyperlynx Layout"
|
||||
msgstr "ส่งออกเค้าโครงไฮเปอร์ลินซ์"
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:95 pcbnew/pcb_expr_evaluator.cpp:264
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:330 pcbnew/pcb_expr_evaluator.cpp:396
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:614 pcbnew/pcb_expr_evaluator.cpp:716
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:829
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:824
|
||||
#, c-format
|
||||
msgid "Missing argument to '%s'"
|
||||
msgstr "ไม่มีอาร์กิวเมนต์สำหรับ '%s'"
|
||||
|
|
@ -31093,7 +31090,7 @@ msgstr "ฟุ้ทพรินท์ไม่มีลานสนามด้
|
|||
msgid "Footprint has no back courtyard."
|
||||
msgstr "ฟุ้ทพรินท์ไม่มีลานสนามด้านหลัง"
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1152
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1153
|
||||
msgid "must be mm, in, or mil"
|
||||
msgstr "ต้องเป็น มม., นิ้ว, หรือ มิล."
|
||||
|
||||
|
|
@ -36177,6 +36174,10 @@ msgstr "แผนผังวงจร KiCad"
|
|||
msgid "KiCad Printed Circuit Board"
|
||||
msgstr "แผ่นวงจรพิมพ์ KiCad"
|
||||
|
||||
#, fuzzy
|
||||
#~ msgid "Net CodewxT( "
|
||||
#~ msgstr "รหัสเน็ต"
|
||||
|
||||
#~ msgid "Save changes to schematic before closing?"
|
||||
#~ msgstr "บันทึกการเปลี่ยนแปลงที่แผนผังก่อนปิดหรือไม่?"
|
||||
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@ msgid ""
|
|||
msgstr ""
|
||||
"Project-Id-Version: PACKAGE VERSION\n"
|
||||
"Report-Msgid-Bugs-To: \n"
|
||||
"POT-Creation-Date: 2022-02-14 09:20-0800\n"
|
||||
"POT-Creation-Date: 2022-02-16 17:22-0800\n"
|
||||
"PO-Revision-Date: 2022-02-16 22:56+0000\n"
|
||||
"Last-Translator: Mustafa Selçuk ÇAVDAR <mselcuk@gmail.com>\n"
|
||||
"Language-Team: Turkish <https://hosted.weblate.org/projects/kicad/v6/tr/>\n"
|
||||
|
|
@ -4568,12 +4568,12 @@ msgstr "Takma Ad: "
|
|||
|
||||
#: common/filename_resolver.cpp:468
|
||||
#, fuzzy
|
||||
msgid "This path:wxT( "
|
||||
msgid "This path:"
|
||||
msgstr "Bu yol:"
|
||||
|
||||
#: common/filename_resolver.cpp:471
|
||||
#, fuzzy
|
||||
msgid "Existing path:wxT( "
|
||||
msgid "Existing path:"
|
||||
msgstr "Mevcut yol:"
|
||||
|
||||
#: common/filename_resolver.cpp:473
|
||||
|
|
@ -8428,7 +8428,7 @@ msgid "ERC report (%s, Encoding UTF8)\n"
|
|||
msgstr "ERC raporu (%s, UTF8 Kodlaması)\n"
|
||||
|
||||
#: eeschema/dialogs/dialog_erc.cpp:810
|
||||
#, c-format, fuzzy
|
||||
#, fuzzy, c-format
|
||||
msgid ""
|
||||
"\n"
|
||||
"***** Sheet %s\n"
|
||||
|
|
@ -13074,9 +13074,9 @@ msgstr "Atanan Ağsınıfı"
|
|||
msgid "Connection Name"
|
||||
msgstr "Bağlantı Adı"
|
||||
|
||||
#: eeschema/sch_connection.cpp:415
|
||||
#, fuzzy
|
||||
msgid "Net CodewxT( "
|
||||
#: eeschema/sch_connection.cpp:415 pcbnew/dialogs/dialog_net_inspector.cpp:76
|
||||
#: pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr "Ağ kodu"
|
||||
|
||||
#: eeschema/sch_connection.cpp:420 eeschema/sch_connection.cpp:433
|
||||
|
|
@ -18440,8 +18440,8 @@ msgid "Application failed to load:\n"
|
|||
msgstr ""
|
||||
|
||||
#: kicad/tools/kicad_manager_control.cpp:670
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1558
|
||||
#: pcbnew/pcb_edit_frame.cpp:1588
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1551
|
||||
#: pcbnew/pcb_edit_frame.cpp:1581
|
||||
msgid "KiCad Error"
|
||||
msgstr ""
|
||||
|
||||
|
|
@ -21290,7 +21290,7 @@ msgstr ""
|
|||
|
||||
#: pcbnew/dialogs/dialog_board_setup.cpp:108
|
||||
#: pcbnew/dialogs/dialog_constraints_reporter.cpp:54
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1744
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1737
|
||||
msgid "Custom Rules"
|
||||
msgstr ""
|
||||
|
||||
|
|
@ -24188,10 +24188,6 @@ msgstr ""
|
|||
msgid "Move Item"
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:76 pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr "Ağ kodu"
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:77 pcbnew/netinfo_item.cpp:74
|
||||
msgid "Net Name"
|
||||
msgstr ""
|
||||
|
|
@ -27527,8 +27523,8 @@ msgid ""
|
|||
" A.inDiffPair('<net_name>')\n"
|
||||
"True if `A` has net that is part of the specified differential pair.\n"
|
||||
"`<net_name>` is the base name of the differential pair. For example, "
|
||||
"`inDiffPair('CLK')`\n"
|
||||
"matches items in the `CLK_P` and `CLK_N` nets.\n"
|
||||
"`inDiffPair('/CLK')`\n"
|
||||
"matches items in the `/CLK_P` and `/CLK_N` nets.\n"
|
||||
"<br><br>\n"
|
||||
"\n"
|
||||
" AB.isCoupledDiffPair()\n"
|
||||
|
|
@ -27568,20 +27564,20 @@ msgid ""
|
|||
" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Distance between Vias of Different Nets\" \n"
|
||||
" (rule \"Distance between Vias of Different Nets\"\n"
|
||||
" (constraint hole_to_hole (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
" (rule \"Clearance between Pads of Different Nets\" \n"
|
||||
" (rule \"Clearance between Pads of Different Nets\"\n"
|
||||
" (constraint clearance (min 3.0mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Via Hole to Track Clearance\" \n"
|
||||
" (rule \"Via Hole to Track Clearance\"\n"
|
||||
" (constraint hole_clearance (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Track'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Pad to Track Clearance\" \n"
|
||||
" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n"
|
||||
"\n"
|
||||
" (rule \"Pad to Track Clearance\"\n"
|
||||
" (constraint clearance (min 0.2mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -27591,11 +27587,11 @@ msgid ""
|
|||
" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\" \n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\"\n"
|
||||
" (constraint hole_size (max 6.3mm))\n"
|
||||
" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Max Drill Hole Size PTH\" \n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size PTH\"\n"
|
||||
" (constraint hole_size (max 6.35mm))\n"
|
||||
" (condition \"A.Pad_Type == 'Through-hole'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -27603,7 +27599,7 @@ msgid ""
|
|||
" # Specify an optimal gap for a particular diff-pair\n"
|
||||
" (rule \"dp clock gap\"\n"
|
||||
" (constraint diff_pair_gap (opt \"0.8mm\"))\n"
|
||||
" (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n"
|
||||
" (condition \"A.inDiffPair('/CLK')\"))\n"
|
||||
"\n"
|
||||
" # Specify a larger clearance around any diff-pair\n"
|
||||
" (rule \"dp clearance\"\n"
|
||||
|
|
@ -30036,52 +30032,52 @@ msgstr ""
|
|||
msgid "PCB file changes are unsaved"
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1473
|
||||
#: pcbnew/pcb_edit_frame.cpp:1466
|
||||
msgid "The schematic for this board cannot be found."
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1497
|
||||
#: pcbnew/pcb_edit_frame.cpp:1490
|
||||
msgid ""
|
||||
"Cannot update the PCB because PCB editor is opened in stand-alone mode. In "
|
||||
"order to create or update PCBs from schematics, you must launch the KiCad "
|
||||
"project manager and create a project."
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1519
|
||||
#: pcbnew/pcb_edit_frame.cpp:1512
|
||||
msgid "Eeschema netlist"
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1530
|
||||
#: pcbnew/pcb_edit_frame.cpp:1523
|
||||
msgid ""
|
||||
"Received an error while reading netlist. Please report this issue to the "
|
||||
"KiCad team using the menu Help->Report Bug."
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1557
|
||||
#: pcbnew/pcb_edit_frame.cpp:1550
|
||||
#, c-format
|
||||
msgid "Schematic file '%s' not found."
|
||||
msgstr "Şematik dosya '%s' bulunamadı."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1587
|
||||
#: pcbnew/pcb_edit_frame.cpp:1580
|
||||
msgid "Eeschema failed to load."
|
||||
msgstr "Eeschema yüklenemedi."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1738
|
||||
#: pcbnew/pcb_edit_frame.cpp:1731
|
||||
msgid "Edit design rules"
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1750
|
||||
#: pcbnew/pcb_edit_frame.cpp:1743
|
||||
msgid "Could not compile custom design rules."
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1785
|
||||
#: pcbnew/pcb_edit_frame.cpp:1778
|
||||
msgid "Export Hyperlynx Layout"
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:95 pcbnew/pcb_expr_evaluator.cpp:264
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:330 pcbnew/pcb_expr_evaluator.cpp:396
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:614 pcbnew/pcb_expr_evaluator.cpp:716
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:829
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:824
|
||||
#, c-format
|
||||
msgid "Missing argument to '%s'"
|
||||
msgstr ""
|
||||
|
|
@ -30103,7 +30099,7 @@ msgstr ""
|
|||
msgid "Footprint has no back courtyard."
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1152
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1153
|
||||
msgid "must be mm, in, or mil"
|
||||
msgstr ""
|
||||
|
||||
|
|
@ -35034,6 +35030,10 @@ msgstr "KiCad Şeması"
|
|||
msgid "KiCad Printed Circuit Board"
|
||||
msgstr "KiCad Baskılı Devre Kartı"
|
||||
|
||||
#, fuzzy
|
||||
#~ msgid "Net CodewxT( "
|
||||
#~ msgstr "Ağ kodu"
|
||||
|
||||
#~ msgid "Others"
|
||||
#~ msgstr "Diğerleri"
|
||||
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@ msgid ""
|
|||
msgstr ""
|
||||
"Project-Id-Version: Kicad\n"
|
||||
"Report-Msgid-Bugs-To: \n"
|
||||
"POT-Creation-Date: 2022-02-14 09:20-0800\n"
|
||||
"POT-Creation-Date: 2022-02-16 17:22-0800\n"
|
||||
"PO-Revision-Date: 2021-11-28 23:29+0000\n"
|
||||
"Last-Translator: lê văn lập <levanlap2502@gmail.com>\n"
|
||||
"Language-Team: Vietnamese <https://hosted.weblate.org/projects/kicad/master-"
|
||||
|
|
@ -4809,12 +4809,12 @@ msgstr "Bí danh: "
|
|||
|
||||
#: common/filename_resolver.cpp:468
|
||||
#, fuzzy
|
||||
msgid "This path:wxT( "
|
||||
msgid "This path:"
|
||||
msgstr "Đường dẫn này:"
|
||||
|
||||
#: common/filename_resolver.cpp:471
|
||||
#, fuzzy
|
||||
msgid "Existing path:wxT( "
|
||||
msgid "Existing path:"
|
||||
msgstr "Đường dẫn hiện tại:"
|
||||
|
||||
#: common/filename_resolver.cpp:473
|
||||
|
|
@ -13601,8 +13601,9 @@ msgstr ""
|
|||
msgid "Connection Name"
|
||||
msgstr ""
|
||||
|
||||
#: eeschema/sch_connection.cpp:415
|
||||
msgid "Net CodewxT( "
|
||||
#: eeschema/sch_connection.cpp:415 pcbnew/dialogs/dialog_net_inspector.cpp:76
|
||||
#: pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr ""
|
||||
|
||||
#: eeschema/sch_connection.cpp:420 eeschema/sch_connection.cpp:433
|
||||
|
|
@ -19113,8 +19114,8 @@ msgid "Application failed to load:\n"
|
|||
msgstr ""
|
||||
|
||||
#: kicad/tools/kicad_manager_control.cpp:670
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1558
|
||||
#: pcbnew/pcb_edit_frame.cpp:1588
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1551
|
||||
#: pcbnew/pcb_edit_frame.cpp:1581
|
||||
msgid "KiCad Error"
|
||||
msgstr ""
|
||||
|
||||
|
|
@ -22007,7 +22008,7 @@ msgstr ""
|
|||
|
||||
#: pcbnew/dialogs/dialog_board_setup.cpp:108
|
||||
#: pcbnew/dialogs/dialog_constraints_reporter.cpp:54
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1744
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1737
|
||||
#, fuzzy
|
||||
msgid "Custom Rules"
|
||||
msgstr "Tùy chỉnh:"
|
||||
|
|
@ -24933,10 +24934,6 @@ msgstr ""
|
|||
msgid "Move Item"
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:76 pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:77 pcbnew/netinfo_item.cpp:74
|
||||
msgid "Net Name"
|
||||
msgstr ""
|
||||
|
|
@ -28306,8 +28303,8 @@ msgid ""
|
|||
" A.inDiffPair('<net_name>')\n"
|
||||
"True if `A` has net that is part of the specified differential pair.\n"
|
||||
"`<net_name>` is the base name of the differential pair. For example, "
|
||||
"`inDiffPair('CLK')`\n"
|
||||
"matches items in the `CLK_P` and `CLK_N` nets.\n"
|
||||
"`inDiffPair('/CLK')`\n"
|
||||
"matches items in the `/CLK_P` and `/CLK_N` nets.\n"
|
||||
"<br><br>\n"
|
||||
"\n"
|
||||
" AB.isCoupledDiffPair()\n"
|
||||
|
|
@ -28347,20 +28344,20 @@ msgid ""
|
|||
" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Distance between Vias of Different Nets\" \n"
|
||||
" (rule \"Distance between Vias of Different Nets\"\n"
|
||||
" (constraint hole_to_hole (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
" (rule \"Clearance between Pads of Different Nets\" \n"
|
||||
" (rule \"Clearance between Pads of Different Nets\"\n"
|
||||
" (constraint clearance (min 3.0mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Via Hole to Track Clearance\" \n"
|
||||
" (rule \"Via Hole to Track Clearance\"\n"
|
||||
" (constraint hole_clearance (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Track'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Pad to Track Clearance\" \n"
|
||||
" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n"
|
||||
"\n"
|
||||
" (rule \"Pad to Track Clearance\"\n"
|
||||
" (constraint clearance (min 0.2mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -28370,11 +28367,11 @@ msgid ""
|
|||
" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\" \n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\"\n"
|
||||
" (constraint hole_size (max 6.3mm))\n"
|
||||
" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Max Drill Hole Size PTH\" \n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size PTH\"\n"
|
||||
" (constraint hole_size (max 6.35mm))\n"
|
||||
" (condition \"A.Pad_Type == 'Through-hole'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -28382,7 +28379,7 @@ msgid ""
|
|||
" # Specify an optimal gap for a particular diff-pair\n"
|
||||
" (rule \"dp clock gap\"\n"
|
||||
" (constraint diff_pair_gap (opt \"0.8mm\"))\n"
|
||||
" (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n"
|
||||
" (condition \"A.inDiffPair('/CLK')\"))\n"
|
||||
"\n"
|
||||
" # Specify a larger clearance around any diff-pair\n"
|
||||
" (rule \"dp clearance\"\n"
|
||||
|
|
@ -30852,55 +30849,55 @@ msgstr ""
|
|||
msgid "PCB file changes are unsaved"
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1473
|
||||
#: pcbnew/pcb_edit_frame.cpp:1466
|
||||
msgid "The schematic for this board cannot be found."
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1497
|
||||
#: pcbnew/pcb_edit_frame.cpp:1490
|
||||
msgid ""
|
||||
"Cannot update the PCB because PCB editor is opened in stand-alone mode. In "
|
||||
"order to create or update PCBs from schematics, you must launch the KiCad "
|
||||
"project manager and create a project."
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1519
|
||||
#: pcbnew/pcb_edit_frame.cpp:1512
|
||||
msgid "Eeschema netlist"
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1530
|
||||
#: pcbnew/pcb_edit_frame.cpp:1523
|
||||
msgid ""
|
||||
"Received an error while reading netlist. Please report this issue to the "
|
||||
"KiCad team using the menu Help->Report Bug."
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1557
|
||||
#: pcbnew/pcb_edit_frame.cpp:1550
|
||||
#, fuzzy, c-format
|
||||
msgid "Schematic file '%s' not found."
|
||||
msgstr "không tìm thấy tệp tin \"%s\"."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1587
|
||||
#: pcbnew/pcb_edit_frame.cpp:1580
|
||||
#, fuzzy
|
||||
msgid "Eeschema failed to load."
|
||||
msgstr "Không tải được thư viện kiface \"%s\"."
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1738
|
||||
#: pcbnew/pcb_edit_frame.cpp:1731
|
||||
#, fuzzy
|
||||
msgid "Edit design rules"
|
||||
msgstr "Chỉnh sửa tập tin"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1750
|
||||
#: pcbnew/pcb_edit_frame.cpp:1743
|
||||
#, fuzzy
|
||||
msgid "Could not compile custom design rules."
|
||||
msgstr "Không thể mở tệp cấu hình"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1785
|
||||
#: pcbnew/pcb_edit_frame.cpp:1778
|
||||
msgid "Export Hyperlynx Layout"
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:95 pcbnew/pcb_expr_evaluator.cpp:264
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:330 pcbnew/pcb_expr_evaluator.cpp:396
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:614 pcbnew/pcb_expr_evaluator.cpp:716
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:829
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:824
|
||||
#, c-format
|
||||
msgid "Missing argument to '%s'"
|
||||
msgstr ""
|
||||
|
|
@ -30922,7 +30919,7 @@ msgstr ""
|
|||
msgid "Footprint has no back courtyard."
|
||||
msgstr ""
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1152
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1153
|
||||
msgid "must be mm, in, or mil"
|
||||
msgstr ""
|
||||
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@ msgid ""
|
|||
msgstr ""
|
||||
"Project-Id-Version: KiCad_zh_CN_Master_v0.0.32\n"
|
||||
"Report-Msgid-Bugs-To: \n"
|
||||
"POT-Creation-Date: 2022-02-14 09:20-0800\n"
|
||||
"POT-Creation-Date: 2022-02-16 17:22-0800\n"
|
||||
"PO-Revision-Date: 2022-02-16 13:03+0000\n"
|
||||
"Last-Translator: Eric <alchemillatruth@purelymail.com>\n"
|
||||
"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
|
||||
|
|
@ -4515,11 +4515,13 @@ msgid "Alias: "
|
|||
msgstr "别名： "
|
||||
|
||||
#: common/filename_resolver.cpp:468
|
||||
msgid "This path:wxT( "
|
||||
#, fuzzy
|
||||
msgid "This path:"
|
||||
msgstr "此路径：wxT( "
|
||||
|
||||
#: common/filename_resolver.cpp:471
|
||||
msgid "Existing path:wxT( "
|
||||
#, fuzzy
|
||||
msgid "Existing path:"
|
||||
msgstr "现有路径：wxT( "
|
||||
|
||||
#: common/filename_resolver.cpp:473
|
||||
|
|
@ -13112,9 +13114,10 @@ msgstr "关联的网络类"
|
|||
msgid "Connection Name"
|
||||
msgstr "连接名称"
|
||||
|
||||
#: eeschema/sch_connection.cpp:415
|
||||
msgid "Net CodewxT( "
|
||||
msgstr "网络 CodewxT( "
|
||||
#: eeschema/sch_connection.cpp:415 pcbnew/dialogs/dialog_net_inspector.cpp:76
|
||||
#: pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr "网络码"
|
||||
|
||||
#: eeschema/sch_connection.cpp:420 eeschema/sch_connection.cpp:433
|
||||
#, c-format
|
||||
|
|
@ -18740,8 +18743,8 @@ msgid "Application failed to load:\n"
|
|||
msgstr "应用程序加载失败：\n"
|
||||
|
||||
#: kicad/tools/kicad_manager_control.cpp:670
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1558
|
||||
#: pcbnew/pcb_edit_frame.cpp:1588
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1551
|
||||
#: pcbnew/pcb_edit_frame.cpp:1581
|
||||
msgid "KiCad Error"
|
||||
msgstr "KiCad 错误"
|
||||
|
||||
|
|
@ -20306,11 +20309,13 @@ msgid ""
|
|||
msgstr ""
|
||||
"如果你指定最大电流，则会计算相应的布线宽度。\n"
|
||||
"\n"
|
||||
"如果你指定其中一个布线宽度，则将计算它可以处理的最大电流。然后将计算另外的同样处理此电流的布线宽度。\n"
|
||||
"如果你指定其中一个布线宽度，则将计算它可以处理的最大电流。然后将计算另外的同"
|
||||
"样处理此电流的布线宽度。\n"
|
||||
"\n"
|
||||
"控制值以粗体显示。\n"
|
||||
"\n"
|
||||
"计算适用于最大 35A（外部）或 17.5A（内部）的电流、高达 100 °C的温升和最多 400mil（10mm）的宽度。\n"
|
||||
"计算适用于最大 35A（外部）或 17.5A（内部）的电流、高达 100 °C的温升和最多 "
|
||||
"400mil（10mm）的宽度。\n"
|
||||
"\n"
|
||||
"来自 IPC 2221 的该公式，为\n"
|
||||
"<center>___I = K · ΔT<sup>0.44</sup> · (W · "
|
||||
|
|
@ -21757,7 +21762,7 @@ msgstr "预定义尺寸"
|
|||
|
||||
#: pcbnew/dialogs/dialog_board_setup.cpp:108
|
||||
#: pcbnew/dialogs/dialog_constraints_reporter.cpp:54
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1744
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1737
|
||||
msgid "Custom Rules"
|
||||
msgstr "自定义规则"
|
||||
|
||||
|
|
@ -24745,10 +24750,6 @@ msgstr "使用极坐标"
|
|||
msgid "Move Item"
|
||||
msgstr "移动项目"
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:76 pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr "网络码"
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:77 pcbnew/netinfo_item.cpp:74
|
||||
msgid "Net Name"
|
||||
msgstr "网络名称"
|
||||
|
|
@ -27208,7 +27209,9 @@ msgstr "模仿旧行为"
|
|||
msgid ""
|
||||
"Produces a slightly smoother outline at the expense of performance, some "
|
||||
"export fidelity issues, and overly aggressive higher-priority zone knockouts."
|
||||
msgstr "以牺牲性能、一些导出保真度问题和过于激进的高优先级区域挖空为代价，生成稍微平滑的轮廓。"
|
||||
msgstr ""
|
||||
"以牺牲性能、一些导出保真度问题和过于激进的高优先级区域挖空为代价，生成稍微平"
|
||||
"滑的轮廓。"
|
||||
|
||||
#: pcbnew/dialogs/panel_setup_constraints_base.cpp:116
|
||||
msgid "Smoothed polygons (best performance)"
|
||||
|
|
@ -28093,6 +28096,7 @@ msgid "Check rule syntax"
|
|||
msgstr "检查规则语法"
|
||||
|
||||
#: pcbnew/dialogs/panel_setup_rules_help_md.h:2
|
||||
#, fuzzy
|
||||
msgid ""
|
||||
"### Top-level Clauses\n"
|
||||
"\n"
|
||||
|
|
@ -28218,8 +28222,8 @@ msgid ""
|
|||
" A.inDiffPair('<net_name>')\n"
|
||||
"True if `A` has net that is part of the specified differential pair.\n"
|
||||
"`<net_name>` is the base name of the differential pair. For example, "
|
||||
"`inDiffPair('CLK')`\n"
|
||||
"matches items in the `CLK_P` and `CLK_N` nets.\n"
|
||||
"`inDiffPair('/CLK')`\n"
|
||||
"matches items in the `/CLK_P` and `/CLK_N` nets.\n"
|
||||
"<br><br>\n"
|
||||
"\n"
|
||||
" AB.isCoupledDiffPair()\n"
|
||||
|
|
@ -28259,20 +28263,20 @@ msgid ""
|
|||
" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Distance between Vias of Different Nets\" \n"
|
||||
" (rule \"Distance between Vias of Different Nets\"\n"
|
||||
" (constraint hole_to_hole (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
" (rule \"Clearance between Pads of Different Nets\" \n"
|
||||
" (rule \"Clearance between Pads of Different Nets\"\n"
|
||||
" (constraint clearance (min 3.0mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Via Hole to Track Clearance\" \n"
|
||||
" (rule \"Via Hole to Track Clearance\"\n"
|
||||
" (constraint hole_clearance (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Track'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Pad to Track Clearance\" \n"
|
||||
" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n"
|
||||
"\n"
|
||||
" (rule \"Pad to Track Clearance\"\n"
|
||||
" (constraint clearance (min 0.2mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -28282,11 +28286,11 @@ msgid ""
|
|||
" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\" \n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\"\n"
|
||||
" (constraint hole_size (max 6.3mm))\n"
|
||||
" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Max Drill Hole Size PTH\" \n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size PTH\"\n"
|
||||
" (constraint hole_size (max 6.35mm))\n"
|
||||
" (condition \"A.Pad_Type == 'Through-hole'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -28294,7 +28298,7 @@ msgid ""
|
|||
" # Specify an optimal gap for a particular diff-pair\n"
|
||||
" (rule \"dp clock gap\"\n"
|
||||
" (constraint diff_pair_gap (opt \"0.8mm\"))\n"
|
||||
" (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n"
|
||||
" (condition \"A.inDiffPair('/CLK')\"))\n"
|
||||
"\n"
|
||||
" # Specify a larger clearance around any diff-pair\n"
|
||||
" (rule \"dp clearance\"\n"
|
||||
|
|
@ -29554,8 +29558,10 @@ msgid ""
|
|||
"This may result in different fills from previous KiCad versions which used "
|
||||
"the line thicknesses of the board boundary on the Edge Cuts layer."
|
||||
msgstr ""
|
||||
"如果重新填充此电路板上的区域，则将应用铜边缘间隙设置 （参见电路板配置 > 设计规则 > 限制）。\n"
|
||||
"老版本的 KiCad 会将电路板边缘 (Edge Cuts 层) 的线粗细作为铜间距，因此新的填充结果可能与老版本的填充结果不同。"
|
||||
"如果重新填充此电路板上的区域，则将应用铜边缘间隙设置 （参见电路板配置 > 设计"
|
||||
"规则 > 限制）。\n"
|
||||
"老版本的 KiCad 会将电路板边缘 (Edge Cuts 层) 的线粗细作为铜间距，因此新的填充"
|
||||
"结果可能与老版本的填充结果不同。"
|
||||
|
||||
#: pcbnew/files.cpp:548
|
||||
msgid "Edge Clearance Warning"
|
||||
|
|
@ -31019,11 +31025,11 @@ msgstr "电路板文件是只读的。"
|
|||
msgid "PCB file changes are unsaved"
|
||||
msgstr "PCB 文件变更未保存"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1473
|
||||
#: pcbnew/pcb_edit_frame.cpp:1466
|
||||
msgid "The schematic for this board cannot be found."
|
||||
msgstr "找不到该电路板的原理图。"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1497
|
||||
#: pcbnew/pcb_edit_frame.cpp:1490
|
||||
msgid ""
|
||||
"Cannot update the PCB because PCB editor is opened in stand-alone mode. In "
|
||||
"order to create or update PCBs from schematics, you must launch the KiCad "
|
||||
|
|
@ -31032,42 +31038,42 @@ msgstr ""
|
|||
"无法更新 PCB, 因为 PCB 编辑器是在独立模式下打开的。为了从原理图创建或更新 "
|
||||
"PCB, 你必须启动 KiCad 工程管理器并创建一个工程。"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1519
|
||||
#: pcbnew/pcb_edit_frame.cpp:1512
|
||||
msgid "Eeschema netlist"
|
||||
msgstr "Eeschema 网表"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1530
|
||||
#: pcbnew/pcb_edit_frame.cpp:1523
|
||||
msgid ""
|
||||
"Received an error while reading netlist. Please report this issue to the "
|
||||
"KiCad team using the menu Help->Report Bug."
|
||||
msgstr ""
|
||||
"读取网表时收到一个错误。 请使用“帮助->报告错误”菜单向 KiCad 团队报告此问题。"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1557
|
||||
#: pcbnew/pcb_edit_frame.cpp:1550
|
||||
#, c-format
|
||||
msgid "Schematic file '%s' not found."
|
||||
msgstr "没有找到原理图文件 '%s'。"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1587
|
||||
#: pcbnew/pcb_edit_frame.cpp:1580
|
||||
msgid "Eeschema failed to load."
|
||||
msgstr "未能加载 Eeschema。"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1738
|
||||
#: pcbnew/pcb_edit_frame.cpp:1731
|
||||
msgid "Edit design rules"
|
||||
msgstr "编辑设计规则"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1750
|
||||
#: pcbnew/pcb_edit_frame.cpp:1743
|
||||
msgid "Could not compile custom design rules."
|
||||
msgstr "无法编译自定义设计规则。"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1785
|
||||
#: pcbnew/pcb_edit_frame.cpp:1778
|
||||
msgid "Export Hyperlynx Layout"
|
||||
msgstr "导出 Hyperlynx 布局"
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:95 pcbnew/pcb_expr_evaluator.cpp:264
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:330 pcbnew/pcb_expr_evaluator.cpp:396
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:614 pcbnew/pcb_expr_evaluator.cpp:716
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:829
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:824
|
||||
#, c-format
|
||||
msgid "Missing argument to '%s'"
|
||||
msgstr "缺少 '%s' 的参数"
|
||||
|
|
@ -31089,7 +31095,7 @@ msgstr "封装没有顶层外框。"
|
|||
msgid "Footprint has no back courtyard."
|
||||
msgstr "封装没有底层外框。"
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1152
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1153
|
||||
msgid "must be mm, in, or mil"
|
||||
msgstr "单位必须为 mm、in 或 mil"
|
||||
|
||||
|
|
@ -31785,8 +31791,8 @@ msgid ""
|
|||
"between these two settings. The setting for disjoint copper has been applied "
|
||||
"as the minimum island area of the KiCad Zone."
|
||||
msgstr ""
|
||||
"CADSTAR 模板 '%s' 具有不同的设置，用于\"保留敷铜- 不相交\"和\"保留敷铜 - 隔离\"。KiCad 不区分这两个设置。"
|
||||
"不相交敷铜的设置已被应用为 KiCad 区域的最小岛区。"
|
||||
"CADSTAR 模板 '%s' 具有不同的设置，用于\"保留敷铜- 不相交\"和\"保留敷铜 - 隔离"
|
||||
"\"。KiCad 不区分这两个设置。不相交敷铜的设置已被应用为 KiCad 区域的最小岛区。"
|
||||
|
||||
#: pcbnew/plugins/cadstar/cadstar_pcb_archive_loader.cpp:1926
|
||||
#, c-format
|
||||
|
|
@ -31817,7 +31823,9 @@ msgid ""
|
|||
"The CADSTAR layer '%s' is defined as a power plane layer. However no net "
|
||||
"with such name exists. The layer has been loaded but no copper zone was "
|
||||
"created."
|
||||
msgstr "CADSTAR 层 '%s' 被定义为电源层。然而，不存在具有该名称的网络。已加载层，但未创建敷铜区。"
|
||||
msgstr ""
|
||||
"CADSTAR 层 '%s' 被定义为电源层。然而，不存在具有该名称的网络。已加载层，但未"
|
||||
"创建敷铜区。"
|
||||
|
||||
#: pcbnew/plugins/cadstar/cadstar_pcb_archive_loader.cpp:2095
|
||||
msgid ""
|
||||
|
|
@ -31826,8 +31834,9 @@ msgid ""
|
|||
"filled, or as a KiCad Track if the shape was an unfilled outline (open or "
|
||||
"closed)."
|
||||
msgstr ""
|
||||
"CADSTAR 设计包含没有直接 KiCad 等价物的铜元素。如果填充的是实体或图案填充，则它们已导入为 KiCad "
|
||||
"区域；如果形状是未填充的轮廓(开放或闭合)，则它们将导入为 KiCad 布线。"
|
||||
"CADSTAR 设计包含没有直接 KiCad 等价物的铜元素。如果填充的是实体或图案填充，则"
|
||||
"它们已导入为 KiCad 区域；如果形状是未填充的轮廓(开放或闭合)，则它们将导入为 "
|
||||
"KiCad 布线。"
|
||||
|
||||
#: pcbnew/plugins/cadstar/cadstar_pcb_archive_loader.cpp:2200
|
||||
#, c-format
|
||||
|
|
@ -31933,8 +31942,8 @@ msgid ""
|
|||
"imported. Please review the design rules as copper pours will affected by "
|
||||
"this."
|
||||
msgstr ""
|
||||
"CADSTAR 设计包含关联了“间隔类”的网络。KiCad 没有与 CADSTAR "
|
||||
"的间隔类等效的元素，因此未导入这些元素。请检查设计规则，因为敷铜将受此影响。"
|
||||
"CADSTAR 设计包含关联了“间隔类”的网络。KiCad 没有与 CADSTAR 的间隔类等效的元"
|
||||
"素，因此未导入这些元素。请检查设计规则，因为敷铜将受此影响。"
|
||||
|
||||
#: pcbnew/plugins/eagle/eagle_plugin.cpp:377
|
||||
#, c-format
|
||||
|
|
@ -36163,6 +36172,9 @@ msgstr "KiCad 原理图"
|
|||
msgid "KiCad Printed Circuit Board"
|
||||
msgstr "KiCad 印刷电路板"
|
||||
|
||||
#~ msgid "Net CodewxT( "
|
||||
#~ msgstr "网络 CodewxT( "
|
||||
|
||||
#~ msgid "Save changes to schematic before closing?"
|
||||
#~ msgstr "是否在关闭前保存对原理图的变更？"
|
||||
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@ msgid ""
|
|||
msgstr ""
|
||||
"Project-Id-Version: KiCad\n"
|
||||
"Report-Msgid-Bugs-To: \n"
|
||||
"POT-Creation-Date: 2022-02-14 09:20-0800\n"
|
||||
"POT-Creation-Date: 2022-02-16 17:22-0800\n"
|
||||
"PO-Revision-Date: 2022-02-01 13:58+0000\n"
|
||||
"Last-Translator: taotieren <admin@taotieren.com>\n"
|
||||
"Language-Team: Chinese (Traditional) <https://hosted.weblate.org/projects/"
|
||||
|
|
@ -4506,12 +4506,12 @@ msgstr "別名： "
|
|||
|
||||
#: common/filename_resolver.cpp:468
|
||||
#, fuzzy
|
||||
msgid "This path:wxT( "
|
||||
msgid "This path:"
|
||||
msgstr "該路徑："
|
||||
|
||||
#: common/filename_resolver.cpp:471
|
||||
#, fuzzy
|
||||
msgid "Existing path:wxT( "
|
||||
msgid "Existing path:"
|
||||
msgstr "現有路徑："
|
||||
|
||||
#: common/filename_resolver.cpp:473
|
||||
|
|
@ -13104,9 +13104,9 @@ msgstr "關聯的網路類"
|
|||
msgid "Connection Name"
|
||||
msgstr "連線名稱"
|
||||
|
||||
#: eeschema/sch_connection.cpp:415
|
||||
#, fuzzy
|
||||
msgid "Net CodewxT( "
|
||||
#: eeschema/sch_connection.cpp:415 pcbnew/dialogs/dialog_net_inspector.cpp:76
|
||||
#: pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr "網路碼"
|
||||
|
||||
#: eeschema/sch_connection.cpp:420 eeschema/sch_connection.cpp:433
|
||||
|
|
@ -18734,8 +18734,8 @@ msgid "Application failed to load:\n"
|
|||
msgstr "應用程式載入失敗：\n"
|
||||
|
||||
#: kicad/tools/kicad_manager_control.cpp:670
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1558
|
||||
#: pcbnew/pcb_edit_frame.cpp:1588
|
||||
#: kicad/tools/kicad_manager_control.cpp:677 pcbnew/pcb_edit_frame.cpp:1551
|
||||
#: pcbnew/pcb_edit_frame.cpp:1581
|
||||
msgid "KiCad Error"
|
||||
msgstr "KiCad 錯誤"
|
||||
|
||||
|
|
@ -21754,7 +21754,7 @@ msgstr "預定義尺寸"
|
|||
|
||||
#: pcbnew/dialogs/dialog_board_setup.cpp:108
|
||||
#: pcbnew/dialogs/dialog_constraints_reporter.cpp:54
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1744
|
||||
#: pcbnew/dialogs/dialog_drc.cpp:193 pcbnew/pcb_edit_frame.cpp:1737
|
||||
msgid "Custom Rules"
|
||||
msgstr "自定義規則"
|
||||
|
||||
|
|
@ -24741,10 +24741,6 @@ msgstr "使用極座標"
|
|||
msgid "Move Item"
|
||||
msgstr "移動專案"
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:76 pcbnew/netinfo_item.cpp:76
|
||||
msgid "Net Code"
|
||||
msgstr "網路碼"
|
||||
|
||||
#: pcbnew/dialogs/dialog_net_inspector.cpp:77 pcbnew/netinfo_item.cpp:74
|
||||
msgid "Net Name"
|
||||
msgstr "網路名稱"
|
||||
|
|
@ -28090,6 +28086,7 @@ msgid "Check rule syntax"
|
|||
msgstr "檢查規則語法"
|
||||
|
||||
#: pcbnew/dialogs/panel_setup_rules_help_md.h:2
|
||||
#, fuzzy
|
||||
msgid ""
|
||||
"### Top-level Clauses\n"
|
||||
"\n"
|
||||
|
|
@ -28215,8 +28212,8 @@ msgid ""
|
|||
" A.inDiffPair('<net_name>')\n"
|
||||
"True if `A` has net that is part of the specified differential pair.\n"
|
||||
"`<net_name>` is the base name of the differential pair. For example, "
|
||||
"`inDiffPair('CLK')`\n"
|
||||
"matches items in the `CLK_P` and `CLK_N` nets.\n"
|
||||
"`inDiffPair('/CLK')`\n"
|
||||
"matches items in the `/CLK_P` and `/CLK_N` nets.\n"
|
||||
"<br><br>\n"
|
||||
"\n"
|
||||
" AB.isCoupledDiffPair()\n"
|
||||
|
|
@ -28256,20 +28253,20 @@ msgid ""
|
|||
" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Distance between Vias of Different Nets\" \n"
|
||||
" (rule \"Distance between Vias of Different Nets\"\n"
|
||||
" (constraint hole_to_hole (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
" (rule \"Clearance between Pads of Different Nets\" \n"
|
||||
" (rule \"Clearance between Pads of Different Nets\"\n"
|
||||
" (constraint clearance (min 3.0mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Via Hole to Track Clearance\" \n"
|
||||
" (rule \"Via Hole to Track Clearance\"\n"
|
||||
" (constraint hole_clearance (min 0.254mm))\n"
|
||||
" (condition \"A.Type =='Via' && B.Type =='Track'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Pad to Track Clearance\" \n"
|
||||
" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n"
|
||||
"\n"
|
||||
" (rule \"Pad to Track Clearance\"\n"
|
||||
" (constraint clearance (min 0.2mm))\n"
|
||||
" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -28279,11 +28276,11 @@ msgid ""
|
|||
" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n"
|
||||
"\n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\" \n"
|
||||
" (rule \"Max Drill Hole Size Mechanical\"\n"
|
||||
" (constraint hole_size (max 6.3mm))\n"
|
||||
" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n"
|
||||
" \n"
|
||||
" (rule \"Max Drill Hole Size PTH\" \n"
|
||||
"\n"
|
||||
" (rule \"Max Drill Hole Size PTH\"\n"
|
||||
" (constraint hole_size (max 6.35mm))\n"
|
||||
" (condition \"A.Pad_Type == 'Through-hole'\"))\n"
|
||||
"\n"
|
||||
|
|
@ -28291,7 +28288,7 @@ msgid ""
|
|||
" # Specify an optimal gap for a particular diff-pair\n"
|
||||
" (rule \"dp clock gap\"\n"
|
||||
" (constraint diff_pair_gap (opt \"0.8mm\"))\n"
|
||||
" (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n"
|
||||
" (condition \"A.inDiffPair('/CLK')\"))\n"
|
||||
"\n"
|
||||
" # Specify a larger clearance around any diff-pair\n"
|
||||
" (rule \"dp clearance\"\n"
|
||||
|
|
@ -31020,11 +31017,11 @@ msgstr "電路板檔案是隻讀的。"
|
|||
msgid "PCB file changes are unsaved"
|
||||
msgstr "PCB 檔案變更未儲存"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1473
|
||||
#: pcbnew/pcb_edit_frame.cpp:1466
|
||||
msgid "The schematic for this board cannot be found."
|
||||
msgstr "找不到該電路板的原理圖。"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1497
|
||||
#: pcbnew/pcb_edit_frame.cpp:1490
|
||||
msgid ""
|
||||
"Cannot update the PCB because PCB editor is opened in stand-alone mode. In "
|
||||
"order to create or update PCBs from schematics, you must launch the KiCad "
|
||||
|
|
@ -31033,42 +31030,42 @@ msgstr ""
|
|||
"無法更新 PCB, 因為 PCB 編輯器是在獨立模式下開啟的。為了從原理圖建立或更新 "
|
||||
"PCB, 你必須啟動 KiCad 工程管理器並建立一個工程。"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1519
|
||||
#: pcbnew/pcb_edit_frame.cpp:1512
|
||||
msgid "Eeschema netlist"
|
||||
msgstr "Eeschema 網表"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1530
|
||||
#: pcbnew/pcb_edit_frame.cpp:1523
|
||||
msgid ""
|
||||
"Received an error while reading netlist. Please report this issue to the "
|
||||
"KiCad team using the menu Help->Report Bug."
|
||||
msgstr ""
|
||||
"讀取網表時收到一個錯誤。 請使用“幫助->報告錯誤”菜單向 KiCad 團隊報告此問題。"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1557
|
||||
#: pcbnew/pcb_edit_frame.cpp:1550
|
||||
#, c-format
|
||||
msgid "Schematic file '%s' not found."
|
||||
msgstr "沒有找到原理圖檔案 '%s'。"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1587
|
||||
#: pcbnew/pcb_edit_frame.cpp:1580
|
||||
msgid "Eeschema failed to load."
|
||||
msgstr "未能載入 Eeschema。"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1738
|
||||
#: pcbnew/pcb_edit_frame.cpp:1731
|
||||
msgid "Edit design rules"
|
||||
msgstr "編輯設計規則"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1750
|
||||
#: pcbnew/pcb_edit_frame.cpp:1743
|
||||
msgid "Could not compile custom design rules."
|
||||
msgstr "無法編譯自定義設計規則。"
|
||||
|
||||
#: pcbnew/pcb_edit_frame.cpp:1785
|
||||
#: pcbnew/pcb_edit_frame.cpp:1778
|
||||
msgid "Export Hyperlynx Layout"
|
||||
msgstr "匯出 Hyperlynx 佈局"
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:95 pcbnew/pcb_expr_evaluator.cpp:264
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:330 pcbnew/pcb_expr_evaluator.cpp:396
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:614 pcbnew/pcb_expr_evaluator.cpp:716
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:829
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:824
|
||||
#, c-format
|
||||
msgid "Missing argument to '%s'"
|
||||
msgstr "缺少 '%s' 的引數"
|
||||
|
|
@ -31090,7 +31087,7 @@ msgstr "封裝沒有頂層外框。"
|
|||
msgid "Footprint has no back courtyard."
|
||||
msgstr "封裝沒有底層外框。"
|
||||
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1152
|
||||
#: pcbnew/pcb_expr_evaluator.cpp:1153
|
||||
msgid "must be mm, in, or mil"
|
||||
msgstr "單位必須為 mm、in 或 mil"
|
||||
|
||||
|
|
@ -36175,6 +36172,10 @@ msgstr "KiCad 原理圖"
|
|||
msgid "KiCad Printed Circuit Board"
|
||||
msgstr "KiCad 印刷電路板"
|
||||
|
||||
#, fuzzy
|
||||
#~ msgid "Net CodewxT( "
|
||||
#~ msgstr "網路碼"
|
||||
|
||||
#~ msgid "Save changes to schematic before closing?"
|
||||
#~ msgstr "是否在關閉前儲存對原理圖的變更？"
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue