drc: use R-Tree intersection for silk clearance tests
This commit is contained in:
Tomasz Wlostowski
parent
b215361b30
commit
2bacfe8202
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@ -38,6 +38,7 @@
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TODO:
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- separate holes to edge check
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- tester only looks for edge crossings. it doesn't check if items are inside/outside the board area.
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- pad test missing!
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*/
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class DRC_TEST_PROVIDER_EDGE_CLEARANCE : public DRC_TEST_PROVIDER_CLEARANCE_BASE
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@ -44,9 +44,6 @@
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Silk to pads clearance test. Check all pads against silkscreen (mask opening in the pad vs silkscreen)
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Errors generated:
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- DRCE_SILK_ON_PADS
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TODO:
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- tester only looks for edge crossings. it doesn't check if items are inside/outside the board area.
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*/
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namespace test {
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@ -106,18 +103,7 @@ bool test::DRC_TEST_PROVIDER_SILK_TO_PAD::Run()
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reportAux( "Worst clearance : %d nm", m_largestClearance );
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reportPhase(( "Pad to silkscreen clearances..." ));
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struct SHAPE_ON_LAYER
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{
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SHAPE_ON_LAYER( std::shared_ptr<SHAPE> aShape, PCB_LAYER_ID aLayer )
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: shape ( aShape ),
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layer ( aLayer )
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{
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}
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std::shared_ptr<SHAPE> shape;
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PCB_LAYER_ID layer;
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};
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DRC_RTREE padTree;
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DRC_RTREE padTree, silkTree;
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auto addPadToTree =
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[&padTree]( BOARD_ITEM *item ) -> bool
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@ -126,106 +112,64 @@ bool test::DRC_TEST_PROVIDER_SILK_TO_PAD::Run()
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return true;
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};
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auto checkClearance =
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[&] ( BOARD_ITEM* refItem ) -> bool
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{
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const PCB_LAYER_ID padOuterLayers[] = { F_Cu, B_Cu };
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const PCB_LAYER_ID padSilkLayers[] = { F_SilkS, B_SilkS };
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for( int i = 0; i < 2; i++ )
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{
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padTree.QueryColliding(
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refItem,
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padSilkLayers[i],
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padOuterLayers[i],
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[&] ( BOARD_ITEM *chkItem ) -> bool
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auto addSilkToTree =
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[&silkTree]( BOARD_ITEM *item ) -> bool
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{
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silkTree.insert( item );
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return true;
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},
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[&] ( BOARD_ITEM *collItem, int distance ) -> bool
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{
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auto constraint = m_drcEngine->EvalRulesForItems( DRC_CONSTRAINT_TYPE_SILK_TO_PAD,
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refItem, collItem );
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};
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auto checkClearance = [&]( const DRC_RTREE::LAYER_PAIR& aLayers,
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DRC_RTREE::ITEM_WITH_SHAPE* aRefItem,
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DRC_RTREE::ITEM_WITH_SHAPE* aTestItem ) -> bool {
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auto constraint = m_drcEngine->EvalRulesForItems(
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DRC_CONSTRAINT_TYPE_SILK_TO_PAD, aRefItem->parent, aTestItem->parent );
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int minClearance = constraint.GetValue().Min();
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if( !distance || distance < minClearance )
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{
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accountCheck( constraint );
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int actual;
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if( ! aRefItem->shape->Collide( aTestItem->shape, minClearance, &actual ) )
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return true;
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_SILK_OVER_PAD );
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wxString msg;
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msg.Printf( drcItem->GetErrorText() + _( " (%s clearance %s; actual %s)" ),
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constraint.GetParentRule()->m_Name,
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MessageTextFromValue( userUnits(), minClearance, true ),
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MessageTextFromValue( userUnits(), distance, true ) );
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drcItem->SetErrorMessage( msg );
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drcItem->SetItems( refItem, collItem );
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drcItem->SetViolatingRule( constraint.GetParentRule() );
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reportViolation( drcItem, refItem->GetPosition() );
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}
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return true;
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},
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m_largestClearance
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);
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}
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return true;
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};
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int numPads = forEachGeometryItem( { PCB_PAD_T }, LSET::AllTechMask() | LSET::AllCuMask(), addPadToTree );
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int numSilk = forEachGeometryItem( { PCB_LINE_T, PCB_MODULE_EDGE_T, PCB_TEXT_T, PCB_MODULE_TEXT_T },
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LSET( 2, F_SilkS, B_SilkS ),
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checkClearance
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);
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reportAux( "Tested %d pads against %d silkscreen features.", numPads, numSilk );
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#if 0
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for( auto& silkShape : boardOutline )
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{
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for( auto& padShape : boardItems )
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{
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// printf("BoardT %d\n", boardItem->Type() );
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auto shape = boardItem->GetEffectiveShape();
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auto constraint = m_drcEngine->EvalRulesForItems( DRC_CONSTRAINT_TYPE_EDGE_CLEARANCE,
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outlineItem, boardItem );
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int minClearance = constraint.GetValue().Min();
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int actual;
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if( refShape->Collide( shape.get(), minClearance, &actual ) )
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{
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_COPPER_EDGE_CLEARANCE );
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wxString msg;
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msg.Printf( drcItem->GetErrorText() + _( " (%s clearance %s; actual %s)" ),
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rule->GetName(),
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MessageTextFromValue( userUnits(), minClearance, true ),
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MessageTextFromValue( userUnits(), actual, true ) );
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drcItem->SetErrorMessage( msg );
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drcItem->SetItems( outlineItem, boardItem );
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drcItem->SetViolatingRule( rule );
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drcItem->SetItems( aRefItem->parent, aTestItem->parent );
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drcItem->SetViolatingRule( constraint.GetParentRule() );
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reportViolation( drcItem, refShape->Centre());
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}
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}
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}
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reportViolation( drcItem, aRefItem->parent->GetPosition() );
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return true;
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#endif
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return !m_drcEngine->IsErrorLimitExceeded( DRCE_SILK_OVER_PAD );
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};
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int numPads = forEachGeometryItem(
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{ PCB_PAD_T }, LSET::AllTechMask() | LSET::AllCuMask(), addPadToTree );
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int numSilk =
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forEachGeometryItem( { PCB_LINE_T, PCB_MODULE_EDGE_T, PCB_TEXT_T, PCB_MODULE_TEXT_T },
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LSET( 2, F_SilkS, B_SilkS ), addSilkToTree );
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reportAux( _("Testing %d pads against %d silkscreen features."), numPads, numSilk );
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const std::vector<DRC_RTREE::LAYER_PAIR> layerPairs =
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{
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DRC_RTREE::LAYER_PAIR( F_SilkS, F_Cu ),
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DRC_RTREE::LAYER_PAIR( B_SilkS, B_Cu )
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};
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padTree.QueryCollidingPairs( &silkTree, layerPairs, checkClearance, m_largestClearance );
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reportRuleStatistics();
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return true;
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}
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@ -0,0 +1,213 @@
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/*
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* This program source code file is part of KiCad, a free EDA CAD application.
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*
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* Copyright (C) 2004-2020 KiCad Developers.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you may find one here:
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* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
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* or you may search the http://www.gnu.org website for the version 2 license,
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* or you may write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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#include <common.h>
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#include <class_board.h>
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#include <class_drawsegment.h>
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#include <class_pad.h>
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#include <convert_basic_shapes_to_polygon.h>
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#include <geometry/polygon_test_point_inside.h>
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#include <geometry/seg.h>
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#include <geometry/shape_poly_set.h>
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#include <geometry/shape_rect.h>
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#include <geometry/shape_segment.h>
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#include <drc/drc_engine.h>
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#include <drc/drc_item.h>
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#include <drc/drc_rule.h>
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#include <drc/drc_test_provider_clearance_base.h>
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#include <drc/drc_rtree.h>
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/*
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Silk to silk clearance test. Check all silkscreen features against each other.
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Errors generated:
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- DRCE_SILK_CLEARANCE
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*/
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namespace test {
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class DRC_TEST_PROVIDER_SILK_TO_SILK : public ::DRC_TEST_PROVIDER
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{
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public:
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DRC_TEST_PROVIDER_SILK_TO_SILK ()
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{
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}
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virtual ~DRC_TEST_PROVIDER_SILK_TO_SILK()
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{
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}
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virtual bool Run() override;
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virtual const wxString GetName() const override
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{
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return "silk_to_silk";
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};
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virtual const wxString GetDescription() const override
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{
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return "Tests for overlapping silkscreen features.";
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}
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virtual int GetNumPhases() const override
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{
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return 1;
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}
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virtual std::set<DRC_CONSTRAINT_TYPE_T> GetConstraintTypes() const override;
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private:
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BOARD* m_board;
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int m_largestClearance;
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};
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};
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bool test::DRC_TEST_PROVIDER_SILK_TO_SILK::Run()
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{
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m_board = m_drcEngine->GetBoard();
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DRC_CONSTRAINT worstClearanceConstraint;
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m_largestClearance = 0;
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if( m_drcEngine->QueryWorstConstraint( DRC_CONSTRAINT_TYPE_SILK_TO_SILK,
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worstClearanceConstraint, DRCCQ_LARGEST_MINIMUM ) )
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{
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m_largestClearance = worstClearanceConstraint.m_Value.Min();
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}
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reportAux( "Worst clearance : %d nm", m_largestClearance );
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reportPhase(( "Silkscreen clearances..." ));
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DRC_RTREE silkTree;
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auto addToTree =
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[&silkTree]( BOARD_ITEM *item ) -> bool
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{
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silkTree.insert( item );
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return true;
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};
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auto checkClearance = [&]( const DRC_RTREE::LAYER_PAIR& aLayers,
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DRC_RTREE::ITEM_WITH_SHAPE* aRefItem,
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DRC_RTREE::ITEM_WITH_SHAPE* aTestItem ) -> bool {
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auto constraint = m_drcEngine->EvalRulesForItems(
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DRC_CONSTRAINT_TYPE_SILK_TO_SILK, aRefItem->parent, aTestItem->parent );
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int minClearance = constraint.GetValue().Min();
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accountCheck( constraint );
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int actual;
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// only check for silkscreen collisions belonging to different modules or overlapping texts
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KICAD_T typeRef = aRefItem->parent->Type();
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KICAD_T typeTest = aTestItem->parent->Type();
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MODULE *parentModRef = nullptr;
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MODULE *parentModTest = nullptr;
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if( typeRef == PCB_MODULE_EDGE_T || typeRef == PCB_MODULE_TEXT_T )
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{
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parentModRef = static_cast<MODULE*> ( aRefItem->parent->GetParent() );
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}
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if( typeTest == PCB_MODULE_EDGE_T || typeTest == PCB_MODULE_TEXT_T )
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{
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parentModTest = static_cast<MODULE*> ( aTestItem->parent->GetParent() );
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}
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// silkscreen drawings within the same module (or globally on the board)
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// don't report clearance errors. Everything else does.
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if( parentModRef && parentModRef == parentModTest )
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{
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if( typeRef == PCB_MODULE_EDGE_T && typeTest == PCB_MODULE_EDGE_T )
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return true;
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}
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if( !parentModRef && !parentModTest )
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{
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if( typeRef == PCB_LINE_T && typeTest == PCB_LINE_T )
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return true;
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}
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if( ! aRefItem->shape->Collide( aTestItem->shape, minClearance, &actual ) )
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return true;
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_SILK_CLEARANCE );
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wxString msg;
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msg.Printf( drcItem->GetErrorText() + _( " (%s clearance %s; actual %s)" ),
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constraint.GetParentRule()->m_Name,
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MessageTextFromValue( userUnits(), minClearance, true ),
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MessageTextFromValue( userUnits(), actual, true ) );
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drcItem->SetErrorMessage( msg );
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drcItem->SetItems( aRefItem->parent, aTestItem->parent );
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drcItem->SetViolatingRule( constraint.GetParentRule() );
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reportViolation( drcItem, aRefItem->parent->GetPosition() );
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return !m_drcEngine->IsErrorLimitExceeded( DRCE_SILK_CLEARANCE );
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};
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int numSilk =
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forEachGeometryItem( { PCB_LINE_T, PCB_MODULE_EDGE_T, PCB_TEXT_T, PCB_MODULE_TEXT_T },
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LSET( 2, F_SilkS, B_SilkS ), addToTree );
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reportAux( _("Testing %d silkscreen features."), numSilk );
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const std::vector<DRC_RTREE::LAYER_PAIR> layerPairs =
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{
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DRC_RTREE::LAYER_PAIR( F_SilkS, F_SilkS ),
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DRC_RTREE::LAYER_PAIR( B_SilkS, B_SilkS )
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};
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silkTree.QueryCollidingPairs( &silkTree, layerPairs, checkClearance, m_largestClearance );
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reportRuleStatistics();
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return true;
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}
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std::set<DRC_CONSTRAINT_TYPE_T> test::DRC_TEST_PROVIDER_SILK_TO_SILK::GetConstraintTypes() const
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{
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return { DRC_CONSTRAINT_TYPE_SILK_TO_SILK };
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}
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namespace detail
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{
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static DRC_REGISTER_TEST_PROVIDER<test::DRC_TEST_PROVIDER_SILK_TO_SILK> dummy;
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}
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