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This commit is contained in:
Maciej Suminski 2017-04-25 11:47:21 +02:00 committed by Tomasz Włostowski
parent 3b16d3cffe
commit 2c68786fa8
4 changed files with 53 additions and 63 deletions
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3
include/layers_id_colors_and_visibility.h
View File

@ -751,7 +751,8 @@ inline int GetNetnameLayer( int aLayer )
return LAYER_PAD_FR_NETNAMES;
else if( aLayer == LAYER_PAD_BK )
return LAYER_PAD_BK_NETNAMES;
// fixme :via names
else if( aLayer >= LAYER_VIA_MICROVIA && aLayer <= LAYER_VIA_THROUGH )
return LAYER_VIAS_NETNAMES;
// Fallback
return Cmts_User;

5
pcbnew/class_track.cpp
View File

@ -990,7 +990,7 @@ void VIA::Draw( EDA_DRAW_PANEL* panel, wxDC* aDC, GR_DRAWMODE aDrawMode, const w
void VIA::ViewGetLayers( int aLayers[], int& aCount ) const
{
aLayers[0] = LAYER_VIAS_HOLES;
aLayers[1] = GetNetnameLayer( m_Layer );
aLayers[1] = LAYER_VIAS_NETNAMES;
aCount = 3;
// Just show it on common via & via holes layers
@ -1012,7 +1012,8 @@ void VIA::ViewGetLayers( int aLayers[], int& aCount ) const
break;
default:
assert( false );
aLayers[2] = LAYER_GP_OVERLAY;
wxASSERT( false );
break;
}
}

20
pcbnew/pcb_draw_panel_gal.cpp
View File

@ -42,9 +42,9 @@ using namespace std::placeholders;
const LAYER_NUM GAL_LAYER_ORDER[] =
{
LAYER_GP_OVERLAY ,
LAYER_GP_OVERLAY,
LAYER_DRC,
LAYER_PADS_NETNAMES,
LAYER_PADS_NETNAMES, LAYER_VIAS_NETNAMES,
Dwgs_User, Cmts_User, Eco1_User, Eco2_User, Edge_Cuts,
LAYER_MOD_TEXT_FR,
@ -194,10 +194,10 @@ void PCB_DRAW_PANEL_GAL::SetHighContrastLayer( PCB_LAYER_ID aLayer )
// fixme do not like the idea of storing the list of layers here,
// should be done in some other way I guess..
LAYER_NUM layers[] = {
GetNetnameLayer( aLayer ), LAYER_VIA_THROUGH,
LAYER_VIAS_HOLES, LAYER_PADS,
LAYER_PADS_HOLES, LAYER_NON_PLATED, LAYER_PADS_NETNAMES,
LAYER_GP_OVERLAY, LAYER_RATSNEST
GetNetnameLayer( aLayer ),
LAYER_VIA_THROUGH, LAYER_VIAS_HOLES, LAYER_VIAS_NETNAMES,
LAYER_PADS, LAYER_PADS_HOLES, LAYER_PADS_NETNAMES,
LAYER_NON_PLATED, LAYER_GP_OVERLAY, LAYER_RATSNEST
};
for( unsigned int i = 0; i < sizeof( layers ) / sizeof( LAYER_NUM ); ++i )
@ -230,10 +230,9 @@ void PCB_DRAW_PANEL_GAL::SetTopLayer( PCB_LAYER_ID aLayer )
// Layers that should always have on-top attribute enabled
const LAYER_NUM layers[] = {
LAYER_VIA_THROUGH,
LAYER_VIAS_HOLES, LAYER_PADS,
LAYER_PADS_HOLES, LAYER_NON_PLATED, LAYER_PADS_NETNAMES,
LAYER_GP_OVERLAY, LAYER_RATSNEST, Dwgs_User,
LAYER_VIA_THROUGH, LAYER_VIAS_HOLES, LAYER_VIAS_NETNAMES,
LAYER_PADS, LAYER_PADS_HOLES, LAYER_PADS_NETNAMES,
LAYER_NON_PLATED, LAYER_GP_OVERLAY, LAYER_RATSNEST, Dwgs_User,
LAYER_DRC
};
@ -401,6 +400,7 @@ void PCB_DRAW_PANEL_GAL::setDefaultLayerDeps()
// Some more required layers settings
m_view->SetRequired( LAYER_VIAS_HOLES, LAYER_VIA_THROUGH );
m_view->SetRequired( LAYER_VIAS_NETNAMES, LAYER_VIA_THROUGH );
m_view->SetRequired( LAYER_PADS_HOLES, LAYER_PADS );
m_view->SetRequired( LAYER_NON_PLATED, LAYER_PADS );
m_view->SetRequired( LAYER_PADS_NETNAMES, LAYER_PADS );

88
pcbnew/pcb_painter.cpp
View File

@ -393,64 +393,52 @@ void PCB_PAINTER::draw( const VIA* aVia, int aLayer )
VECTOR2D center( aVia->GetStart() );
double radius = 0.0;
// Only draw the via if at least one of the layers it crosses is being displayed
BOARD* brd = aVia->GetBoard( );
if( !( brd->GetVisibleLayers() & aVia->GetLayerSet() ).any() )
return;
// Draw description layer
if( IsNetnameLayer( aLayer ) )
{
VECTOR2D position( center );
// Draw description layer
if( IsNetnameLayer( aLayer ) )
// Is anything that we can display enabled?
if( m_pcbSettings.m_netNamesOnVias )
{
VECTOR2D position( center );
bool displayNetname = ( !aVia->GetNetname().empty() );
double maxSize = PCB_RENDER_SETTINGS::MAX_FONT_SIZE;
double size = aVia->GetWidth();
// Is anything that we can display enabled?
if( m_pcbSettings.m_netNamesOnVias )
// Font size limits
if( size > maxSize )
size = maxSize;
m_gal->Save();
m_gal->Translate( position );
// Default font settings
m_gal->ResetTextAttributes();
m_gal->SetStrokeColor( m_pcbSettings.GetColor( NULL, aLayer ) );
// Set the text position to the pad shape position (the pad position is not the best place)
VECTOR2D textpos( 0.0, 0.0 );
if( displayNetname )
{
bool displayNetname = ( !aVia->GetNetname().empty() );
double maxSize = PCB_RENDER_SETTINGS::MAX_FONT_SIZE;
double size = aVia->GetWidth();
// calculate the size of net name text:
double tsize = 1.5 * size / aVia->GetShortNetname().Length();
tsize = std::min( tsize, size );
// Use a smaller text size to handle interline, pen size..
tsize *= 0.7;
VECTOR2D namesize( tsize, tsize );
// Font size limits
if( size > maxSize )
size = maxSize;
m_gal->Save();
m_gal->Translate( position );
// Default font settings
m_gal->SetHorizontalJustify( GR_TEXT_HJUSTIFY_CENTER );
m_gal->SetVerticalJustify( GR_TEXT_VJUSTIFY_CENTER );
m_gal->SetFontBold( false );
m_gal->SetFontItalic( false );
m_gal->SetTextMirrored( false );
m_gal->SetStrokeColor( m_pcbSettings.GetColor( NULL, aLayer ) );
m_gal->SetIsStroke( true );
m_gal->SetIsFill( false );
// Set the text position to the pad shape position (the pad position is not the best place)
VECTOR2D textpos( 0.0, 0.0 );
if( displayNetname )
{
// calculate the size of net name text:
double tsize = 1.5 * size / aVia->GetShortNetname().Length();
tsize = std::min( tsize, size );
// Use a smaller text size to handle interline, pen size..
tsize *= 0.7;
VECTOR2D namesize( tsize, tsize );
m_gal->SetGlyphSize( namesize );
m_gal->SetLineWidth( namesize.x / 12.0 );
m_gal->BitmapText( aVia->GetShortNetname(), textpos, 0.0 );
}
m_gal->Restore();
m_gal->SetGlyphSize( namesize );
m_gal->SetLineWidth( namesize.x / 12.0 );
m_gal->BitmapText( aVia->GetShortNetname(), textpos, 0.0 );
}
return;
}
m_gal->Restore();
}
return;
}
// Choose drawing settings depending on if we are drawing via's pad or hole
if( aLayer == LAYER_VIAS_HOLES )
radius = aVia->GetDrillValue() / 2.0;