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Fix issue in GPcb footprints import. 

Better code in test connections in zones.
Very minor other fixes
This commit is contained in:
jean-pierre charras 2011-12-22 09:07:50 +01:00
parent 85d2f2f1d5
commit 2df818b844
12 changed files with 1138 additions and 1119 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2078
demos/interf_u/interf_u.brd
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File diff suppressed because it is too large Load Diff

3
eeschema/files-io.cpp
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@ -75,7 +75,8 @@ bool SCH_EDIT_FRAME::SaveEEFile( SCH_SCREEN* aScreen, int aSaveType, bool aCreat
if( schematicFileName.FileExists() )
{
backupFileName.SetExt( g_SchematicBackupFileExtension );
wxRemoveFile( backupFileName.GetFullPath() );
if( backupFileName.FileExists() )
wxRemoveFile( backupFileName.GetFullPath() );
if( !wxRenameFile( schematicFileName.GetFullPath(), backupFileName.GetFullPath() ) )
{

14
eeschema/sch_collectors.cpp
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@ -408,20 +408,22 @@ wxString SCH_FIND_COLLECTOR::GetText()
SCH_FIND_COLLECTOR_DATA data = m_data[ m_foundIndex ];
EDA_ITEM* foundItem = m_List[ m_foundIndex ];
wxCHECK_MSG( foundItem != NULL, wxEmptyString, wxT( "Inavalid found item pointer." ) );
wxCHECK_MSG( foundItem != NULL, wxEmptyString, wxT( "Invalid found item pointer." ) );
wxString msg;
if( data.GetParent() )
{
msg = _( "Child item " ) + foundItem->GetSelectMenuText() +
_( " of parent item " ) + data.GetParent()->GetSelectMenuText() +
_( " found in sheet " ) + data.GetSheetPath();
msg.Printf( _( "Child item %s of parent item %s found in sheet %s" ),
GetChars( foundItem->GetSelectMenuText() ),
GetChars( data.GetParent()->GetSelectMenuText() ),
GetChars( data.GetSheetPath() ) );
}
else
{
msg = _( "Item " ) + foundItem->GetSelectMenuText() + _( " found in sheet " ) +
data.GetSheetPath();
msg.Printf( _( "Item %s found in sheet %s" ),
GetChars( foundItem->GetSelectMenuText() ),
GetChars( data.GetSheetPath() ) );
}
return msg;

4
pcbnew/connect.cpp
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@ -856,8 +856,6 @@ void PCB_BASE_FRAME::TestConnections()
m_Pcb->Test_Connections_To_Copper_Areas();
// int st = clock(); // For test only, will be removed
// Test existing connections net by net
// note some nets can have no tracks, and pads intersecting
// so Build_CurrNet_SubNets_Connections must be called for each net
@ -889,8 +887,6 @@ void PCB_BASE_FRAME::TestConnections()
for( int net = last_net_tested+1; net < netsCount; net++ )
connections.Build_CurrNet_SubNets_Connections( NULL, NULL, net );
// wxLogMessage("time %g ms", (double)(clock() - st)*1000.0/CLOCKS_PER_SEC);
Merge_SubNets_Connected_By_CopperAreas( m_Pcb );
return;

6
pcbnew/files.cpp
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@ -299,10 +299,10 @@ this file again." ) );
}
}
catch( IO_ERROR ioe )
{
{wxMessageBox("catch");
wxString msg = wxString::Format( _( "Error loading board.\n%s" ),
ioe.errorText.GetData() );
wxMessageBox( msg, _( "Open Board File" ), wxICON_ERROR | wxOK );
wxMessageBox( msg, _( "Open Board File" ), wxOK | wxICON_ERROR );
}
if( !aAppend )
@ -490,7 +490,7 @@ bool PCB_EDIT_FRAME::SavePcbFile( const wxString& aFileName, bool aCreateBackupF
{
wxString msg = wxString::Format( _( "Error saving board.\n%s" ),
ioe.errorText.GetData() );
wxMessageBox( msg, _( "Save Board File" ), wxICON_ERROR );
wxMessageBox( msg, _( "Save Board File" ), wxICON_ERROR | wxOK );
saveok = false;
}

29
pcbnew/gpcb_exchange.cpp
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@ -251,16 +251,17 @@ bool MODULE::Read_GPCB_Descr( const wxString& CmpFullFileName )
pos.y = wxRound( ibuf[idx+1] * conv_unit );
m_Reference->SetPos( pos );
m_Reference->SetPos0( pos );
m_Reference->m_Orient = ibuf[idx+2] ? 900 : 0;
m_Reference->SetOrientation( ibuf[idx+2] ? 900 : 0 );
// Calculate size: default is 40 mils (400 pcb units)
// real size is: default * ibuf[idx+3] / 100 (size in gpcb is given in percent of default size
int tsize = ( ibuf[idx+3] * TEXT_DEFAULT_SIZE ) / 100;
int thickness = m_Reference->m_Size.x / 6;
m_Reference->m_Size.x = m_Reference->m_Size.y = MAX( 40, tsize );
tsize = MAX( 40, tsize );
m_Reference->SetSize( wxSize( tsize, tsize ) );
m_Reference->m_Thickness = thickness;
m_Value->m_Orient = m_Reference->m_Orient;
m_Value->m_Size = m_Reference->m_Size;
m_Value->SetOrientation( m_Reference->GetOrientation() );
m_Value->SetSize( m_Reference->GetSize() );
m_Value->m_Thickness = m_Reference->m_Thickness;
pos.y += tsize + thickness;
m_Value->SetPos( pos );
@ -421,11 +422,14 @@ bool MODULE::Read_GPCB_Descr( const wxString& CmpFullFileName )
// Negate angle (due to Y reversed axis) and convert it to internal units
angle = - angle * 1800.0 / M_PI;
Pad->SetOrientation( wxRound( angle ) );
Pad->m_Pos.x = (ibuf[0] + ibuf[2]) / 2;
Pad->m_Pos.y = (ibuf[1] + ibuf[3]) / 2;
wxPoint padPos;
padPos.x = (ibuf[0] + ibuf[2]) / 2;
padPos.y = (ibuf[1] + ibuf[3]) / 2;
Pad->m_Size.x = wxRound( hypot( (double)delta.x, (double)delta.y ) ) + ibuf[4];
Pad->m_Size.y = ibuf[4];
Pad->m_Pos += m_Pos;
padPos += m_Pos;
Pad->SetPos0( padPos );
Pad->SetPosition( padPos );
if( !TestFlags( params[iflgidx], 0x0100, wxT( "square" ) ) )
{
@ -478,13 +482,14 @@ bool MODULE::Read_GPCB_Descr( const wxString& CmpFullFileName )
{
Pad->SetPadName( params[9] );
}
Pad->m_Pos.x = ibuf[0];
Pad->m_Pos.y = ibuf[1];
wxPoint padPos;
padPos.x = ibuf[0];
padPos.y = ibuf[1];
Pad->m_Drill.x = Pad->m_Drill.y = ibuf[5];
Pad->m_Size.x = Pad->m_Size.y = ibuf[3] + Pad->m_Drill.x;
Pad->m_Pos.x += m_Pos.x;
Pad->m_Pos.y += m_Pos.y;
padPos += m_Pos;
Pad->SetPos0( padPos );
Pad->SetPosition( padPos );
if( (Pad->m_PadShape == PAD_ROUND) && (Pad->m_Size.x != Pad->m_Size.y) )
Pad->m_PadShape = PAD_OVAL;

2
pcbnew/ioascii.cpp
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@ -349,7 +349,7 @@ int PCB_BASE_FRAME::ReadSetup( LINE_READER* aReader )
msg.Printf( _( "Error reading PcbPlotParams from %s:\n%s" ),
aReader->GetSource().GetData(),
e.errorText.GetData() );
wxMessageBox( msg, _( "Open Board File" ), wxICON_ERROR );
wxMessageBox( msg, _( "Open Board File" ), wxOK | wxICON_ERROR );
}
continue;

2
pcbnew/muonde.cpp
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@ -937,7 +937,6 @@ MODULE* PCB_EDIT_FRAME::Create_MuWavePolygonShape()
wxString cmp_name;
int pad_count = 2;
EDGE_MODULE* edge;
int npoints;
WinEDA_SetParamShapeFrame* frame = new WinEDA_SetParamShapeFrame( this, wxPoint( -1, -1 ) );
@ -988,7 +987,6 @@ MODULE* PCB_EDIT_FRAME::Create_MuWavePolygonShape()
edge->SetShape( S_POLYGON );
edge->SetLayer( LAYER_N_FRONT );
npoints = PolyEdges.size();
std::vector<wxPoint> polyPoints = edge->GetPolyPoints();
polyPoints.reserve( 2 * PolyEdges.size() + 2 );

7
pcbnew/pcbplot.cpp
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@ -291,7 +291,7 @@ void DIALOG_PLOT::OnOutputDirectoryBrowseClicked( wxCommandEvent& event )
if( !dirName.MakeRelativeTo( boardFilePath ) )
wxMessageBox( wxT( "Cannot make path relative (target volume different from board file volume)!" ),
wxT( "Plot Output Directory" ), wxICON_ERROR );
wxT( "Plot Output Directory" ), wxOK | wxICON_ERROR );
}
m_outputDirectoryName->SetValue( dirName.GetFullPath() );
@ -568,7 +568,7 @@ void DIALOG_PLOT::Plot( wxCommandEvent& event )
msg.Printf( wxT( " Cannot make %s absolute with respect to %s!" ),
GetChars( outputDir.GetPath() ),
GetChars( boardFilePath ) );
wxMessageBox( msg, wxT( "Plot" ), wxICON_ERROR );
wxMessageBox( msg, wxT( "Plot" ), wxOK | wxICON_ERROR );
return;
}
@ -582,7 +582,8 @@ void DIALOG_PLOT::Plot( wxCommandEvent& event )
}
else
{
wxMessageBox( wxT( "Cannot create output directory!" ), wxT( "Plot" ), wxICON_ERROR );
wxMessageBox( wxT( "Cannot create output directory!" ),
wxT( "Plot" ), wxOK | wxICON_ERROR );
return;
}
}

6
pcbnew/xchgmod.cpp
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@ -151,7 +151,6 @@ int DIALOG_EXCHANGE_MODULE::Maj_ListeCmp( const wxString& reference,
FILE* FichCmp, * NewFile;
char line[1024];
wxString msg;
char* rs;
if( old_name == new_name )
return 0;
@ -189,7 +188,7 @@ int DIALOG_EXCHANGE_MODULE::Maj_ListeCmp( const wxString& reference,
return 1;
}
rs = fgets( line, sizeof(line), FichCmp );
fgets( line, sizeof(line), FichCmp );
fprintf( NewFile, "Cmp-Mod V01 Genere par PcbNew le %s\n", TO_UTF8( DateAndTime() ) );
@ -587,7 +586,6 @@ void PCB_EDIT_FRAME::RecreateCmpFileFromBoard( wxCommandEvent& aEvent )
MODULE* Module = GetBoard()->m_Modules;
wxString msg;
wxString wildcard;
char* rs;
if( Module == NULL )
{
@ -618,7 +616,7 @@ void PCB_EDIT_FRAME::RecreateCmpFileFromBoard( wxCommandEvent& aEvent )
return;
}
rs = fgets( line, sizeof(line), FichCmp );
fgets( line, sizeof(line), FichCmp );
fprintf( FichCmp, "Cmp-Mod V01 Genere par PcbNew le %s\n", TO_UTF8( DateAndTime() ) );
for( ; Module != NULL; Module = Module->Next() )

104
pcbnew/zones_polygons_test_connections.cpp
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@ -31,11 +31,9 @@ void Merge_SubNets_Connected_By_CopperAreas( BOARD* aPcb, int aNetcode );
void BOARD::Test_Connections_To_Copper_Areas( int aNetcode )
{
// list of pads and tracks candidates on this layer and on this net.
std::vector <BOARD_CONNECTED_ITEM*> Candidates;
int subnet = 0;
int netcode;
ZONE_CONTAINER* curr_zone;
BOARD_CONNECTED_ITEM* item;
// It is static to avoid multiple memory realloc.
static std::vector <BOARD_CONNECTED_ITEM*> Candidates;
// clear .m_ZoneSubnet parameter for pads
for( MODULE* module = m_Modules; module; module = module->Next() )
@ -53,13 +51,14 @@ void BOARD::Test_Connections_To_Copper_Areas( int aNetcode )
}
// examine all zones, net by net:
int subnet = 0;
for( int index = 0; index < GetAreaCount(); index++ )
{
curr_zone = GetArea( index );
ZONE_CONTAINER* curr_zone = GetArea( index );
if( !curr_zone->IsOnCopperLayer() )
continue;
netcode = curr_zone->GetNet();
int netcode = curr_zone->GetNet();
if( (aNetcode >= 0) && !( aNetcode == netcode ) )
continue;
@ -71,21 +70,22 @@ void BOARD::Test_Connections_To_Copper_Areas( int aNetcode )
// At this point, layers are not considered, because areas on different layers can
// be connected by a via or a pad.
for( MODULE* module = m_Modules; module; module = module->Next() )
{
for( D_PAD* pad = module->m_Pads; pad != NULL; pad = pad->Next() )
{
if( pad->GetNet() != curr_zone->GetNet() )
continue;
Candidates.push_back( pad );
}
}
// Build the list of pads candidates connected to the net:
NETINFO_ITEM* net = FindNet( netcode );
wxASSERT( net );
if( net == NULL )
continue;
Candidates.reserve( net->m_PadInNetList.size() );
for( unsigned ii = 0; ii < net->m_PadInNetList.size(); ii++ )
Candidates.push_back( net->m_PadInNetList[ii] );
for( TRACK* track = m_Track; track; track = track->Next() )
// Build the list of track candidates connected to the net:
TRACK* track = m_Track.GetFirst()->GetStartNetCode( netcode );
for( ; track; track = track->Next() )
{
if( track->GetNet() != netcode )
continue;
break;
Candidates.push_back( track );
}
@ -102,7 +102,7 @@ void BOARD::Test_Connections_To_Copper_Areas( int aNetcode )
for( unsigned ic = 0; ic < Candidates.size(); ic++ )
{ // test if this area is connected to a board item:
item = Candidates[ic];
BOARD_CONNECTED_ITEM* item = Candidates[ic];
if( !item->IsOnLayer( curr_zone->GetLayer() ) )
continue;
@ -212,10 +212,6 @@ void Merge_SubNets_Connected_By_CopperAreas( BOARD* aPcb )
*/
void Merge_SubNets_Connected_By_CopperAreas( BOARD* aPcb, int aNetcode )
{
BOARD_CONNECTED_ITEM* item;
int old_subnet, subnet, next_subnet_free_number;
int old_zone_subnet, zone_subnet;
// Ensure a zone with the given netcode exists: examine all zones:
bool found = false;
@ -233,35 +229,38 @@ void Merge_SubNets_Connected_By_CopperAreas( BOARD* aPcb, int aNetcode )
if( !found ) // No zone with this netcode, therefore no connection by zone
return;
std::vector <BOARD_CONNECTED_ITEM*> Candidates; // list of pads and tracks candidates to test.
// list of pads and tracks candidates to test:
// It is static to avoid multiple memory realloc.
static std::vector <BOARD_CONNECTED_ITEM*> Candidates;
Candidates.clear();
// Build a list of candidates connected to the net:
next_subnet_free_number = 0;
// Build the list of pads candidates connected to the net:
NETINFO_ITEM* net = aPcb->FindNet( aNetcode );
wxASSERT( net );
Candidates.reserve( net->m_PadInNetList.size() );
for( unsigned ii = 0; ii < net->m_PadInNetList.size(); ii++ )
Candidates.push_back( net->m_PadInNetList[ii] );
for( MODULE* module = aPcb->m_Modules; module; module = module->Next() )
// Build the list of track candidates connected to the net:
TRACK* track;
track = aPcb->m_Track.GetFirst()->GetStartNetCode( aNetcode );
for( ; track; track = track->Next() )
{
for( D_PAD* pad = module->m_Pads; pad != NULL; pad = pad->Next() )
{
if( pad->GetNet() == aNetcode )
{
Candidates.push_back( pad );
next_subnet_free_number = MAX( next_subnet_free_number, pad->GetSubNet() );
}
}
}
for( TRACK* track = aPcb->m_Track; track; track = track->Next() )
{
if( track->GetNet() == aNetcode )
{
Candidates.push_back( track );
next_subnet_free_number = MAX( next_subnet_free_number, track->GetSubNet() );
}
if( track->GetNet() != aNetcode )
break;
Candidates.push_back( track );
}
if( Candidates.size() == 0 )
return;
int next_subnet_free_number = 0;
for( unsigned ii = 0; ii < Candidates.size(); ii++ )
{
int subnet = Candidates[ii]->GetSubNet();
next_subnet_free_number = MAX( next_subnet_free_number, subnet );
}
next_subnet_free_number++; // This is a subnet we can use with not connected items
// by tracks, but connected by zone.
@ -269,12 +268,12 @@ void Merge_SubNets_Connected_By_CopperAreas( BOARD* aPcb, int aNetcode )
sort( Candidates.begin(), Candidates.end(), CmpZoneSubnetValue );
// Some items can be not connected, but they can be connected to a filled area:
// give them a subnet common to these items connected only by the area, and not already used.
// give them a subnet common to these items connected only by the area,
// and not already used.
// a value like next_subnet_free_number+zone_subnet is right
for( unsigned jj = 0; jj < Candidates.size(); jj++ )
{
item = Candidates[jj];
BOARD_CONNECTED_ITEM* item = Candidates[jj];
if ( item->GetSubNet() == 0 && (item->GetZoneSubNet() > 0) )
{
item->SetSubNet( next_subnet_free_number + item->GetZoneSubNet() );
@ -283,18 +282,17 @@ void Merge_SubNets_Connected_By_CopperAreas( BOARD* aPcb, int aNetcode )
// Now, for each zone subnet, we search for 2 items with different subnets.
// if found, the 2 subnet are merged in the whole candidate list.
old_subnet = 0;
old_zone_subnet = 0;
int old_subnet = 0;
int old_zone_subnet = 0;
for( unsigned ii = 0; ii < Candidates.size(); ii++ )
{
item = Candidates[ii];
zone_subnet = item->GetZoneSubNet();
BOARD_CONNECTED_ITEM* item = Candidates[ii];
int zone_subnet = item->GetZoneSubNet();
if( zone_subnet == 0 ) // Not connected by a filled area, skip it
continue;
subnet = item->GetSubNet();
int subnet = item->GetSubNet();
if( zone_subnet != old_zone_subnet ) // a new zone subnet is found
{

2
polygon/PolyLine.cpp
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@ -478,7 +478,7 @@ int CPolyLine::MakeKboolPoly( int aStart_contour, int aEnd_contour, std::vector<
x = x1;
y = y1;
}
booleng->AddPoint( x1, y1 );
booleng->AddPoint( x, y );
ivtx++;
}
}