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QA: refill zones in issue5990.kicad_pcb

This commit is contained in:
Alex Shvartzkop 2023-09-13 14:38:25 +03:00
parent 72737b20cd
commit 36a4d5a511
2 changed files with 11298 additions and 11474 deletions
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22689
qa/data/pcbnew/issue5990.kicad_pcb
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83
qa/data/pcbnew/issue5990.kicad_pro
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@ -1,5 +1,6 @@
{
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {
"board_outline_line_width": 0.15239999999999998,
@ -62,6 +63,7 @@
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"connection_width": "warning",
"copper_edge_clearance": "error",
"copper_sliver": "warning",
"courtyards_overlap": "error",
@ -70,13 +72,17 @@
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint": "error",
"footprint_type_mismatch": "ignore",
"hole_clearance": "error",
"hole_near_hole": "error",
"invalid_outline": "error",
"isolated_copper": "warning",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"lib_footprint_issues": "ignore",
"lib_footprint_mismatch": "ignore",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
@ -86,13 +92,15 @@
"padstack": "error",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_edge_clearance": "warning",
"silk_over_copper": "error",
"silk_overlap": "error",
"skew_out_of_range": "error",
"solder_mask_bridge": "ignore",
"solder_mask_bridge": "error",
"starved_thermal": "error",
"text_height": "warning",
"text_thickness": "warning",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
"track_dangling": "warning",
"track_width": "error",
@ -100,7 +108,6 @@
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zone_has_empty_net": "error",
"zones_intersect": "error"
},
"rules": {
@ -108,6 +115,7 @@
"allow_microvias": false,
"max_error": 0.005,
"min_clearance": 0.2032,
"min_connection": 0.0,
"min_copper_edge_clearance": 0.3,
"min_hole_clearance": 0.0,
"min_hole_to_hole": 0.25,
@ -122,8 +130,49 @@
"min_via_annular_width": 0.049999999999999996,
"min_via_annulus": 0.15,
"min_via_diameter": 0.6,
"solder_mask_to_copper_clearance": 0.0,
"use_height_for_length_calcs": true
},
"teardrop_options": [
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 5,
"td_on_pad_in_zone": false,
"td_onpadsmd": true,
"td_onroundshapesonly": false,
"td_ontrackend": false,
"td_onviapad": true
}
],
"teardrop_parameters": [
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_round_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_rect_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_track_end",
"td_width_to_size_filter_ratio": 0.9
}
],
"track_widths": [
0.0,
0.254,
@ -167,7 +216,8 @@
"zones_allow_external_fillets": false,
"zones_use_no_outline": false
},
"layer_presets": []
"layer_presets": [],
"viewports": []
},
"boards": [],
"cvpcb": {
@ -357,7 +407,7 @@
"net_settings": {
"classes": [
{
"bus_width": 12.0,
"bus_width": 12,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
@ -371,10 +421,10 @@
"track_width": 0.254,
"via_diameter": 0.6,
"via_drill": 0.3,
"wire_width": 6.0
"wire_width": 6
},
{
"bus_width": 6.0,
"bus_width": 6,
"clearance": 0.4,
"diff_pair_gap": 0.2032,
"diff_pair_via_gap": 0.25,
@ -383,16 +433,15 @@
"microvia_diameter": 0.6,
"microvia_drill": 0.3,
"name": "100V",
"nets": [],
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.254,
"via_diameter": 0.6,
"via_drill": 0.3,
"wire_width": 6.0
"wire_width": 6
},
{
"bus_width": 6.0,
"bus_width": 6,
"clearance": 0.8,
"diff_pair_gap": 0.508,
"diff_pair_via_gap": 0.25,
@ -401,22 +450,26 @@
"microvia_diameter": 0.6,
"microvia_drill": 0.3,
"name": "170V",
"nets": [
"/170V"
],
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.4064,
"via_diameter": 0.6,
"via_drill": 0.3,
"wire_width": 6.0
"wire_width": 6
}
],
"hidden_nets": [],
"meta": {
"version": 1
"version": 3
},
"net_colors": null
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": [
{
"netclass": "170V",
"pattern": "/170V"
}
]
},
"pcbnew": {
"last_paths": {