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Showing net names on pads.

This commit is contained in:
Maciej Suminski 2013-07-08 11:30:50 +02:00
parent 032ef3a74c
commit 3841b0ac3a
7 changed files with 114 additions and 19 deletions
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5
include/layers_id_colors_and_visibility.h
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@ -216,8 +216,9 @@ enum PCB_VISIBLE
TRACKS_VISIBLE,
TRACKS_NETNAMES_VISIBLE,
PADS_VISIBLE,
VIA_HOLES_VISIBLE,
PAD_HOLES_VISIBLE,
PADS_NETNAMES_VISIBLE,
PADS_HOLES_VISIBLE,
VIAS_HOLES_VISIBLE,
END_PCB_VISIBLE_LIST // sentinel
};

4
pcbnew/basepcbframe.cpp
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@ -94,7 +94,8 @@ const int m_galLayerOrder[] =
ITEM_GAL_LAYER( MOD_REFERENCES_VISIBLE), ITEM_GAL_LAYER( MOD_VALUES_VISIBLE ),
SILKSCREEN_N_FRONT, SOLDERPASTE_N_FRONT, ADHESIVE_N_FRONT, SOLDERMASK_N_FRONT,
ITEM_GAL_LAYER( VIA_HOLES_VISIBLE ), ITEM_GAL_LAYER( PAD_HOLES_VISIBLE ),
ITEM_GAL_LAYER( PADS_NETNAMES_VISIBLE ),
ITEM_GAL_LAYER( VIAS_HOLES_VISIBLE ), ITEM_GAL_LAYER( PADS_HOLES_VISIBLE ),
ITEM_GAL_LAYER( VIAS_VISIBLE ), ITEM_GAL_LAYER( PADS_VISIBLE ),
ITEM_GAL_LAYER( TRACKS_NETNAMES_VISIBLE ), ITEM_GAL_LAYER( PAD_FR_VISIBLE ),
@ -227,6 +228,7 @@ void PCB_BASE_FRAME::SetBoard( BOARD* aBoard )
// Netnames are drawn only when scale is sufficient (level of details)
// so there is no point in caching them
view->SetLayerCached( ITEM_GAL_LAYER( TRACKS_NETNAMES_VISIBLE ), false );
view->SetLayerCached( ITEM_GAL_LAYER( PADS_NETNAMES_VISIBLE ), false );
// Load layer & elements visibility settings
for( unsigned int i = 0; i < NB_LAYERS; ++i )

44
pcbnew/class_pad.cpp
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@ -746,36 +746,36 @@ EDA_ITEM* D_PAD::Clone() const
void D_PAD::ViewGetLayers( int aLayers[], int& aCount ) const
{
if( m_Attribute == PAD_SMD || m_Attribute == PAD_CONN)
aCount = 0;
if( m_Attribute == PAD_SMD || m_Attribute == PAD_CONN )
{
// Single layer pad (smd) without hole
if( IsOnLayer( LAYER_N_FRONT ) )
aLayers[0] = ITEM_GAL_LAYER( PAD_FR_VISIBLE );
aLayers[aCount++] = ITEM_GAL_LAYER( PAD_FR_VISIBLE );
else if( IsOnLayer( LAYER_N_BACK ) )
aLayers[0] = ITEM_GAL_LAYER( PAD_BK_VISIBLE );
aLayers[aCount++] = ITEM_GAL_LAYER( PAD_BK_VISIBLE );
#ifdef __WXDEBUG__
else // Should not occur
{
wxLogWarning( wxT("D_PAD::ViewGetLayers():PAD on layer different than FRONT/BACK") );
}
#endif
aCount = 1;
}
else
{
if( IsOnLayer( LAYER_N_FRONT ) && IsOnLayer( LAYER_N_BACK ) )
{
// Multi layer pad
aLayers[0] = ITEM_GAL_LAYER( PADS_VISIBLE );
aLayers[aCount++] = ITEM_GAL_LAYER( PADS_VISIBLE );
}
else if( IsOnLayer( LAYER_N_FRONT ) )
{
aLayers[0] = ITEM_GAL_LAYER( PAD_FR_VISIBLE );
aLayers[aCount++] = ITEM_GAL_LAYER( PAD_FR_VISIBLE );
}
else if( IsOnLayer( LAYER_N_BACK ) )
{
aLayers[0] = ITEM_GAL_LAYER( PAD_BK_VISIBLE );
aLayers[aCount++] = ITEM_GAL_LAYER( PAD_BK_VISIBLE );
}
#ifdef __WXDEBUG__
else // Should not occur
@ -785,9 +785,31 @@ void D_PAD::ViewGetLayers( int aLayers[], int& aCount ) const
#endif
// Draw a hole
aLayers[1] = ITEM_GAL_LAYER( PAD_HOLES_VISIBLE );
aCount = 2;
aLayers[aCount++] = ITEM_GAL_LAYER( PADS_HOLES_VISIBLE );
}
// Pad description layer (number & net)
aLayers[aCount++] = ITEM_GAL_LAYER( PADS_NETNAMES_VISIBLE );
}
void D_PAD::ViewGetRequiredLayers( int aLayers[], int& aCount ) const
{
ViewGetLayers( aLayers, aCount );
// Remove pad description layer from the required layers group
aCount--;
}
unsigned int D_PAD::ViewGetLOD( int aLayer ) const
{
// Netnames will be shown only if zoom is appropriate
if( aLayer == ITEM_GAL_LAYER( PADS_NETNAMES_VISIBLE ) )
{
return ( 100000000 / std::max( m_Size.x, m_Size.y ) );
}
// Other layers are shown without any conditions
return 0;
}

6
pcbnew/class_pad.h
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@ -433,6 +433,12 @@ public:
/// @copydoc VIEW_ITEM::ViewGetLayers()
virtual void ViewGetLayers( int aLayers[], int& aCount ) const;
/// @copydoc VIEW_ITEM::ViewGetRequiredLayers()
virtual void ViewGetRequiredLayers( int aLayers[], int& aCount ) const;
/// @copydoc VIEW_ITEM::ViewGetLOD()
virtual unsigned int ViewGetLOD( int aLayer ) const;
/**
* Function CopyNetlistSettings
* copies the netlist settings to \a aPad.

2
pcbnew/class_track.cpp
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@ -996,7 +996,7 @@ void SEGVIA::ViewGetLayers( int aLayers[], int& aCount ) const
{
// Just show it on common via & via holes layers
aLayers[0] = ITEM_GAL_LAYER( VIAS_VISIBLE );
aLayers[1] = ITEM_GAL_LAYER( VIA_HOLES_VISIBLE );
aLayers[1] = ITEM_GAL_LAYER( VIAS_HOLES_VISIBLE );
aCount = 2;
}

70
pcbnew/pcb_painter.cpp
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@ -68,8 +68,8 @@ void PCB_RENDER_SETTINGS::ImportLegacyColors( COLORS_DESIGN_SETTINGS* aSettings
}
// Default colors for specific layers
m_itemColors[VIA_HOLES_VISIBLE] = COLOR4D( 0.5, 0.4, 0.0, 1.0 );
m_itemColors[PAD_HOLES_VISIBLE] = COLOR4D( 0.0, 0.5, 0.5, 1.0 );
m_itemColors[VIAS_HOLES_VISIBLE] = COLOR4D( 0.5, 0.4, 0.0, 1.0 );
m_itemColors[PADS_HOLES_VISIBLE] = COLOR4D( 0.0, 0.5, 0.5, 1.0 );
m_itemColors[VIAS_VISIBLE] = COLOR4D( 0.7, 0.7, 0.7, 1.0 );
m_itemColors[PADS_VISIBLE] = COLOR4D( 0.7, 0.7, 0.7, 1.0 );
m_itemColors[TRACKS_NETNAMES_VISIBLE] = COLOR4D( 0.9, 0.9, 0.9, 1.0 );
@ -321,7 +321,7 @@ void PCB_PAINTER::draw( const SEGVIA* aVia, int aLayer )
{
radius = aVia->GetWidth() / 2.0;
}
else if( aLayer == ITEM_GAL_LAYER( VIA_HOLES_VISIBLE ) )
else if( aLayer == ITEM_GAL_LAYER( VIAS_HOLES_VISIBLE ) )
{
radius = aVia->GetDrillValue() / 2.0;
}
@ -354,11 +354,73 @@ void PCB_PAINTER::draw( const D_PAD* aPad, int aLayer )
{
COLOR4D color;
VECTOR2D size;
VECTOR2D position( aPad->GetPosition() );
PAD_SHAPE_T shape;
double m, n;
double orientation = aPad->GetOrientation();
NORMALIZE_ANGLE_90( orientation ); // do not display descriptions upside down
orientation = orientation * M_PI / 1800.0;
color = getLayerColor( aLayer, aPad->GetNet() );
// Draw description layer
if( aLayer == ITEM_GAL_LAYER( PADS_NETNAMES_VISIBLE ) )
{
size = VECTOR2D( aPad->GetSize() / 2 );
// Font size limits
if( size.x > PCB_RENDER_SETTINGS::MAX_FONT_SIZE )
size.x = PCB_RENDER_SETTINGS::MAX_FONT_SIZE;
if( size.y > PCB_RENDER_SETTINGS::MAX_FONT_SIZE )
size.y = PCB_RENDER_SETTINGS::MAX_FONT_SIZE;
// Keep the size ratio for the font, but make it smaller
if( size.x < size.y )
{
orientation -= M_PI / 2;
size.y = size.x * 4.0 / 3.0;
}
else
{
size.x = size.y * 3.0 / 4.0;
}
m_gal->Save();
m_gal->Translate( position );
m_gal->Rotate( -orientation );
// Default font settings
m_gal->SetHorizontalJustify( GR_TEXT_HJUSTIFY_CENTER );
m_gal->SetVerticalJustify( GR_TEXT_VJUSTIFY_CENTER );
m_gal->SetBold( false );
m_gal->SetItalic( false );
m_gal->SetMirrored( false );
m_gal->SetStrokeColor( color );
// Let's make some space for a netname too, if there's one to display
if( !aPad->GetNetname().empty() )
{
size = size / 2.0;
m_gal->SetGlyphSize( size );
m_gal->SetLineWidth( size.y / 10.0 );
m_gal->StrokeText( std::string( aPad->GetNetname().mb_str() ),
VECTOR2D( 0, size.y ), 0.0 );
m_gal->Translate( VECTOR2D( 0.0, -size.y / 2.0 ) );
}
else
{
// In case when there's no netname assigned
m_gal->SetGlyphSize( size );
m_gal->SetLineWidth( size.y / 10.0 );
}
m_gal->StrokeText( std::string( aPad->GetPadName().mb_str() ), VECTOR2D( 0, 0 ), 0.0 );
m_gal->Restore();
return;
}
if( m_pcbSettings->m_sketchModeSelect[PADS_VISIBLE] )
{
// Outline mode
@ -380,7 +442,7 @@ void PCB_PAINTER::draw( const D_PAD* aPad, int aLayer )
m_gal->Rotate( -aPad->GetOrientation() * M_PI / 1800.0 ); // orientation is in tenths of degree
// Choose drawing settings depending on if we are drawing a pad itself or a hole
if( aLayer == ITEM_GAL_LAYER( PAD_HOLES_VISIBLE ) )
if( aLayer == ITEM_GAL_LAYER( PADS_HOLES_VISIBLE ) )
{
// Drawing hole
size = VECTOR2D( aPad->GetDrillSize() ) / 2.0;

2
pcbnew/pcb_painter.h
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@ -105,6 +105,8 @@ protected:
bool m_visibleLayers [NB_LAYERS];
bool m_visibleItems [END_PCB_VISIBLE_LIST];
static const double MAX_FONT_SIZE = 1500000;
DisplayZonesMode m_displayZoneMode;
};