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Update QA boards' fills

This commit is contained in:
Seth Hillbrand 2023-07-20 12:08:17 -07:00
parent 810f3efcbb
commit 391204ea0d
21 changed files with 117252 additions and 18589 deletions
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19518
qa/data/pcbnew/complex_hierarchy.kicad_pcb
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File diff suppressed because it is too large Load Diff

244
qa/data/pcbnew/complex_hierarchy.kicad_pro
View File

@ -1,5 +1,6 @@
{
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {
"board_outline_line_width": 0.2032,
@ -44,7 +45,6 @@
"silk_text_thickness": 0.30479999999999996,
"silk_text_upright": false,
"zones": {
"45_degree_only": false,
"min_clearance": 0.508
}
},
@ -57,6 +57,7 @@
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"connection_width": "warning",
"copper_edge_clearance": "error",
"copper_sliver": "warning",
"courtyards_overlap": "error",
@ -65,24 +66,27 @@
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint_type_mismatch": "error",
"footprint": "error",
"footprint_type_mismatch": "ignore",
"hole_clearance": "error",
"hole_near_hole": "error",
"invalid_outline": "error",
"isolated_copper": "warning",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"lib_footprint_issues": "error",
"lib_footprint_mismatch": "error",
"lib_footprint_issues": "warning",
"lib_footprint_mismatch": "warning",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
"missing_footprint": "warning",
"net_conflict": "warning",
"npth_inside_courtyard": "ignore",
"padstack": "error",
"padstack": "warning",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_edge_clearance": "warning",
"silk_over_copper": "warning",
"silk_overlap": "warning",
"skew_out_of_range": "error",
@ -98,14 +102,12 @@
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zone_has_empty_net": "error",
"zones_intersect": "error"
},
"rules": {
"allow_blind_buried_vias": false,
"allow_microvias": false,
"max_error": 0.005,
"min_clearance": 0.0,
"min_connection": 0.0,
"min_copper_edge_clearance": 0.1016,
"min_hole_clearance": 0.25,
"min_hole_to_hole": 0.25,
@ -114,10 +116,10 @@
"min_resolved_spokes": 2,
"min_silk_clearance": 0.0,
"min_text_height": 0.7999999999999999,
"min_text_thickness": 0.12,
"min_text_thickness": 0.08,
"min_through_hole_diameter": 0.508,
"min_track_width": 0.2032,
"min_via_annular_width": 0.049999999999999996,
"min_via_annular_width": 0.09999999999999999,
"min_via_diameter": 0.889,
"solder_mask_to_copper_clearance": 0.0,
"use_height_for_length_calcs": true
@ -185,7 +187,7 @@
"net_settings": {
"classes": [
{
"bus_width": 12.0,
"bus_width": 12,
"clearance": 0.2794,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
@ -199,10 +201,10 @@
"track_width": 0.4318,
"via_diameter": 1.651,
"via_drill": 0.635,
"wire_width": 6.0
"wire_width": 6
},
{
"bus_width": 12.0,
"bus_width": 12,
"clearance": 0.381,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
@ -211,25 +213,221 @@
"microvia_diameter": 0.508,
"microvia_drill": 0.2032,
"name": "power",
"nets": [
"-VAA",
"/12Vext",
"GND",
"HT",
"VCC"
],
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.6096,
"via_diameter": 1.651,
"via_drill": 0.635,
"wire_width": 6.0
"wire_width": 6
}
],
"meta": {
"version": 2
"version": 3
},
"net_colors": null
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": [
{
"netclass": "Default",
"pattern": "+12V"
},
{
"netclass": "Default",
"pattern": "/ampli_h1"
},
{
"netclass": "Default",
"pattern": "/ampli_h2"
},
{
"netclass": "Default",
"pattern": "/ampli_h3"
},
{
"netclass": "Default",
"pattern": "/ampli_h4"
},
{
"netclass": "Default",
"pattern": "/ampli_h5"
},
{
"netclass": "Default",
"pattern": "/ampli_h6"
},
{
"netclass": "Default",
"pattern": "/ampli_h7"
},
{
"netclass": "Default",
"pattern": "/ampli_h8"
},
{
"netclass": "Default",
"pattern": "N-000005"
},
{
"netclass": "Default",
"pattern": "N-000010"
},
{
"netclass": "Default",
"pattern": "N-000011"
},
{
"netclass": "Default",
"pattern": "N-000012"
},
{
"netclass": "Default",
"pattern": "N-000013"
},
{
"netclass": "Default",
"pattern": "N-000014"
},
{
"netclass": "Default",
"pattern": "N-000015"
},
{
"netclass": "Default",
"pattern": "N-000016"
},
{
"netclass": "Default",
"pattern": "N-000017"
},
{
"netclass": "Default",
"pattern": "N-000018"
},
{
"netclass": "Default",
"pattern": "N-000019"
},
{
"netclass": "Default",
"pattern": "N-000020"
},
{
"netclass": "Default",
"pattern": "N-000021"
},
{
"netclass": "Default",
"pattern": "N-000022"
},
{
"netclass": "Default",
"pattern": "N-000023"
},
{
"netclass": "Default",
"pattern": "N-000024"
},
{
"netclass": "Default",
"pattern": "N-000025"
},
{
"netclass": "Default",
"pattern": "N-000026"
},
{
"netclass": "Default",
"pattern": "N-000027"
},
{
"netclass": "Default",
"pattern": "N-000032"
},
{
"netclass": "Default",
"pattern": "N-000033"
},
{
"netclass": "Default",
"pattern": "N-000034"
},
{
"netclass": "Default",
"pattern": "N-000035"
},
{
"netclass": "Default",
"pattern": "N-000036"
},
{
"netclass": "Default",
"pattern": "N-000037"
},
{
"netclass": "Default",
"pattern": "N-000038"
},
{
"netclass": "Default",
"pattern": "N-000039"
},
{
"netclass": "Default",
"pattern": "N-000040"
},
{
"netclass": "Default",
"pattern": "N-000041"
},
{
"netclass": "Default",
"pattern": "N-000042"
},
{
"netclass": "Default",
"pattern": "N-000043"
},
{
"netclass": "Default",
"pattern": "N-000044"
},
{
"netclass": "Default",
"pattern": "N-000045"
},
{
"netclass": "Default",
"pattern": "N-000046"
},
{
"netclass": "Default",
"pattern": "N-000047"
},
{
"netclass": "Default",
"pattern": "N-000048"
},
{
"netclass": "power",
"pattern": "-VAA"
},
{
"netclass": "power",
"pattern": "/12Vext"
},
{
"netclass": "power",
"pattern": "GND"
},
{
"netclass": "power",
"pattern": "HT"
},
{
"netclass": "power",
"pattern": "VCC"
}
]
},
"pcbnew": {
"last_paths": {

26
qa/data/pcbnew/connection_width_rules.kicad_pro
View File

@ -71,6 +71,7 @@
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint": "error",
"footprint_type_mismatch": "warning",
"hole_clearance": "error",
"hole_near_hole": "error",
@ -87,7 +88,6 @@
"missing_footprint": "warning",
"net_conflict": "warning",
"npth_inside_courtyard": "ignore",
"overlapping_pads": "warning",
"padstack": "warning",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
@ -194,13 +194,13 @@
"pinned_symbol_libs": []
},
"meta": {
"filename": "connection_width.kicad_pro",
"filename": "connection_width_rules.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12.0,
"bus_width": 12,
"clearance": 0.1,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
@ -214,10 +214,10 @@
"track_width": 0.1,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6.0
"wire_width": 6
},
{
"bus_width": 12.0,
"bus_width": 12,
"clearance": 0.1,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
@ -226,21 +226,25 @@
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "High_current",
"nets": [
"net_HC"
],
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.25,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6.0
"wire_width": 6
}
],
"meta": {
"version": 2
"version": 3
},
"net_colors": null
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": [
{
"netclass": "High_current",
"pattern": "net_HC"
}
]
},
"pcbnew": {
"last_paths": {

80
qa/data/pcbnew/custom_fields.kicad_pro
View File

@ -1,5 +1,6 @@
{
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {
"board_outline_line_width": 0.09999999999999999,
@ -51,24 +52,31 @@
"diff_pair_dimensions": [],
"drc_exclusions": [],
"meta": {
"version": 1
"version": 2
},
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"connection_width": "warning",
"copper_edge_clearance": "error",
"copper_sliver": "warning",
"courtyards_overlap": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint": "error",
"footprint_type_mismatch": "ignore",
"hole_clearance": "error",
"hole_near_hole": "error",
"invalid_outline": "error",
"isolated_copper": "warning",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"lib_footprint_issues": "warning",
"lib_footprint_mismatch": "warning",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
@ -78,9 +86,15 @@
"padstack": "error",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_edge_clearance": "warning",
"silk_over_copper": "error",
"silk_overlap": "error",
"skew_out_of_range": "error",
"solder_mask_bridge": "error",
"starved_thermal": "error",
"text_height": "warning",
"text_thickness": "warning",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
"track_dangling": "warning",
"track_width": "error",
@ -88,7 +102,6 @@
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zone_has_empty_net": "error",
"zones_intersect": "error"
},
"rules": {
@ -96,27 +109,70 @@
"allow_microvias": false,
"max_error": 0.005,
"min_clearance": 0.0,
"min_connection": 0.0,
"min_copper_edge_clearance": 0.0,
"min_hole_clearance": 0.0,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.19999999999999998,
"min_microvia_drill": 0.09999999999999999,
"min_resolved_spokes": 2,
"min_silk_clearance": 0.0,
"min_text_height": 0.7999999999999999,
"min_text_thickness": 0.08,
"min_through_hole_diameter": 0.3,
"min_track_width": 0.19999999999999998,
"min_via_annular_width": 0.049999999999999996,
"min_via_diameter": 0.39999999999999997,
"solder_mask_clearance": 0.0,
"solder_mask_min_width": 0.0,
"solder_paste_clearance": 0.0,
"solder_paste_margin_ratio": 0.0
"solder_mask_to_copper_clearance": 0.0,
"use_height_for_length_calcs": true
},
"teardrop_options": [
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 5,
"td_on_pad_in_zone": false,
"td_onpadsmd": true,
"td_onroundshapesonly": false,
"td_ontrackend": false,
"td_onviapad": true
}
],
"teardrop_parameters": [
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_round_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_rect_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_track_end",
"td_width_to_size_filter_ratio": 0.9
}
],
"track_widths": [],
"via_dimensions": [],
"zones_allow_external_fillets": false,
"zones_use_no_outline": true
},
"layer_presets": []
"layer_presets": [],
"viewports": []
},
"boards": [],
"cvpcb": {
@ -337,7 +393,7 @@
"net_settings": {
"classes": [
{
"bus_width": 6.0,
"bus_width": 6,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
@ -351,13 +407,15 @@
"track_width": 0.25,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6.0
"wire_width": 6
}
],
"meta": {
"version": 0
"version": 3
},
"net_colors": null
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": []
},
"pcbnew": {
"last_paths": {

63
qa/data/pcbnew/custom_pads.kicad_pro
View File

@ -1,5 +1,6 @@
{
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {
"board_outline_line_width": 0.049999999999999996,
@ -56,6 +57,7 @@
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"connection_width": "warning",
"copper_edge_clearance": "error",
"copper_sliver": "warning",
"courtyards_overlap": "error",
@ -64,13 +66,17 @@
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint": "error",
"footprint_type_mismatch": "ignore",
"hole_clearance": "error",
"hole_near_hole": "error",
"invalid_outline": "error",
"isolated_copper": "warning",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"lib_footprint_issues": "error",
"lib_footprint_mismatch": "warning",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
@ -80,6 +86,7 @@
"padstack": "error",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_edge_clearance": "warning",
"silk_over_copper": "warning",
"silk_overlap": "warning",
"skew_out_of_range": "error",
@ -87,6 +94,7 @@
"starved_thermal": "error",
"text_height": "warning",
"text_thickness": "warning",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
"track_dangling": "warning",
"track_width": "error",
@ -94,7 +102,6 @@
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zone_has_empty_net": "error",
"zones_intersect": "error"
},
"rules": {
@ -102,6 +109,7 @@
"allow_microvias": false,
"max_error": 0.005,
"min_clearance": 0.0,
"min_connection": 0.0,
"min_copper_edge_clearance": 0.01,
"min_hole_clearance": 0.0,
"min_hole_to_hole": 0.25,
@ -118,12 +126,53 @@
"solder_mask_to_copper_clearance": 0.0,
"use_height_for_length_calcs": true
},
"teardrop_options": [
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 5,
"td_on_pad_in_zone": false,
"td_onpadsmd": true,
"td_onroundshapesonly": false,
"td_ontrackend": false,
"td_onviapad": true
}
],
"teardrop_parameters": [
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_round_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_rect_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_track_end",
"td_width_to_size_filter_ratio": 0.9
}
],
"track_widths": [],
"via_dimensions": [],
"zones_allow_external_fillets": false,
"zones_use_no_outline": true
},
"layer_presets": []
"layer_presets": [],
"viewports": []
},
"boards": [],
"cvpcb": {
@ -140,7 +189,7 @@
"net_settings": {
"classes": [
{
"bus_width": 12.0,
"bus_width": 12,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
@ -154,13 +203,15 @@
"track_width": 0.25,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6.0
"wire_width": 6
}
],
"meta": {
"version": 1
"version": 3
},
"net_colors": null
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": []
},
"pcbnew": {
"last_paths": {

92
qa/data/pcbnew/issue11814.kicad_pro
View File

@ -70,6 +70,7 @@
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"connection_width": "warning",
"copper_edge_clearance": "ignore",
"copper_sliver": "warning",
"courtyards_overlap": "error",
@ -78,6 +79,7 @@
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint": "error",
"footprint_type_mismatch": "ignore",
"hole_clearance": "error",
"hole_near_hole": "error",
@ -94,7 +96,6 @@
"missing_footprint": "warning",
"net_conflict": "warning",
"npth_inside_courtyard": "ignore",
"overlapping_pads": "warning",
"padstack": "error",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
@ -121,6 +122,7 @@
"allow_microvias": false,
"max_error": 0.005,
"min_clearance": 0.0,
"min_connection": 0.0,
"min_copper_edge_clearance": 0.25,
"min_hole_clearance": 0.254,
"min_hole_to_hole": 0.25,
@ -421,7 +423,7 @@
"net_settings": {
"classes": [
{
"bus_width": 12.0,
"bus_width": 12,
"clearance": 0.15,
"diff_pair_gap": 0.1524,
"diff_pair_via_gap": 0.25,
@ -435,10 +437,10 @@
"track_width": 0.1524,
"via_diameter": 0.45,
"via_drill": 0.2,
"wire_width": 6.0
"wire_width": 6
},
{
"bus_width": 12.0,
"bus_width": 12,
"clearance": 1.0,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
@ -447,28 +449,15 @@
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "HV",
"nets": [
"/ATN_IN",
"/SIG_100XC2",
"/SIG_1X",
"/SIG_1XC",
"/SIG_1XC2",
"/SIG_50_{OPEN}",
"/SIG_IN_{1}",
"/SIG_IN_{2}",
"/SIG_IN_{3}",
"/SIG_{1}",
"/SIG_{2}"
],
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.1524,
"via_diameter": 0.45,
"via_drill": 0.2,
"wire_width": 6.0
"wire_width": 6
},
{
"bus_width": 12.0,
"bus_width": 12,
"clearance": 0.4,
"diff_pair_gap": 0.1524,
"diff_pair_via_gap": 0.25,
@ -477,22 +466,73 @@
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "VaricapBias",
"nets": [
"/VFILT'",
"/VFILTER"
],
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.1524,
"via_diameter": 0.45,
"via_drill": 0.2,
"wire_width": 6.0
"wire_width": 6
}
],
"meta": {
"version": 2
"version": 3
},
"net_colors": null
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": [
{
"netclass": "HV",
"pattern": "/ATN_IN"
},
{
"netclass": "HV",
"pattern": "/SIG_100XC2"
},
{
"netclass": "HV",
"pattern": "/SIG_1X"
},
{
"netclass": "HV",
"pattern": "/SIG_1XC"
},
{
"netclass": "HV",
"pattern": "/SIG_1XC2"
},
{
"netclass": "HV",
"pattern": "/SIG_50_{OPEN}"
},
{
"netclass": "HV",
"pattern": "/SIG_IN_{1}"
},
{
"netclass": "HV",
"pattern": "/SIG_IN_{2}"
},
{
"netclass": "HV",
"pattern": "/SIG_IN_{3}"
},
{
"netclass": "HV",
"pattern": "/SIG_{1}"
},
{
"netclass": "HV",
"pattern": "/SIG_{2}"
},
{
"netclass": "VaricapBias",
"pattern": "/VFILT'"
},
{
"netclass": "VaricapBias",
"pattern": "/VFILTER"
}
]
},
"pcbnew": {
"last_paths": {

73
qa/data/pcbnew/issue12109.kicad_pro
View File

@ -1,5 +1,6 @@
{
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {
"board_outline_line_width": 0.09999999999999999,
@ -62,20 +63,26 @@
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"connection_width": "warning",
"copper_edge_clearance": "error",
"copper_sliver": "warning",
"courtyards_overlap": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint": "error",
"footprint_type_mismatch": "error",
"hole_clearance": "error",
"hole_near_hole": "error",
"invalid_outline": "error",
"isolated_copper": "warning",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"lib_footprint_issues": "warning",
"lib_footprint_mismatch": "warning",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
@ -85,9 +92,14 @@
"padstack": "error",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_edge_clearance": "warning",
"silk_over_copper": "warning",
"silk_overlap": "warning",
"skew_out_of_range": "error",
"solder_mask_bridge": "error",
"starved_thermal": "error",
"text_height": "warning",
"text_thickness": "warning",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
"track_dangling": "warning",
@ -96,7 +108,6 @@
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zone_has_empty_net": "error",
"zones_intersect": "error"
},
"rules": {
@ -104,20 +115,65 @@
"allow_microvias": false,
"max_error": 0.005,
"min_clearance": 0.19999999999999998,
"min_connection": 0.0,
"min_copper_edge_clearance": 0.5,
"min_hole_clearance": 0.25,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.19999999999999998,
"min_microvia_drill": 0.09999999999999999,
"min_resolved_spokes": 2,
"min_silk_clearance": 0.0,
"min_text_height": 0.7999999999999999,
"min_text_thickness": 0.08,
"min_through_hole_diameter": 0.3,
"min_track_width": 0.19999999999999998,
"min_via_annular_width": 0.19999999999999998,
"min_via_diameter": 0.39999999999999997,
"solder_mask_clearance": 0.0,
"solder_mask_min_width": 0.0,
"solder_mask_to_copper_clearance": 0.0,
"use_height_for_length_calcs": true
},
"teardrop_options": [
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 5,
"td_on_pad_in_zone": false,
"td_onpadsmd": true,
"td_onroundshapesonly": false,
"td_ontrackend": false,
"td_onviapad": true
}
],
"teardrop_parameters": [
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_round_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_rect_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_track_end",
"td_width_to_size_filter_ratio": 0.9
}
],
"track_widths": [
0.0
],
@ -130,7 +186,8 @@
"zones_allow_external_fillets": true,
"zones_use_no_outline": true
},
"layer_presets": []
"layer_presets": [],
"viewports": []
},
"boards": [],
"cvpcb": {
@ -346,13 +403,13 @@
"pinned_symbol_libs": []
},
"meta": {
"filename": "annular_ring_bug.kicad_pro",
"filename": "issue12109.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12.0,
"bus_width": 12,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
@ -366,13 +423,15 @@
"track_width": 0.25,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6.0
"wire_width": 6
}
],
"meta": {
"version": 2
"version": 3
},
"net_colors": null
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": []
},
"pcbnew": {
"last_paths": {

6
qa/data/pcbnew/issue12609.kicad_pro
View File

@ -55,9 +55,7 @@
"width": 0.0
}
],
"drc_exclusions": [
"courtyards_overlap|156916541|75399999|c252dcdc-a75f-458d-80db-287ecab15830|ff13b34e-f2dd-464a-8eab-fcfac643f59c"
],
"drc_exclusions": [],
"meta": {
"version": 2
},
@ -404,7 +402,7 @@
"pinned_symbol_libs": []
},
"meta": {
"filename": "minikv_primary.kicad_pro",
"filename": "issue12609.kicad_pro",
"version": 1
},
"net_settings": {

14
qa/data/pcbnew/issue1358.kicad_pro
View File

@ -1,5 +1,6 @@
{
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {
"board_outline_line_width": 0.049999999999999996,
@ -63,6 +64,7 @@
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"connection_width": "warning",
"copper_edge_clearance": "error",
"copper_sliver": "warning",
"courtyards_overlap": "error",
@ -71,6 +73,7 @@
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint": "error",
"footprint_type_mismatch": "error",
"hole_clearance": "error",
"hole_near_hole": "error",
@ -114,6 +117,7 @@
"max_error": 0.005,
"min_aperture_clearance": 0.049999999999999996,
"min_clearance": 0.0,
"min_connection": 0.0,
"min_copper_edge_clearance": 0.25,
"min_hole_clearance": 0.0,
"min_hole_to_hole": 0.25,
@ -382,7 +386,7 @@
"net_settings": {
"classes": [
{
"bus_width": 12.0,
"bus_width": 12,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
@ -396,13 +400,15 @@
"track_width": 0.25,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6.0
"wire_width": 6
}
],
"meta": {
"version": 2
"version": 3
},
"net_colors": null
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": []
},
"pcbnew": {
"last_paths": {

627
qa/data/pcbnew/issue18.kicad_pcb
View File

@ -1,87 +1,51 @@
(kicad_pcb (version 20171130) (host pcbnew "(5.1.0-rc2-38-g4612175da2)")
(kicad_pcb (version 20221018) (generator pcbnew)
(general
(thickness 1.6)
(drawings 0)
(tracks 7)
(zones 0)
(modules 1)
(nets 15)
)
(page A4)
(paper "A4")
(layers
(0 F.Cu signal)
(1 In1.Cu signal)
(2 In2.Cu signal)
(3 In3.Cu signal)
(4 In4.Cu signal)
(31 B.Cu signal)
(32 B.Adhes user)
(33 F.Adhes user)
(34 B.Paste user)
(35 F.Paste user)
(36 B.SilkS user)
(37 F.SilkS user)
(38 B.Mask user)
(39 F.Mask user)
(40 Dwgs.User user)
(41 Cmts.User user)
(42 Eco1.User user)
(43 Eco2.User user)
(44 Edge.Cuts user)
(45 Margin user)
(46 B.CrtYd user)
(47 F.CrtYd user)
(48 B.Fab user)
(49 F.Fab user)
(0 "F.Cu" signal)
(1 "In1.Cu" signal)
(2 "In2.Cu" signal)
(3 "In3.Cu" signal)
(4 "In4.Cu" signal)
(31 "B.Cu" signal)
(32 "B.Adhes" user "B.Adhesive")
(33 "F.Adhes" user "F.Adhesive")
(34 "B.Paste" user)
(35 "F.Paste" user)
(36 "B.SilkS" user "B.Silkscreen")
(37 "F.SilkS" user "F.Silkscreen")
(38 "B.Mask" user)
(39 "F.Mask" user)
(40 "Dwgs.User" user "User.Drawings")
(41 "Cmts.User" user "User.Comments")
(42 "Eco1.User" user "User.Eco1")
(43 "Eco2.User" user "User.Eco2")
(44 "Edge.Cuts" user)
(45 "Margin" user)
(46 "B.CrtYd" user "B.Courtyard")
(47 "F.CrtYd" user "F.Courtyard")
(48 "B.Fab" user)
(49 "F.Fab" user)
)
(setup
(last_trace_width 0.127)
(user_trace_width 0.1)
(user_trace_width 0.25)
(user_trace_width 0.5)
(user_trace_width 0.75)
(user_trace_width 1)
(user_trace_width 1.2)
(user_trace_width 1.65)
(user_trace_width 2.5)
(trace_clearance 0.12)
(zone_clearance 0.22)
(zone_45_only no)
(trace_min 0.09)
(via_size 0.45)
(via_drill 0.2)
(via_min_size 0.45)
(via_min_drill 0.2)
(user_via 0.45 0.2)
(uvia_size 0.2)
(uvia_drill 0.1)
(uvias_allowed no)
(uvia_min_size 0.2)
(uvia_min_drill 0.1)
(edge_width 0.15)
(segment_width 0.2)
(pcb_text_width 0.3)
(pcb_text_size 1.5 1.5)
(mod_edge_width 0.15)
(mod_text_size 0.5 0.5)
(mod_text_width 0.125)
(pad_size 0.3 0.5)
(pad_drill 0)
(pad_to_mask_clearance 0.0508)
(solder_mask_min_width 0.25)
(aux_axis_origin 0 0)
(visible_elements FFFDFF7F)
(pcbplotparams
(layerselection 0x010fc_ffffffff)
(layerselection 0x00010fc_ffffffff)
(plot_on_all_layers_selection 0x0000000_00000000)
(disableapertmacros false)
(usegerberextensions false)
(usegerberattributes false)
(usegerberadvancedattributes false)
(creategerberjobfile false)
(excludeedgelayer true)
(linewidth 0.100000)
(dashed_line_dash_ratio 12.000000)
(dashed_line_gap_ratio 3.000000)
(svgprecision 4)
(plotframeref false)
(viasonmask false)
(mode 1)
@ -89,204 +53,395 @@
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15.000000)
(dxfpolygonmode true)
(dxfimperialunits true)
(dxfusepcbnewfont true)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
(plotinvisibletext false)
(padsonsilk false)
(sketchpadsonfab false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 0)
(scaleselection 1)
(outputdirectory "."))
(outputdirectory ".")
)
)
(net 0 "")
(net 1 GND)
(net 2 /rasp_cm/HDMI_CK_N)
(net 3 /rasp_cm/HDMI_CK_P)
(net 4 /hdmi_conn/HDMI_D0_N)
(net 5 /hdmi_conn/HDMI_D0_P)
(net 6 /hdmi_conn/HDMI_D1_N)
(net 7 /hdmi_conn/HDMI_D1_P)
(net 8 /hdmi_conn/HDMI_D2_N)
(net 9 /hdmi_conn/HDMI_D2_P)
(net 10 /hdmi_conn/HDMI_CEC)
(net 11 /hdmi_conn/HDMI_SDA)
(net 12 /hdmi_conn/HDMI_SCL)
(net 13 /hdmi_conn/HDMI_HPD)
(net 14 +5V)
(net 1 "GND")
(net 2 "/rasp_cm/HDMI_CK_N")
(net 3 "/rasp_cm/HDMI_CK_P")
(net 4 "/hdmi_conn/HDMI_D0_N")
(net 5 "/hdmi_conn/HDMI_D0_P")
(net 6 "/hdmi_conn/HDMI_D1_N")
(net 7 "/hdmi_conn/HDMI_D1_P")
(net 8 "/hdmi_conn/HDMI_D2_N")
(net 9 "/hdmi_conn/HDMI_D2_P")
(net 10 "/hdmi_conn/HDMI_CEC")
(net 11 "/hdmi_conn/HDMI_SDA")
(net 12 "/hdmi_conn/HDMI_SCL")
(net 13 "/hdmi_conn/HDMI_HPD")
(net 14 "+5V")
(net_class Default "This is the default net class."
(clearance 0.12)
(trace_width 0.127)
(via_dia 0.45)
(via_drill 0.2)
(uvia_dia 0.2)
(uvia_drill 0.1)
(diff_pair_width 0.2)
(diff_pair_gap 0.127)
(add_net +5V)
(add_net /hdmi_conn/HDMI_CEC)
(add_net /hdmi_conn/HDMI_D0_N)
(add_net /hdmi_conn/HDMI_D0_P)
(add_net /hdmi_conn/HDMI_D1_N)
(add_net /hdmi_conn/HDMI_D1_P)
(add_net /hdmi_conn/HDMI_D2_N)
(add_net /hdmi_conn/HDMI_D2_P)
(add_net /hdmi_conn/HDMI_HPD)
(add_net /hdmi_conn/HDMI_SCL)
(add_net /hdmi_conn/HDMI_SDA)
(add_net /rasp_cm/HDMI_CK_N)
(add_net /rasp_cm/HDMI_CK_P)
(add_net GND)
)
(module FS-Diode:TestFootprint (layer F.Cu) (tedit 5C7F02F0) (tstamp 5C7EF524)
(footprint "FS-Diode:TestFootprint" (layer "F.Cu")
(tstamp 00000000-0000-0000-0000-00005c7ef524)
(at 22.8 18.07 180)
(path /5B657F9C/5B658966)
(path "/00000000-0000-0000-0000-00005b657f9c/00000000-0000-0000-0000-00005b658966")
(attr smd)
(fp_text reference U13 (at 0 1.8 180) (layer F.SilkS)
(fp_text reference "U13" (at 0 1.8 180) (layer "F.SilkS")
(effects (font (size 0.5 0.5) (thickness 0.125)))
(tstamp 70010b2d-ab17-4430-9604-b823efcd92a2)
)
(fp_text value TestFootprint (at 0 -1.7 180) (layer F.Fab)
(fp_text value "TestFootprint" (at 0 -1.7 180) (layer "F.Fab")
(effects (font (size 0.5 0.5) (thickness 0.125)))
(tstamp c9e03b0f-ca50-4773-a617-1d00f6187cdf)
)
(fp_line (start -2.9 -0.9) (end -2.9 0.85) (layer F.SilkS) (width 0.15))
(fp_line (start -2.5 -0.9) (end -2.9 -0.9) (layer F.SilkS) (width 0.15))
(fp_line (start 2.9 -0.9) (end 2.5 -0.9) (layer F.SilkS) (width 0.15))
(fp_line (start 2.9 0.9) (end 2.9 -0.9) (layer F.SilkS) (width 0.15))
(fp_line (start 2.75 0.9) (end 2.9 0.9) (layer F.SilkS) (width 0.15))
(fp_line (start 2.75 0.75) (end 2.75 -0.75) (layer F.CrtYd) (width 0.15))
(fp_line (start 2.75 0.75) (end -2.75 0.75) (layer F.CrtYd) (width 0.15))
(fp_line (start -2.75 -0.75) (end -2.75 0.75) (layer F.CrtYd) (width 0.15))
(fp_line (start -2.75 -0.75) (end 2.75 -0.75) (layer F.CrtYd) (width 0.15))
(pad 15 smd rect (at 0 -0.65 180) (size 0.3 0.5) (layers F.Cu F.Paste F.Mask)
(net 11 /hdmi_conn/HDMI_SDA))
(pad 14 smd rect (at 0.75 -0.65 180) (size 0.3 0.5) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad 13 smd rect (at 1.5 -0.65 180) (size 0.3 0.5) (layers F.Cu F.Paste F.Mask)
(net 14 +5V))
(pad 12 smd rect (at 2.25 -0.65 180) (size 0.3 0.5) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad 16 smd rect (at -0.75 -0.65 180) (size 0.3 0.5) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad 17 smd rect (at -1.5 -0.65 180) (size 0.3 0.5) (layers F.Cu F.Paste F.Mask)
(net 10 /hdmi_conn/HDMI_CEC))
(pad 18 smd rect (at -2.25 -0.65 180) (size 0.3 0.5) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad 6 smd rect (at 0 0.65 180) (size 0.3 0.5) (layers F.Cu F.Paste F.Mask)
(net 12 /hdmi_conn/HDMI_SCL))
(pad 7 smd rect (at 0.5 0.65 180) (size 0.3 0.5) (layers F.Cu F.Paste F.Mask)
(net 5 /hdmi_conn/HDMI_D0_P))
(pad 8 smd rect (at 1 0.65 180) (size 0.3 0.5) (layers F.Cu F.Paste F.Mask)
(net 4 /hdmi_conn/HDMI_D0_N))
(pad 9 smd rect (at 1.5 0.65 180) (size 0.3 0.5) (layers F.Cu F.Paste F.Mask)
(net 13 /hdmi_conn/HDMI_HPD))
(pad 10 smd rect (at 2 0.65 180) (size 0.3 0.5) (layers F.Cu F.Paste F.Mask)
(net 3 /rasp_cm/HDMI_CK_P))
(pad 11 smd rect (at 2.5 0.65 180) (size 0.3 0.5) (layers F.Cu F.Paste F.Mask)
(net 2 /rasp_cm/HDMI_CK_N))
(pad 5 smd rect (at -0.5 0.65 180) (size 0.3 0.5) (layers F.Cu F.Paste F.Mask)
(net 6 /hdmi_conn/HDMI_D1_N))
(pad 4 smd rect (at -1 0.65 180) (size 0.3 0.5) (layers F.Cu F.Paste F.Mask)
(net 7 /hdmi_conn/HDMI_D1_P))
(pad 3 smd rect (at -1.5 0.65 180) (size 0.3 0.5) (layers F.Cu F.Paste F.Mask))
(pad 2 smd rect (at -2 0.65 180) (size 0.3 0.5) (layers F.Cu F.Paste F.Mask)
(net 8 /hdmi_conn/HDMI_D2_N))
(pad 1 smd rect (at -2.575 0.65 180) (size 0.45 0.5) (layers F.Cu F.Paste F.Mask)
(net 9 /hdmi_conn/HDMI_D2_P))
(fp_line (start -2.9 -0.9) (end -2.9 0.85)
(stroke (width 0.15) (type solid)) (layer "F.SilkS") (tstamp 019b6ef4-2f3e-4c9f-ad46-ea420dac0c54))
(fp_line (start -2.5 -0.9) (end -2.9 -0.9)
(stroke (width 0.15) (type solid)) (layer "F.SilkS") (tstamp ae5fa37d-bdac-487c-9310-d9a3486f5821))
(fp_line (start 2.75 0.9) (end 2.9 0.9)
(stroke (width 0.15) (type solid)) (layer "F.SilkS") (tstamp 568a65b5-68ec-4a57-8af3-435842f64b61))
(fp_line (start 2.9 -0.9) (end 2.5 -0.9)
(stroke (width 0.15) (type solid)) (layer "F.SilkS") (tstamp 5dd1ed02-e70b-4f60-86a3-d1fc0f5cc1d4))
(fp_line (start 2.9 0.9) (end 2.9 -0.9)
(stroke (width 0.15) (type solid)) (layer "F.SilkS") (tstamp dc1a1d8c-c7b5-46b8-ba69-f8fedb3ce7e0))
(fp_line (start -2.75 -0.75) (end -2.75 0.75)
(stroke (width 0.15) (type solid)) (layer "F.CrtYd") (tstamp 302a3b1e-6d13-4489-bdad-cf8959cf3eec))
(fp_line (start -2.75 -0.75) (end 2.75 -0.75)
(stroke (width 0.15) (type solid)) (layer "F.CrtYd") (tstamp f5cae03d-0647-425c-96dd-847c8e557c57))
(fp_line (start 2.75 0.75) (end -2.75 0.75)
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61
qa/data/pcbnew/issue2512.kicad_pro
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@ -1,5 +1,6 @@
{
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@ -71,13 +73,17 @@
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@ -101,7 +109,6 @@
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72
qa/data/pcbnew/issue2528.kicad_pro
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243
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14717
qa/data/pcbnew/issue2904.kicad_pcb
View File

File diff suppressed because it is too large Load Diff

396
qa/data/pcbnew/issue2904.kicad_pro Normal file
View File

@ -0,0 +1,396 @@
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73
qa/data/pcbnew/issue3812.kicad_pro
View File

@ -1,5 +1,6 @@
{
"board": {
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@ -62,6 +63,7 @@
"rule_severities": {
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"clearance": "error",
"connection_width": "warning",
"copper_edge_clearance": "error",
"copper_sliver": "warning",
"courtyards_overlap": "error",
@ -70,13 +72,17 @@
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint": "error",
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"hole_clearance": "error",
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"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
@ -86,6 +92,7 @@
"padstack": "error",
"pth_inside_courtyard": "ignore",
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"silk_edge_clearance": "warning",
"silk_over_copper": "error",
"silk_overlap": "error",
"skew_out_of_range": "error",
@ -93,6 +100,7 @@
"starved_thermal": "error",
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@ -100,7 +108,6 @@
"unconnected_items": "error",
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},
"rule_severitieslegacy_courtyards_overlap": true,
@ -110,6 +117,7 @@
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@ -123,8 +131,49 @@
"min_track_width": 0.19812,
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@ -139,7 +188,8 @@
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@ -360,7 +410,7 @@
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@ -374,10 +424,10 @@
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@ -386,23 +436,20 @@
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75
qa/data/pcbnew/issue4774.kicad_pro
View File

@ -1,5 +1,6 @@
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@ -61,22 +62,27 @@
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@ -86,12 +92,15 @@
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@ -99,7 +108,6 @@
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},
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@ -110,6 +118,7 @@
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@ -123,8 +132,49 @@
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@ -139,7 +189,8 @@
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@ -365,7 +416,7 @@
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@ -379,10 +430,10 @@
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@ -391,22 +442,20 @@
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File diff suppressed because it is too large Load Diff

229
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@ -0,0 +1,229 @@
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