Translated using Weblate (Chinese (Simplified))
Currently translated at 100.0% (9170 of 9170 strings) Translation: KiCad EDA/v8 Translate-URL: https://hosted.weblate.org/projects/kicad/v8/zh_Hans/
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@ -36,8 +36,8 @@ msgstr ""
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"Project-Id-Version: KiCad_zh_CN_Master_v0.0.32\n"
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"Report-Msgid-Bugs-To: \n"
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"POT-Creation-Date: 2024-04-14 14:22-0700\n"
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"PO-Revision-Date: 2024-04-17 14:21+0000\n"
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"Last-Translator: taotieren <admin@taotieren.com>\n"
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"PO-Revision-Date: 2024-04-18 07:23+0000\n"
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"Last-Translator: CloverGit <w991593239@163.com>\n"
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"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
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"kicad/v8/zh_Hans/>\n"
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"Language: zh_CN\n"
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@ -78,9 +78,8 @@ msgstr ""
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#: 3d-viewer/3d_canvas/board_adapter.cpp:931
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msgid "Board outline is missing or malformed. Run DRC for a full analysis."
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msgstr ""
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"电路板缺少板框或板框形状异常 (如板框线条没有闭合)。可用设计规则检查 (DRC) 分"
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"析原因。"
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msgstr "电路板缺少外框或外框形状异常 (如板外框线条没有闭合)。可用设计规则检查 (DRC) "
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"分析原因。"
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#: 3d-viewer/3d_canvas/create_layer_items.cpp:260
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msgid "Create tracks and vias"
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@ -752,7 +751,7 @@ msgstr "板外丝印层"
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#: 3d-viewer/dialogs/appearance_controls_3D.cpp:79
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msgid "Do not clip silk layers to board outline"
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msgstr "避免板边裁剪丝印层"
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msgstr "避免电路板外框裁剪丝印层"
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#: 3d-viewer/dialogs/appearance_controls_3D.cpp:81
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msgid "3D Axis"
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@ -25668,7 +25667,7 @@ msgstr "<= 2%"
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#: pcb_calculator/calculator_panels/panel_color_code_base.cpp:22
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#: pcb_calculator/calculator_panels/panel_color_code_base.cpp:54
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msgid "Tolerance"
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msgstr "误差"
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msgstr "精度容差"
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#: pcb_calculator/calculator_panels/panel_color_code_base.cpp:34
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msgid "1st Band"
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@ -28163,7 +28162,7 @@ msgstr "(不是闭合形状)"
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#: pcbnew/convert_shape_list_to_polygon.cpp:516
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msgid "(multiple board outlines not supported)"
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msgstr "(不支持多电路板轮廓)"
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msgstr "(不支持多个电路板外框)"
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#: pcbnew/convert_shape_list_to_polygon.cpp:652
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#, c-format
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@ -28956,12 +28955,12 @@ msgstr "(不会考虑合并出现在 Net Tie 焊盘组中的焊盘。)"
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#: pcbnew/dialogs/dialog_cleanup_graphics_base.cpp:41
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msgid "Fix discontinuities in board outlines"
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msgstr "修复未闭合的电路板板外框"
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msgstr "修复未闭合的电路板外框"
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#: pcbnew/dialogs/dialog_cleanup_graphics_base.cpp:46
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#: pcbnew/import_gfx/dialog_import_graphics_base.cpp:178
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msgid "Tolerance:"
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msgstr "容差:"
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msgstr "精度容差:"
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#: pcbnew/dialogs/dialog_cleanup_graphics_base.cpp:67
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#: pcbnew/dialogs/dialog_cleanup_tracks_and_vias_base.cpp:72
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@ -30387,7 +30386,7 @@ msgid ""
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"Board outline is missing or not closed using %.3f mm tolerance.\n"
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"Run DRC for a full analysis."
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msgstr ""
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"电路板轮廓缺失或未用 %.3f mm 公差闭合。\n"
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"电路板外框缺失或外框形状的闭合误差超过允许的容差值: %.3f mm。\n"
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"运行设计规则检查 (DRC) 进行全面分析。"
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#: pcbnew/dialogs/dialog_export_step.cpp:412
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@ -30524,7 +30523,7 @@ msgstr "导出锡膏图形。"
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#: pcbnew/dialogs/dialog_export_step_base.cpp:188
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msgid "Board outline chaining tolerance:"
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msgstr "电路板边框公差:"
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msgstr "电路板外框容差:"
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#: pcbnew/dialogs/dialog_export_step_base.cpp:192
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msgid "Tight (0.001 mm)"
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@ -30542,7 +30541,7 @@ msgstr "松散 (0.1 mm)"
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msgid ""
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"Tolerance sets the distance between two points that are considered joined "
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"when building the board outlines."
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msgstr "当构建电路板边框时, 公差设定了两个被视为联结的点的距离。"
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msgstr "容差用于设定在构造电路板外框时, 两个被视为连结点的最小距离值。"
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#: pcbnew/dialogs/dialog_export_step_base.h:93
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msgid "Export STEP / GLTF"
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@ -30731,7 +30730,7 @@ msgstr "包含走线 (&T)"
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#: pcbnew/dialogs/dialog_filter_selection_base.cpp:45
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msgid "Include &board outline layer"
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msgstr "包含电路板边框层 (&B)"
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msgstr "包含电路板外框层 (&B)"
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#: pcbnew/dialogs/dialog_filter_selection_base.cpp:48
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msgid "Include &vias"
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@ -31642,7 +31641,7 @@ msgstr "覆铜"
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#: pcbnew/dialogs/dialog_global_deletion_base.cpp:31
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msgid "Board outlines"
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msgstr "电路板边框"
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msgstr "电路板外框"
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#: pcbnew/dialogs/dialog_global_deletion_base.cpp:34
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#: pcbnew/widgets/panel_selection_filter.cpp:191
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@ -38054,7 +38053,7 @@ msgstr "(层 %s)"
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#: pcbnew/drc/drc_test_provider_misc.cpp:379
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msgid "Checking board outline..."
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msgstr "正在检查电路板边框..."
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msgstr "正在检查电路板外框..."
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#: pcbnew/drc/drc_test_provider_misc.cpp:387
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msgid "Checking disabled layers..."
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@ -38242,7 +38241,7 @@ msgstr "它们已被导出为椭圆焊盘。"
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#: pcbnew/exporters/step/exporter_step.cpp:382
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#: pcbnew/specctra_import_export/specctra_export.cpp:119
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msgid "Board outline is malformed. Run DRC for a full analysis."
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msgstr "PCB 轮廓异常, 请运行 DRC 来进行全面分析。"
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msgstr "PCB 外框异常, 请运行 DRC 来进行全面分析。"
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#: pcbnew/exporters/export_idf.cpp:653 pcbnew/exporters/export_idf.cpp:662
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#: pcbnew/exporters/export_idf.cpp:670
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@ -38339,7 +38338,7 @@ msgid ""
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"Check that the board has a valid outline and models."
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msgstr ""
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"无法创建 %s 文件。\n"
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"检查电路板是否具有有效的轮廓和模型。"
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"检查电路板是否具有有效的外框和模型。"
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#: pcbnew/exporters/step/exporter_step.cpp:571
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#, c-format
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